CN112528577A - Management method and device of clock reset circuit and computer storage medium - Google Patents
Management method and device of clock reset circuit and computer storage medium Download PDFInfo
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- CN112528577A CN112528577A CN201910823535.1A CN201910823535A CN112528577A CN 112528577 A CN112528577 A CN 112528577A CN 201910823535 A CN201910823535 A CN 201910823535A CN 112528577 A CN112528577 A CN 112528577A
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- G06F1/24—Resetting means
Abstract
The embodiment of the application discloses a management method and a management device of a clock reset circuit and a computer storage medium. The method comprises the following steps: acquiring a design file of a clock reset circuit; according to a preset basic function unit, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file; generating a global link table of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link table is description information of a link relation of the basic functional unit to the modules in the clock reset circuit; and generating a block diagram file of the clock reset circuit according to the global link table.
Description
Technical Field
The present invention relates to the field of information processing, and in particular, to a method and an apparatus for managing a clock reset circuit, and a computer storage medium.
Background
With the development of integrated circuit technology, the scale of circuit integration is getting larger and larger; the popularization of information and communication technology enables the application range of integrated circuits to be wider and wider, and the requirements tend to be diversified; the design of the integrated circuit is more and more complex, and the circuit design of multiple clock domains, multiple reset domains and multiple power domains is more and more common. With the demand for intellectualization and customization, the design of soc (system On chip) is becoming more and more common. In circuit design, particularly in SOC design, clock reset design is accompanied by multiple clock domains, the scale of the requirement of the multiple reset domains is larger and larger, and the complexity is higher and higher; meanwhile, the complexity of the clock reset Design is further aggravated by adding a DFT (Design For Test) technology. Due to the introduction of the SOC design, the clock reset can be configured dynamically, and the complexity is further increased.
The design of clock reset is related to whether the whole chip can be normally used, and a reliable verification means for clock reset becomes more and more important. At present, most verification means can monitor the quality of a clock signal, the quality of a reset signal, the influence of asynchronous clock design on a circuit, how to build a verification environment of the whole SOC system and the like in a centralized manner.
In circuit design, one Module is often designed for centrally managing the Clock Reset (CRM Clock Reset Module) of the system; the design conforms to the methodology of chip design, and the design is modularized and internalized; is adopted by most design manufacturers. For the design verification of the whole clock reset system, the following method is adopted in the related art:
1. the dynamic simulation mode is used for detecting the output condition of clock reset under different configurations of clock reset and checking the quality of the clock reset;
2. the manual inspection mode comprises the following steps: manual review, peer review code design; checking and confirming modes such as adding assertion to clock reset and the like;
3. and compiling the link relation of clock reset into an assertion, and checking through a formal verification tool.
The above method is a method widely applied in the industry, and a verification method using only a dynamic simulation method is not sufficient. For example, the sequential exchange of Buf and clock gating does not affect the output of the final clock, but may cause inconsistency with the original design; the manner in which the human or assertion is incorporated is necessary. The verification mode of the assertion requires that the manual writing of the link relation assertion and the manual Review have similar workload.
In the manual inspection process, the code design and connection condition needs to be analyzed manually line by line, or the inspection of the connection relation and the system block diagram of the clock reset design are compared by means of some universal tools (Verdi). On one hand, the operation mode is low in efficiency, and on the other hand, the general tool needs manual layer-by-layer tracking for clock reset links crossing layers.
Disclosure of Invention
In order to solve any one of the above technical problems, embodiments of the present application provide a method and an apparatus for managing a clock reset circuit, and a computer storage medium.
In order to achieve the object of the embodiment of the present application, an embodiment of the present application provides a management method for a clock reset circuit, including:
acquiring a design file of a clock reset circuit;
according to a preset basic function unit, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file;
generating global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of a link relation of the basic functional unit to the modules in the clock reset circuit;
and generating a block diagram file of the clock reset circuit according to the global link information.
In an exemplary embodiment, the generating global link information of the clock reset circuit according to the configuration information corresponding to each module includes:
generating link information based on a basic clock resetting unit corresponding to each module according to configuration information corresponding to each module, wherein the link information comprises link information of a port of each module and sub-modules in the module and link information between the sub-modules in the module;
determining one group or at least two groups of modules with link paths according to the link information corresponding to each module;
and processing the link information of one group or at least two groups of modules with link paths to obtain the global link information based on the basic clock resetting unit.
In an exemplary embodiment, the determining, according to the link information corresponding to each module, that one or at least two groups of modules exist in the link path includes:
acquiring name information of signals transmitted by ports in link information corresponding to each module;
inquiring whether a port for transmitting signals with the same name exists in the ports of the clock reset circuit;
after finding out the ports which have the signals with the same name, determining the target module corresponding to the ports, and taking the target module as a group of modules with link paths.
In an exemplary embodiment, after generating the block diagram file of the clock reset circuit according to the global link information, the method further includes:
acquiring a checking strategy for a clock reset circuit;
and checking the design information described in the block diagram file according to the detection strategy.
In an exemplary embodiment, after generating the block diagram file of the clock reset circuit according to the global link information, the method further includes:
acquiring a debugging strategy for a clock reset circuit;
and modifying the design information described in the block diagram file according to the debugging strategy.
A management apparatus for a clock reset circuit, comprising a processor and a memory, wherein the memory stores a computer program, and the processor calls the computer program in the memory to implement operations comprising:
acquiring a design file of a clock reset circuit;
according to a preset basic function unit, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file;
generating global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of a link relation of the basic functional unit to the modules in the clock reset circuit;
and generating a block diagram file of the clock reset circuit according to the global link information.
In an exemplary embodiment, the processor calls a computer program in the memory to implement the operation of generating global link information of the clock reset circuit according to the configuration information corresponding to each module, including:
generating link information based on a basic clock resetting unit corresponding to each module according to configuration information corresponding to each module, wherein the link information comprises link information of a port of each module and sub-modules in the module and link information between the sub-modules in the module;
determining one group or at least two groups of modules with link paths according to the link information corresponding to each module;
and processing the link information of one group or at least two groups of modules with link paths to obtain the global link information based on the basic clock resetting unit.
In an exemplary embodiment, the processor calls a computer program in the memory to implement the operation of determining that a link path exists in one or at least two groups of modules according to the link information corresponding to each module, including:
acquiring name information of signals transmitted by ports in link information corresponding to each module;
inquiring whether a port for transmitting signals with the same name exists in the ports of the clock reset circuit;
after finding out the ports which have the signals with the same name, determining the target module corresponding to the ports, and taking the target module as a group of modules with link paths.
In an exemplary embodiment, after the processor calls the computer program in the memory to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement the following operations, including:
acquiring a checking strategy for a clock reset circuit;
and checking the design information described in the block diagram file according to the detection strategy.
In an exemplary embodiment, after the processor calls the computer program in the memory to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement the following operations, including:
acquiring a debugging strategy for a clock reset circuit;
and modifying the design information described in the block diagram file according to the debugging strategy.
A computer storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement any of the methods described above.
The embodiments provided in the embodiments of the present application,
additional features and advantages of the embodiments of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the examples of the embodiments of the present application do not constitute a limitation of the embodiments of the present application.
Fig. 1 is a flowchart of a management method of a clock reset circuit according to an embodiment of the present disclosure;
fig. 2 is a structural diagram of a management apparatus of a clock reset circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a computer storage medium provided in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, in the embodiments of the present application, features in the embodiments and the examples may be arbitrarily combined with each other without conflict.
Fig. 1 is a flowchart of a management method of a clock reset circuit according to an embodiment of the present disclosure. The method shown in fig. 1, comprising:
102, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file according to a preset basic function unit;
in an exemplary embodiment, the configuration information for each module is determined by the name of each module, and the configuration information includes at least one of: the name of the signal linked by the port, the input and output attributes of the port, the instantiation name of the sub-module instantiated in the module, the definition name of the module, the port name of the module and the instantiation link name of the port;
in one example embodiment, the basic functional unit may be a clock buffer (Buf), clock gating, clock divider, clock multiplexer, DFT clock buffer, reset controller, or the like;
103, generating global link information of the clock reset circuit according to configuration information corresponding to each module, wherein the global link information is description information of a link relation of the basic functional unit to the modules in the clock reset circuit;
in one exemplary embodiment, the configuration information describes the components included inside by using a clock reset circuit in the basic functional unit; determining the link information of the basic function unit and determining the link relation of components in the clock reset circuit by using the configuration information and the port information in the configuration information;
and step 104, generating a block diagram file of the clock reset circuit according to the global link information.
According to the method provided by the embodiment of the application, the design file of the clock reset circuit is obtained, the configuration information of the ports and the sub-modules in each module in the clock reset circuit is obtained from the design file according to the preset basic function units, the global link information of the clock reset circuit is generated according to the configuration information corresponding to each module, and the block diagram file of the clock reset circuit is generated according to the global link information, so that the purpose of automatically generating the clock reset block diagram is achieved, and the problem that the manual block diagram drawing time in the related technology is long is solved.
The method provided by the embodiments of the present application is explained as follows:
in an exemplary embodiment, the generating global link information of the clock reset circuit according to the configuration information corresponding to each module includes:
generating link information based on a basic clock resetting unit corresponding to each module according to configuration information corresponding to each module, wherein the link information comprises link information of a port of each module and sub-modules in the module and link information between the sub-modules in the module;
determining one group or at least two groups of modules with link paths according to the link information corresponding to each module;
and processing the link information of one group or at least two groups of modules with link paths to obtain the global link information based on the basic clock resetting unit.
Determining sub-modules connected with the ports according to configuration information of the ports in the modules, and determining link information between the sub-modules according to names of signals between the sub-modules by means of the ports to obtain the link information of each module; determining one group or at least two groups of modules with link paths by means of the characteristics of signals transmitted among the modules after obtaining the link information of each module; and after the link relation between the modules is determined, iterating the links of the modules to obtain the global link information of the clock reset circuit.
In an exemplary embodiment, the determining, according to the link information corresponding to each module, that one or at least two groups of modules exist in the link path includes:
acquiring name information of signals transmitted by ports in link information corresponding to each module;
inquiring whether a port for transmitting signals with the same name exists in the ports of the clock reset circuit;
after finding out the ports which have the signals with the same name, determining the target module corresponding to the ports, and taking the target module as a group of modules with link paths.
When designing the clock reset circuit, an instantiated name of the transmission signal is set for the port of the module to distinguish the transmitted signal. When the link information between the modules is determined, the names of the signals transmitted by the ports can be used for determining the connected modules, so that the purpose of automatically acquiring the link information between the modules is achieved by skillfully utilizing the information on the basis of utilizing the existing information.
In an exemplary embodiment, after generating the block diagram file of the clock reset circuit according to the global link information, the method further includes:
acquiring a checking strategy for a clock reset circuit;
and checking the design information described in the block diagram file according to the detection strategy.
The checking policy may be a user-entered checking rule, e.g., clock gating is placed in front of the divider; reset needs to pass through output, etc.; after obtaining the checking strategy, analyzing a structure diagram defined by the checking strategy; the structure diagram can be obtained by analysis, the obtained block diagram file is compared, the design is checked, and the violation part in the block diagram file is output.
And after the violation part in the block diagram file is output, receiving the violation part selected by the user, and modifying the violation part according to the structure diagram corresponding to the check rule.
In an exemplary embodiment, after generating the block diagram file of the clock reset circuit according to the global link information, the method further includes:
acquiring a debugging strategy for a clock reset circuit;
and modifying the design information described in the block diagram file according to the debugging strategy.
The debugging strategy is used for confirming whether the clock or the reset can work normally in the chip;
after the debugging strategy is obtained, the clock reset signal can be set to the pin of the chip for observation, the MUX design of automatically adding the clock for debugging and resetting is realized, and the design efficiency is improved.
The method provided by the embodiments of the present application is explained as follows:
in order to solve at least one of the problems existing in the prior art that the efficiency of manually tracking codes is not high and the problem that the auxiliary tracking of a circuit diagram is inconvenient to use for a multi-level clock reset design, the embodiment of the present application provides the following solutions, including:
in one example embodiment, the basic functional unit may be a clock buffer (Buf), clock gating, clock divider, clock multiplexer, DFT clock buffer, reset controller, or the like;
in an exemplary embodiment, the design files for the clock reset circuit may be in HDL format or verilog format.
In one exemplary embodiment, the HDL file is analyzed through a regular expression, and required information in the HDL file is extracted.
In an exemplary embodiment, the configuration information of the ports and the sub-modules may be obtained by the following methods, including:
clearing annotation content in the description information of the module in the design file to remove invalid information;
extracting the name information of the module, the name information of the signal transmitted by the port and the input and output attributes of the port; extracting instantiation names of instantiated sub-modules in the module, definition names of the modules, port names of the modules and instantiation link names of the ports; and in the same way, traversing all modules of the clock reset design until the basic functional unit is analyzed, and stopping analyzing the internal design.
Step 203, determining a global link table based on a basic clock reset unit of the clock reset circuit according to the configuration information of the port and the sub-module corresponding to each module; the global link table comprises link information of a port and a sub-module of each module and link information between sub-modules in each module;
in an exemplary embodiment, the global link relationship is continuously iterated based on the example name matching of the port links. For example, if the port 1 of the module 1 and the port 1 of the module 2 transmit signals with the same example name, and the port 2 of the module 2 and the port 1 of the module 3 transmit signals with the same example name, it may be determined that the module 1, the module 2, and the module 3 are sequentially connected by iterating the link information of the above 3 modules.
In step D, the display is carried out through a graphic language; step 204, processing the global link table by using a preset graph generation strategy to obtain a design block diagram file corresponding to the global link table;
in an exemplary embodiment, the global link table is a generated clock reset block diagram which can be correspondingly generated by using the icons of the basic clock reset units stored in the graph generation strategy based on the link information described by the basic clock reset units.
In one exemplary embodiment, a SVG-based graphics system can be used, displayed into HTML, opened through a browser.
After obtaining the block diagram file, the block diagram file may be used for any one of the following uses, including:
the output block diagram can be delivered to a chip product as a design manual, and compared with the manual drawing block diagram: by adopting the block diagram output by the method provided by the embodiment of the application, more regular drawing styles can be ensured, or display effects with different detailed degrees can be customized according to requirements, so that different requirements can be met; such as a hidden clock BUF, a reset source of a display clock divider, etc.
Manually comparing the generated block diagram file with a block diagram file designed and used by a clock resetting system; the generated block diagram has high similarity with the block diagram used for design, so that comparison is convenient, and the efficiency of manual inspection is improved.
Whether a violation exists in the design can be detected according to a design rule defined by a user; for example, if all resets need to be synchronized with the clock, it is detected whether the reset signal passes through the synchronizer, otherwise an error is reported, the design engineer is guided to design, or the synchronizer is automatically added according to the operation request of the user.
After the clock reset design is completed, in order to confirm whether the clock or reset can work normally in the chip, a clock reset signal is sent to a pin of the chip for observation. By using the invention, according to the clock and the reset signal specified by the use case, the MUX logic of the clock signal and the reset signal is added in the design, thereby realizing the purpose of automatically adding the MUX design of the clock and the reset for debugging, and improving the design efficiency.
Compared with the prior art, the method provided by the embodiment of the application achieves the progress of a method for verifying the clock reset system, achieves the effect of perfecting the clock reset verification, saves the verification time of the clock reset system, and improves the efficiency of the clock reset verification; and the design of automatically adding debugging logic brings objective beneficial effects to the test and use of the chip.
Fig. 2 is a structural diagram of a management apparatus of a clock reset circuit according to an embodiment of the present application. The apparatus shown in fig. 2 comprises a processor 201 and a memory 202, wherein the memory 202 stores a computer program, and the processor 201 calls the computer program in the memory 202 to implement the following operations, including:
acquiring a design file of a clock reset circuit;
according to a preset basic function unit, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file;
generating global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of a link relation of the basic functional unit to the modules in the clock reset circuit;
and generating a block diagram file of the clock reset circuit according to the global link information.
In an exemplary embodiment, the processor 201 calls a computer program in the memory 202 to implement the operation of generating the global link information of the clock reset circuit according to the configuration information corresponding to each module, including:
generating link information based on a basic clock resetting unit corresponding to each module according to configuration information corresponding to each module, wherein the link information comprises link information of a port of each module and sub-modules in the module and link information between the sub-modules in the module;
determining one group or at least two groups of modules with link paths according to the link information corresponding to each module;
and processing the link information of one group or at least two groups of modules with link paths to obtain the global link information based on the basic clock resetting unit.
In an exemplary embodiment, the processor 201 calls a computer program in the memory 202 to implement the operation of determining that there are one or at least two groups of modules of a link path according to the link information corresponding to each module, including:
acquiring name information of signals transmitted by ports in link information corresponding to each module;
inquiring whether a port for transmitting signals with the same name exists in the ports of the clock reset circuit;
after finding out the ports which have the signals with the same name, determining the target module corresponding to the ports, and taking the target module as a group of modules with link paths.
In an exemplary embodiment, after the processor 201 calls the computer program in the memory 202 to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor 201 calls the computer program in the memory 202 to further implement the following operations, including:
acquiring a checking strategy for a clock reset circuit;
and checking the design information described in the block diagram file according to the detection strategy.
In an exemplary embodiment, after the processor 201 calls the computer program in the memory 202 to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor 201 calls the computer program in the memory 202 to further implement the following operations, including:
acquiring a debugging strategy for a clock reset circuit;
and modifying the design information described in the block diagram file according to the debugging strategy.
The device provided by the embodiment of the application acquires a design file of a clock reset circuit, acquires configuration information of ports and sub-modules in each module in the clock reset circuit from the design file according to a preset basic function unit, generates a global link table of the clock reset circuit according to the configuration information corresponding to each module, and generates a block diagram file of the clock reset circuit according to the global link table, so that the purpose of automatically generating a clock reset block diagram is achieved, and the problem of long time for manually drawing the block diagram in the related art is solved.
FIG. 3 is a schematic diagram of a computer storage medium provided in an embodiment of the present application. The computer-readable storage medium of fig. 3 stores one or more programs that are executable by one or more processors to implement any of the methods described above.
The computer storage medium provided in the embodiment of the present application obtains a design file of a clock reset circuit, obtains configuration information of a port and a sub-module in each module in the clock reset circuit from the design file according to a preset basic function unit, generates a global link table of the clock reset circuit according to the configuration information corresponding to each module, and generates a block diagram file of the clock reset circuit according to the global link table, thereby achieving the purpose of automatically generating a clock reset block diagram, and overcoming the problem of long time for manually drawing the block diagram in the related art.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Claims (11)
1. A method of managing a clock reset circuit, comprising:
acquiring a design file of a clock reset circuit;
according to a preset basic function unit, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file;
generating global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of a link relation of the basic functional unit to the modules in the clock reset circuit;
and generating a block diagram file of the clock reset circuit according to the global link information.
2. The method of claim 1, wherein the generating global link information of the clock reset circuit according to the configuration information corresponding to each module comprises:
generating link information based on a basic clock resetting unit corresponding to each module according to configuration information corresponding to each module, wherein the link information comprises link information of a port of each module and sub-modules in the module and link information between the sub-modules in the module;
determining one group or at least two groups of modules with link paths according to the link information corresponding to each module;
and processing the link information of one group or at least two groups of modules with link paths to obtain the global link information based on the basic clock resetting unit.
3. The method according to claim 2, wherein the determining, according to the link information corresponding to each module, one or at least two groups of modules where a link path exists comprises:
acquiring name information of signals transmitted by ports in link information corresponding to each module;
inquiring whether a port for transmitting signals with the same name exists in the ports of the clock reset circuit;
after finding out the ports which have the signals with the same name, determining the target module corresponding to the ports, and taking the target module as a group of modules with link paths.
4. The method of claim 1, wherein after generating a block diagram file of the clock reset circuit according to the global link information, the method further comprises:
acquiring a checking strategy for a clock reset circuit;
and checking the design information described in the block diagram file according to the detection strategy.
5. The method of claim 1, wherein after generating a block diagram file of the clock reset circuit according to the global link information, the method further comprises:
acquiring a debugging strategy for a clock reset circuit;
and modifying the design information described in the block diagram file according to the debugging strategy.
6. A management apparatus for a clock reset circuit, comprising a processor and a memory, wherein the memory stores a computer program, and the processor calls the computer program in the memory to implement operations comprising:
acquiring a design file of a clock reset circuit;
according to a preset basic function unit, acquiring configuration information of ports and sub-modules in each module in the clock reset circuit from the design file;
generating global link information of the clock reset circuit according to the configuration information corresponding to each module, wherein the global link information is description information of a link relation of the basic functional unit to the modules in the clock reset circuit;
and generating a block diagram file of the clock reset circuit according to the global link information.
7. The apparatus of claim 6, wherein the processor invokes a computer program in the memory to perform operations for generating global link information for the clock reset circuit according to the configuration information corresponding to each module, comprising:
generating link information based on a basic clock resetting unit corresponding to each module according to configuration information corresponding to each module, wherein the link information comprises link information of a port of each module and sub-modules in the module and link information between the sub-modules in the module;
determining one group or at least two groups of modules with link paths according to the link information corresponding to each module;
and processing the link information of one group or at least two groups of modules with link paths to obtain the global link information based on the basic clock resetting unit.
8. The apparatus of claim 7, wherein the processor calls a computer program in the memory to implement the operation of determining that there are one or at least two groups of modules of the link path according to the link information corresponding to each module, comprising:
acquiring name information of signals transmitted by ports in link information corresponding to each module;
inquiring whether a port for transmitting signals with the same name exists in the ports of the clock reset circuit;
after finding out the ports which have the signals with the same name, determining the target module corresponding to the ports, and taking the target module as a group of modules with link paths.
9. The apparatus of claim 6, wherein after the processor calls the computer program in the memory to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement operations comprising:
acquiring a checking strategy for a clock reset circuit;
and checking the design information described in the block diagram file according to the detection strategy.
10. The apparatus of claim 6, wherein after the processor calls the computer program in the memory to implement the operation of generating the block diagram file of the clock reset circuit according to the global link information, the processor calls the computer program in the memory to further implement operations comprising:
acquiring a debugging strategy for a clock reset circuit;
and modifying the design information described in the block diagram file according to the debugging strategy.
11. A computer storage medium, the computer readable storage medium storing one or more programs, the one or more programs being executable by one or more processors to perform the method of any of claims 1 to 5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114356436A (en) * | 2021-12-08 | 2022-04-15 | 北京爱芯科技有限公司 | Clock and reset excitation method, device and storage medium |
| CN114356436B (en) * | 2021-12-08 | 2024-04-19 | 北京爱芯科技有限公司 | Clock and reset excitation method, device and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114356436A (en) * | 2021-12-08 | 2022-04-15 | 北京爱芯科技有限公司 | Clock and reset excitation method, device and storage medium |
| CN114356436B (en) * | 2021-12-08 | 2024-04-19 | 北京爱芯科技有限公司 | Clock and reset excitation method, device and storage medium |
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