CN112527239A - Floating point data processing method and device - Google Patents

Floating point data processing method and device Download PDF

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CN112527239A
CN112527239A CN202110182926.7A CN202110182926A CN112527239A CN 112527239 A CN112527239 A CN 112527239A CN 202110182926 A CN202110182926 A CN 202110182926A CN 112527239 A CN112527239 A CN 112527239A
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floating point
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CN112527239B (en
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郇丹丹
赵继业
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Beijing Micro Core Technology Co ltd
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Abstract

The application provides a floating point data processing method and a device, and the method comprises the following steps: when floating point data are input to a floating point register file unit by a unit except a floating point arithmetic unit and a floating point register file unit, performing first processing on the floating point data to convert the format of the floating point data from a floating point original format to a floating point internal format; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format; and performing floating-point operation on floating-point data with a format of a floating-point internal format in the floating-point register file unit by using the floating-point operation unit to obtain an operation result, wherein the format of the operation result is the floating-point internal format, and the formats of the floating-point data are all the floating-point internal formats when the floating-point operation unit operates the floating-point data. The method provided by the application has the advantages of high efficiency, low cost and low complexity.

Description

Floating point data processing method and device
Technical Field
The present application relates to the field of computer processors, and in particular, to a floating-point data processing method and apparatus.
Background
Floating point arithmetic units are typically provided in high performance processors to perform floating point operations on floating point numbers. The floating point number mainly comprises a sign bit S, an order code Exp and a Mantissa, wherein the sign bit is used for representing the positive and negative of the floating point number, the order code is used for representing the position of a decimal point in the number and is an integer with a sign, and the Mantissa is used for representing the effective numerical value of the number. For example, in the IEEE754 standard, sign bits are used to represent positive and negative of floating-point numbers, and the codes adopt the shape of a shift codeThe mantissa is represented by the original code. Meanwhile, the floating point number further includes a plurality of formats, which are respectively: normalized number, denormalized number, positive and negative zeros, positive and negative infinity, and not-number. Positive and negative zero, positive and negative infinity, and non-numbers are collectively referred to as special numbers. Wherein, the order code and the mantissa of positive and negative zeros are all 0; the positive and negative infinite order codes are all 1's and the mantissas are all 0's; the non-number order codes are all 1's and the mantissa is not 0; the order code of the denormal number is all 0 and the mantissa is not 0; the remaining cases represent normalized numbers. Wherein, for the normalized number, the corresponding decimal Value1 can be represented as: value1= (-1)s×1.Mantissa×2Exp-Bias(ii) a For denormals, its corresponding decimal Value2 may be expressed as: value2= (-1)s×0.Mantissa×2Exp-Bias+1(ii) a Bias primarily indicates a level offset, for a single precision type of floating point number, Bias is 127; for a double precision type of floating point number, the Bias is 1023.
The floating-point operation unit is mainly used for performing floating-point operation on the floating-point number with the format of a normalized number. When the operation result obtained by the floating-point operation unit operating on the floating-point number is small and smaller than the minimum value that can be indicated by the normalization number, the operation result needs to be represented by the denormal number. And, because the floating-point operation unit is mainly used for processing the normalized number, and the difficulty of performing unified processing on the denormal number is high, when the subsequent floating-point operation unit needs to perform further floating-point operation on the operation result in the denormal number format, it needs to perform special processing on the denormal number, and specifically, the following processing methods may be included:
the method I is to simulate an unnormalized number by software to calculate.
And when the operation result output by the floating point operation unit is smaller and cannot be represented by the normalized number, the floating point operation unit outputs the operation result after the denormalization processing.
For the first method, the floating-point operation efficiency is greatly reduced when software is used for denormal number operation. For the second method, bubbles are formed in the pipeline, so that the number of instructions executed in each clock cycle is reduced, and the pipeline of one clock cycle is blocked, so that the data cannot be processed in full flow, the control complexity is increased, and the performance of the processor is reduced. And, a high performance processor generally includes a plurality of floating point arithmetic units such as a floating point multiply-add unit, a floating point comparison unit, a floating point division unit, and an open-square unit, so that it is necessary to add a normalization processing block at an input terminal of each floating point arithmetic unit in order to normalize an unnormal number when input data of the floating point arithmetic unit is an unnormal number, and to add a denormal processing block at an output terminal of each floating point arithmetic unit in order to denormal an arithmetic result obtained by the floating point arithmetic unit when the arithmetic result is small and cannot be represented by a normalized number. Thus, hardware resources are consumed, increasing power consumption and area and cost of the processor.
Disclosure of Invention
The application provides a floating point data processing method and a floating point data processing device, which at least solve the technical problems of complexity, low efficiency, long time consumption and high cost of the floating point data processing method in the related technology.
An embodiment of a first aspect of the present application provides a floating point data processing method, including:
when floating point data are input to a floating point register file unit by a unit except a floating point arithmetic unit and a floating point register file unit, performing first processing on the floating point data to convert the format of the floating point data from a floating point original format to a floating point internal format; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format;
and performing floating-point operation on floating-point data with a format of a floating-point internal format in the floating-point register file unit by using the floating-point operation unit to obtain an operation result, wherein the format of the operation result is the floating-point internal format, and the formats of the floating-point data are all the floating-point internal formats when the floating-point operation unit operates the floating-point data.
An embodiment of a second aspect of the present application provides a floating point data processing apparatus, including:
the first conversion module is used for performing first processing on the floating point data to convert the format of the floating point data from a floating point original format to a floating point internal format when the floating point data is input to the floating point register file unit by a unit except the floating point arithmetic unit; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the original format;
the floating-point register file unit is connected with the first conversion module and used for storing floating-point data with a format of a floating-point internal format;
the floating-point operation unit is connected with the floating-point register file unit and is used for performing floating-point operation on floating-point data stored in the floating-point register file unit to obtain an operation result and inputting the operation result into the floating-point register file unit for storage, wherein the operation result is in a floating-point internal format, and when the floating-point operation unit operates on the floating-point data, the floating-point data is in the floating-point internal format; and when the operation result is transmitted to the floating-point register file unit for storage by the floating-point operation unit, the format of the operation result is not converted.
The technical scheme provided by the embodiment of the application at least has the following beneficial effects:
first, in the floating point data processing method provided by the present application, before floating point data is input to the floating point register file unit from a unit other than the floating point arithmetic unit and the floating point register file unit, a single bit is added to a stage code of the floating point data to convert a floating point native format into a floating point internal format, and when floating point data in the floating point register file unit is output to a unit other than the floating point arithmetic unit and the floating point register file unit, a single bit is removed from the stage code of the floating point data to convert the floating point internal format into the floating point native format. Therefore, the formats of the floating point data in the floating point register file unit and the floating point data in the floating point operation unit are always in a floating point internal format. And because the order code of the floating point data under the floating point internal format is increased by one bit, the range of the value which can be indicated by the order code is larger, even if the operation result obtained by the floating point operation unit based on the floating point data in the floating point register file unit is smaller, the operation result can be represented by the floating point internal format, and the format of the operation result does not need to be converted, so that the efficiency of the floating point operation can be improved.
And secondly, when the format of the floating point data is converted from the original floating point format to the original floating point format and the format of the operation result is converted from the original floating point format to the original floating point format, the method does not need to block a pipeline, so that the execution time can be reduced, the full-pipeline processing can be realized, the control complexity is reduced, and the efficiency of the floating point operation is improved.
Third, format conversion is only needed to be performed when the floating-point register file unit enters and exits, and because the formats of the floating-point data inside the floating-point register file unit and the floating-point data inside the floating-point operation unit are always in the floating-point internal format, format conversion is not needed, so that a format conversion module does not need to be arranged at the entrance and exit end of each floating-point operation unit, and a format conversion module only needs to be arranged at the entrance and exit end of the floating-point register file unit, so that the performance is improved, the power consumption and the hardware area are reduced, and the cost is reduced.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart illustrating a floating point data processing method according to an embodiment of the present application;
FIG. 2 is a block diagram of a floating-point data processing apparatus according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of another floating-point data processing apparatus according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.
In the floating point data processing method, when floating point data is input to a floating point register file unit by a unit except a floating point arithmetic unit and a floating point register file unit, first processing is performed on the floating point data so as to convert the format of the floating point data from a floating point original format to a floating point internal format; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format;
then, the floating-point operation unit performs a floating-point operation on the floating-point data in the floating-point register file unit, where the floating-point data is in a floating-point internal format, so as to obtain an operation result, where the operation result is in the floating-point internal format, and when the floating-point operation unit performs an operation on the floating-point data, the floating-point data is in the floating-point internal format.
Therefore, in the embodiment of the application, when floating point data is subjected to floating point operation in the floating point operation unit, the format of the floating point data is always the internal format of the floating point, and the format conversion is not needed, so that the efficiency of the floating point operation can be improved. In addition, a format conversion module does not need to be arranged at the input/output port of each floating-point operation unit, so that the performance is improved, the power consumption is reduced, the area is saved, and the cost is reduced.
The floating-point data processing method and apparatus according to the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Example one
Fig. 1 is a schematic flowchart of a floating point data processing method according to an embodiment of the present application, and as shown in fig. 1, the method may include:
step 100, floating point data is input to the floating point register file unit.
The floating point data may be input to the floating point register file unit from a unit, such as a memory unit, a fixed point register file unit, or a vector register file unit, except for the floating point arithmetic unit and the floating point register file unit, and may specifically include three parts, namely a sign bit S for indicating the positive and negative of a floating point number, an order code Exp for indicating the position of a decimal point in the number, which is a signed integer, and a Mantissa for indicating the significant value of the number. And the floating point data has a floating point primitive format, which may be a floating point data format satisfying IEEE754 standard, in which a sign bit is used to represent positive and negative of a floating point number, when the sign bit S is 1, a negative number is represented, and when the sign bit S is 0, a positive number is represented; the order code is represented by a code shift form, and the mantissa is represented by an original code. For example, the floating point primitive format may include: normalized number, denormal number, positive and negative zero, positive and negative infinity, and a non-number, wherein positive and negative zero, positive and negative infinity, and a non-number are collectively referred to as a special number. The floating point data may also include a single precision type and a double precision type. Table 1 is a bit width schematic table of single-precision floating point data and double-precision floating point data in the floating point primitive format.
TABLE 1
Type (B) Sign bit width Bit width of code Mantissa bit width Total bit width Rank offset Bias Maximum order code Minimum order code
Single precision 1 8 23 32 127 +127 -126
Double precision 1 11 52 64 1023 +1023 -1022
As shown in Table 1, the single precision type floating point data in the native format has a code bit width of 8bits, a mantissa bit width of 23bits, and a code offset of 127. The double precision type floating point data in the floating point primitive format has an order bit width of 11bits, a mantissa bit width of 52bits, and an order offset of 1023.
Further, the floating-point register file unit may be connected to at least one floating-point arithmetic unit, and the floating-point arithmetic unit may be a floating-point multiply-add unit, a floating-point comparison unit, a floating-point division unit, or a square-on unit. After the floating-point data is input to the floating-point register file unit, the floating-point arithmetic unit may perform a floating-point operation on the floating-point data in the floating-point register file unit to obtain an arithmetic result, and return the arithmetic result to the floating-point register file unit for storage.
Step 200, when floating point data are input to a floating point register file unit by a unit except a floating point arithmetic unit and a floating point register file unit, performing first processing on the floating point data to convert the format of the floating point data from a floating point original format to a floating point internal format.
It should be noted that, in the present embodiment, the conversion only converts the format of the floating point data, and does not change the type of the floating point data (for example, a double precision type or a single precision type).
In this embodiment, when the floating point primitive formats of the floating point data are different, the first processing is also different. The first processing is described by taking the floating-point primitive format as normalized number, denormal number, special number positive and negative zero, positive and negative infinity, and non-number as examples.
Specifically, when the floating-point primitive format of the floating-point data satisfies IEEE754 standards and the floating-point data is input to the floating-point register file unit by a unit other than the floating-point arithmetic unit and the floating-point register file unit, the first processing includes: and increasing the code of the floating point data in the floating point original format by one bit.
Wherein, when the floating point primitive format of the floating point data is a normalized number, the first processing includes: and setting the step codes of the floating point data in the internal format as binary numbers corresponding to the sum of the set value and the floating point original format step codes. The value rule of the set value comprises the following steps: the set value is a decimal number, and the set value is equal to 129 when the type of the floating point data is single precision; when the type of the floating point data is double precision, the set value is 1025.
For the example, for a raw format of floating point as normalized single precision floating point data, assume that the normalized single precision floating point data is as shown in Table 2.
TABLE 2
Sign bit 1bit Code 8bits Mantissa 23bits
0 100 0001 0 011 0110 0000 0000 0000 0000
As shown in Table 2, the normalized single precision floating point data has a sign bit of 0, a level code of 10000010, and a mantissa of 01101100000000000000000. The first processing performed on the normalized single precision floating point data should be: the highest bit of the level 10000010 is increased by one bit 0, the level of the floating point data in the internal format is set to be the binary number 010000001 of the setting value 129 and the binary number corresponding to the sum of the 010000010 obtained after the highest bit of the level is increased by one bit 0, that is, the binary number corresponding to the level in the floating point internal format is: 010000001+010000010= 100000011. The single-precision floating point data in the floating point internal format obtained after the first processing is performed on the normalized single-precision floating point data shown in table 2 may be as shown in table 3.
TABLE 3
Sign bit 1bit 9bits of code Mantissa 23bits
0 1000 0001 1 011 0110 0000 0000 0000 0000
Referring to table 3, the stage code of the single-precision floating point data in the floating-point internal format obtained after the first processing is performed on the normalized single-precision floating point data shown in table 2 becomes 100000011, and the sign bit and the mantissa do not change.
And, for the original format of floating point as normalized double precision floating point data, assume that the normalized double precision floating point data is as shown in Table 4.
TABLE 4
Sign bit 1bit Code 11bits Mantissa 52bits
1 100 0001 0000 0001 0000 1110 0000 1010 0101 0000 0011 0110 0000 0000 0000 0000
As shown in Table 4, the normalized double precision floating point data has a sign bit of 1, a level code of 10000010000, and a mantissa of 0001000011100000101001010000001101100000000000000000. The first processing performed on the normalized double precision floating point data should be: the most significant bit of the level 10000010000 is increased by one bit 0, and the level of the floating point data in internal format is set to the binary number 010000000001 corresponding to the setting value 1025 and the binary number corresponding to the sum of 010000010000 obtained after the most significant bit of the level is increased by one bit 0, i.e. the binary number corresponding to the level in floating point internal format is: 010000000001+010000010000= 100000010001. The double-precision floating point data in the floating-point internal format obtained after the first processing is performed on the normalized double-precision floating point data shown in table 4 may be as shown in table 5.
TABLE 5
Sign bit 1bit Code 12bits Mantissa 52bits
1 1000 0001 0001 0001 0000 1110 0000 1010 0101 0000 0011 0110 0000 0000 0000 0000
Referring to table 5, the carry code of the double-precision floating point data in the floating-point internal format obtained after the first processing is performed on the normalized double-precision floating point data shown in table 4 becomes 100000010001, and the sign bit and the mantissa do not change.
Exemplary floating point primitive formats for normalized positive numbers of maximum and minimum single and double precisions are shown in table 6, respectively.
TABLE 6
Floating point primitive format Sign bit: 1bit order code single precision: 8bits double precision: 11bits mantissa single precision: 23bits double precision: 52bits
Minimum single precision normalized floating point correction Number of 0 000 0000 1 000 0000 0000 0000 0000 0001
Maximum single precision normalized floating point correction Number of 0 111 1111 0 111 1111 1111 1111 1111 1111
Minimum double precision normalized floating point norm Number of 0 000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
Maximum double precision normalized floating point correction Number of 0 111 1111 1110 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
The floating-point internal format of the converted normalized positive numbers of single and double precision for the maximum and minimum values after the first processing is performed is shown in table 7.
TABLE 7
Floating point internal format Sign bit: 1bit order code single precision: 9bits double precision: 12bits mantissa single precision: 23bits double precision: 52bits
Minimum single precision normalized floating point correction Number of 0 0100 0001 0 000 0000 0000 0000 0000 0001
Maximum single precision normalized floating point correction Number of 0 1011 1111 1 111 1111 1111 1111 1111 1111
Minimum double precision normalized floating point norm Number of 0 0100 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
Maximum double precision normalized floating point correction Number of 0 1011 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Further, when the floating point primitive format of the floating point data input to the floating point register file unit by the unit other than the floating point arithmetic unit and the floating point register file unit is an denormal number, the first processing includes: and performing left shift of a first preset digit by using 0 on the mantissa of the floating point data in the floating point original format, wherein the first preset digit is the number of zeros of the mantissa of the floating point data in the floating point original format before the first 1 of the mantissa of the floating point data in the first digit plus one, so as to shift out the first 1 of the mantissa. And taking a binary number corresponding to the difference value between the set value and the first preset digit as a new level code of the floating point data in the floating point internal format, wherein the bit width of the new level code is the level code bit width of the floating point data in the floating point original format plus one.
For the example, for a floating point primitive format of denormal single precision floating point data, assume that the denormal single precision floating point data is as shown in table 8.
TABLE 8
Sign bit 1bit Code 8bits Mantissa 23bits
1 000 0000 0 100 0000 0000 1000 0000 0000
As shown in Table 8, the denormal single-precision floating-point data has a sign bit of 1, a level bit of 8bits, a level of 00000000, and a mantissa of 10000000000100000000000. Then the first processing performed on the denormal single-precision floating-point data should be: left-shifting the mantissa 10000000000100000000000 by 0 for a first preset number of bits, which is the number of zeros of the mantissa 10000000000100000000000 that precede the first 1 of the leading number by one, i.e., the first preset number of bits is 1; then left shifting the mantissa 10000000000100000000000 by 0 to 1bit results in a new mantissa 00000000001000000000000. And taking a binary number corresponding to the difference value (i.e. 128) between the set value 129 and the first preset number of bits 1 as a new step code, and if the bit width of the new step code is the step code bit width of the floating point data in the original floating point format plus one, the bit width of the new step code is 9bits, so that the new step code is 010000000, and then determining the floating point data in the floating point internal format corresponding to the floating point data shown in table 8 based on the new step code and the new mantissa. The floating point data in the floating point internal format obtained after the first processing is performed on the denormal single-precision floating point data shown in table 8 may be as shown in table 9.
TABLE 9
Sign bit 1bit 9bits of code Mantissa 23bits
1 0100 0000 0 000 0000 0001 0000 0000 0000
Referring to table 9, the mantissa of the new stage of the floating point data in the floating point internal format obtained after the first processing is performed on the normalized single-precision floating point data shown in table 8 becomes 9bits, and the sign bit remains unchanged, with the new stage being 010000000 and the new mantissa being 00000000001000000000000.
And, for the original format of floating point being denormal double precision floating point data, assume that the denormal double precision floating point data is as shown in Table 10.
Watch 10
Sign bit 1bit Code 11bits Mantissa 52bits
0 000 0000 0000 0001 0100 1100 0010 1111 0000 0100 0000 0000 0000 0000 0000 1010
As shown in Table 10, the denormal double precision floating point data has a sign bit of 0, a level bit of 11bits, a level of 00000000000, and a mantissa of 0001010011000010111100000100000000000000000000001010. And, the first processing performed on the denormalized double precision floating point data should be: shifting the mantissa 0001010011000010111100000100000000000000000000001010 left by 0 for a first preset number of bits, where the first preset number of bits is the number of zeros of the mantissa 0001010011000010111100000100000000000000000000001010 before the first 1 of the leading number plus one, that is, the first preset number of bits is 4, and then shifting the mantissa 0001010011000010111100000100000000000000000000001010 left by 0 for 4 bits to obtain a new mantissa 0100110000101111000001000000000000000000000010100000. And taking a binary number corresponding to the difference value (namely 1021) between the set value 1025 and the first preset digit 4 as a new level code, wherein the bit width of the new level code is the level code bit width of the floating point data in the floating point original format plus one, namely the bit width of the new level code is 12bits, so that the new level code is 001111111101, and then, based on the new level code and the new mantissa, the sign bit is kept unchanged to determine the floating point data in the floating point internal format corresponding to the floating point data shown in table 10. The floating point data in the floating point internal format obtained after the first processing is performed on the denormal double-precision floating point data shown in table 10 may be as shown in table 11.
TABLE 11
Sign bit 1bit Code 12bits Mantissa 52bits
0 0011 1111 1101 0100 1100 0010 1111 0000 0100 0000 0000 0000 0000 0000 1010 0000
Referring to table 11, it can be seen that the floating point data in the floating point internal format obtained after the first processing is performed on the denormal double precision floating point data shown in table 10 has 12bits, 001111111101 as a new level, 0100110000101111000001000000000000000000000010100000 as a new mantissa, and 0 as a sign bit.
Exemplary floating point primitive formats for the maximum and minimum single and double precision denormal numbers are shown in table 6, respectively.
TABLE 12
Floating point primitive format Sign bit: 1bit order code single precision: 8bits double precision: 11bits mantissa single precision: 23bits double precision: 52bits
Minimum single precision denormal floating point Positive number 0 000 0000 0 000 0000 0000 0000 0000 0001
Maximum single precision denormal floating point Positive number 0 000 0000 0 111 1111 1111 1111 1111 1111
Minimum double precision denormal floating point Positive number 0 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
Maximum double precision denormal floating point Positive number 0 000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
The floating point internal format of the converted denormal positive numbers of single and double precision for the maximum and minimum after the first processing is performed is shown in table 13.
Watch 13
Floating point internal format Sign bit: 1bit order code single precision: 9bits double precision: 12bits mantissa single precision: 23bits double precision: 52bits
Minimum single precision denormal floating point Positive number 0 0011 0101 0 000 0000 0000 0000 0000 0001
Maximum single precision denormal floating point Positive number 0 0100 0000 0 111 1111 1111 1111 1111 1110
Minimum double precision denormal floating point Positive number 0 0011 0110 1001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001
Maximum double precision denormal floating point Positive number 0 0100 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110
For the example, for a floating point primitive format of single precision, double precision floating point data positive and negative zeros, the floating point data positive and negative zeros are shown in table 14.
TABLE 14
Floating point primitive format Sign bit 1bit Order code single precision: 8bits double precision: 11bits Mantissa single precision: 23bits double precision: 52bits
Single precision positive zero 0 000 0000 0 000 0000 0000 0000 0000 0000
Single precision negative zero 1 000 0000 0 000 0000 0000 0000 0000 0000
Double precision positive zero 0 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Double-precision negative zero 1 000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
As shown in table 14, the order and mantissa of positive and negative zeros are both 0, the sign bit of the positive zeros is 0, and the sign bit of the negative zeros is 1. The first processing performed on the positive and negative zero floating point data should be: the most significant bit of the code is increased by one bit, 0. The floating-point internal format single-precision and double-precision floating-point data positive and negative zeros obtained after the first processing is performed on the single-precision and double-precision floating-point data positive and negative zeros shown in table 14 may be shown in table 15.
Watch 15
Floating point internal format Sign bit 1bit Order code single precision: 9bits double precision: 12bits Mantissa single precision: 23bits double precision: 52bits
Single precision positive zero 0 0000 0000 0 000 0000 0000 0000 0000 0000
Single precision negative zero 1 0000 0000 0 000 0000 0000 0000 0000 0000
Double precision positive zero 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Double-precision negative zero 1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Referring to table 15, the stage code in the floating point internal format obtained after the first processing is performed on the positive and negative zero floating point data shown in table 14 is obtained by adding one bit, 0, to the most significant bit of the stage code of the floating point data in the floating point original format, and the sign bit and the mantissa are not changed.
For example, for a floating point primitive format of single precision, double precision floating point data plus or minus infinity, the floating point data plus or minus infinity is shown in table 16.
TABLE 16
Floating point primitive format Sign bit 1bit Order code single precision: 8bits double precision: 11bits Mantissa single precision: 23bits double precision: 52bits
Single precision positive infinity 0 111 1111 1 000 0000 0000 0000 0000 0000
Single precision negative infinity 1 111 1111 1 000 0000 0000 0000 0000 0000
Double-precision positive infinity 0 111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Double-precision negative infinity 1 111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
As shown in table 16, the positive and negative infinite order codes are all 1's and the mantissas are all 0's, the positive infinite sign bit is 0's, and the negative infinite sign bit is 1's. Then the first processing performed on the positive and negative infinity floating point data should be: the most significant bit of the code is increased by one bit 1. The floating-point internal format single-precision and double-precision floating-point data obtained after the first processing is executed to positive and negative infinity for the single-precision and double-precision floating-point data shown in table 16 may be shown as positive and negative infinity in table 17.
TABLE 17
Floating point internal format Sign bit 1bit Order code single precision: 9bits double precision: 12bits Mantissa single precision: 23bits double precision: 52bits
Single precision positive zero 0 1111 1111 1 000 0000 0000 0000 0000 0000
Single precision negative zero 1 1111 1111 1 000 0000 0000 0000 0000 0000
Double precision positive zero 0 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Double-precision negative zero 1 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Referring to table 17, the stage code in the floating point internal format obtained after the first processing is performed on the positive and negative infinite floating point data shown in table 16 is obtained by adding one bit 1 to the highest bit of the stage code of the floating point data in the floating point original format, and the sign bit and the mantissa are not changed.
For the example, for a floating point primitive format of a single precision, double precision floating point data not, the example floating point data not is shown in table 18.
Watch 18
Floating point primitive format Sign bit 1bit Order code single precision: 8bits double precision: 11bits Mantissa single precision: 23bits double precision: 52bits
Single precision nonnumeric 0 111 1111 1 001 0000 0000 0000 0000 0000
Double precision non-number 1 111 1111 1111 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000
As shown in table 18, the nonces have all 1's and all 0's. The first processing performed on non-floating point data should be: the most significant bit of the order code is incremented by one bit 1 and the two bits following the incremented most significant bit are set to 10. The single-precision and double-precision floating point nonnumbers in the floating point internal format obtained after the first processing is performed on the single-precision and double-precision floating point nonnumbers shown in table 18 may be as shown in table 19.
Watch 19
Floating point internal format Sign bit 1bit Order code single precision: 9bits double precision: 12bits Mantissa single precision: 23bits double precision: 52bits
Single precision nonnumeric 0 1101 1111 1 001 0000 0000 0000 0000 0000
Double precision non-number 1 1101 1111 1111 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 0000 0000 0000
Referring to table 19, the stage code in the floating point internal format obtained after the first processing is performed on the positive and negative infinite floating point data shown in table 18 is obtained by adding one bit 1 to the highest bit of the stage code of the floating point data in the floating point original format, setting the two bits following the added highest bit to 10, and keeping the sign bit and the mantissa unchanged.
It can be seen from the above that the floating point data in the floating point internal format described in the present embodiment is substantially increased by one bit from the level code of the floating point data in the floating point original format, and the sign bit and the mantissa bit are not changed. Table 20 is a bit width schematic table of floating-point internal format single-precision floating-point data and double-precision floating-point data in this embodiment.
Watch 20
Type (B) Sign bit width Bit width of code Mantissa bit width Total bit width Rank offset Bias
Single precision 1 9 23 33 255
Double precision 1 12 52 65 2047
Comparing table 1 and table 20, it can be seen that the opcode bit width for floating point data in the floating point internal format is increased by one bit from the opcode bit width for floating point data in the floating point native format.
As can be seen from the above, in the present application, the floating point data in the original floating point format is subjected to the first processing, so that the bit width of the stage code of the floating point data is increased by one bit, and thus the format of the floating point data is converted from the original floating point format to the floating point internal format. And, the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format. Meanwhile, for single-precision floating point data, the floating point data in the floating point internal format can indicate all numerical values of the single-precision floating point data in the 32-bit floating point original format; for the floating point data of the double-precision type, the floating point data in the floating point internal format can indicate all numerical values that the floating point data of the double-precision type in the 64-bit floating point original format can indicate, that is, the range of the numerical values that the floating point data in the floating point internal format can indicate is large. Therefore, the internal formats of the floating point data of the smaller numerical value can be successfully indicated, so that the phenomenon that the formats of the floating point data need to be switched to successfully indicate the floating point data with the smaller numerical value does not occur when the floating point operation unit performs the floating point operation on the floating point data in the floating point register file unit, and when the floating point operation unit performs the floating point operation on the floating point data, the format conversion step does not need to be executed, so that the efficiency of the floating point operation is improved.
And 300, performing floating-point operation on floating-point data with a format of a floating-point internal format in the floating-point register file unit by using the floating-point operation unit to obtain an operation result, wherein the format of the operation result is the format of the floating-point internal format.
In this embodiment, the floating point operation unit is connected to the floating point register file unit, and is configured to acquire floating point data in the floating point register file unit, perform operation to obtain a calculation result, and return the calculation result to the floating point register file unit for storage. In addition, in the present embodiment, when the floating point data in the floating point register file unit is input to the floating point arithmetic unit, the format of the floating point data is not converted, but the floating point data in the format of the floating point internal format is directly input from the floating point register file unit to the floating point arithmetic unit. And when the floating point operation unit operates the floating point data, the format of the floating point data is always in a floating point internal format.
And step 400, the floating-point operation unit transmits the operation result to the floating-point register file unit.
When the floating-point operation unit transmits the operation result to the floating-point register file unit, the format of the operation result is not converted, but the operation result with the format of the floating-point internal format is directly input to the floating-point register file unit from the floating-point operation unit.
And 500, outputting the operation result by a floating point register file unit, wherein when the operation result is output to a unit except the floating point operation unit and the floating point register file unit, the floating point register file unit performs second processing on the operation result in the floating point internal format to convert the format of the operation result into the floating point original format for subsequent processing.
Wherein the second processing may include: and removing one bit of the stage code of the floating point data in the floating point original format. And the numerical value indicated by the operation result in the floating-point internal format is equal to the numerical value indicated by the operation result in the floating-point original format.
Specifically, the method for converting the format of the operation result from the floating point internal format to the floating point original format mainly comprises the following steps:
judging whether the order of the operation result in the floating-point internal format is in the range corresponding to the order in the floating-point internal format converted from the floating-point normalized number, namely judging whether the order in the floating-point internal format is in the range from 010000010 (the floating-point internal format order corresponding to the minimum single-precision floating-point normalized positive number) to 101111111 (the floating-point internal format order corresponding to the maximum single-precision floating-point normalized positive number) by the operation result in the single-precision type, wherein the ranges comprise 010000010 and 101111111; the double precision type operation result determines whether the floating point internal format stage is in the range from 010000000010 (the floating point internal format stage corresponding to the minimum double precision floating point normalization positive number) to 101111111111 (the floating point internal format stage corresponding to the maximum double precision floating point normalization positive number), including 010000000010 and 101111111111; when the stage of the operation result in the floating-point internal format is within a range of stages in a floating-point internal format converted from a floating-point normalized number, determining that the floating-point primitive format corresponding to the operation result is a floating-point normalized number, and the second processing includes: and removing the highest bit from the difference between the binary number corresponding to the level code of the operation result in the floating point internal format and the binary number corresponding to the set value to obtain the converted level code in the floating point original format.
Judging whether the order of the operation result in the floating-point internal format is in the range corresponding to the order converted from the floating-point denormal number and after the floating-point internal format, namely judging whether the order in the floating-point internal format is in the range from 001101010 (the floating-point internal format order corresponding to the minimum single-precision floating-point denormal positive number) to 010000000 (the floating-point internal format order corresponding to the maximum single-precision floating-point denormal positive number) by the operation result in the single-precision type, wherein the order comprises 001101010 and 010000000; the double precision type operation result determines whether the order of the floating point internal format is in the range from 001101101001 (the floating point internal format order corresponding to the minimum double precision floating point denormal positive) to 010000000000 (the floating point internal format order corresponding to the maximum double precision floating point denormal positive), including 001101101001 and 010000000000; then, it is determined that the floating point primitive format corresponding to the operation result is an denormal number, the second processing may include: changing the order codes of the operation results in the floating point internal format into all 0 and removing one bit, and performing right shift on mantissas of the operation results in the floating point internal format by using a second preset digit, wherein when performing the right shift, one bit of 1 is firstly used for performing the right shift, then all 0 are used for performing the right shift, and the second preset digit = a set value-the decimal value corresponding to the order codes of the operation results in the floating point internal format before performing the second processing.
Determining whether the level code of the operation result in the floating point internal format is within a level code range of the floating point internal format converted from the floating point special number floating point original format, that is, whether the highest three bits of the floating point internal format are 000, 111, or 110, and when the highest three bits of the level code of the operation result in the floating point internal format are 000, determining that the floating point original format corresponding to the operation result is positive or negative zero, wherein the second processing includes: removing the highest order of the order code of the operation result in the floating point internal format to be used as the converted order code in the original floating point format; when the highest three bits of the order code of the operation result in the floating-point internal format are 111, determining that the floating-point original format corresponding to the operation result is positive, negative and infinite, and the second processing includes: and removing the highest order of the order code of the operation result in the floating point internal format to be used as the converted order code in the original floating point format. When the highest three bits of the order code of the operation result in the floating-point internal format are 110, determining that the floating-point original format corresponding to the operation result is a non-number, wherein the second processing includes: and removing the highest bit of the order code of the operation result in the floating point internal format, and setting the first two bits of the number after the removed highest bit as 11 to be used as the order code in the converted floating point original format.
For example, in combination with the above, it is assumed that the operation result is floating point data shown in table 3. Referring to Table 3, with the stage 100000011, it can be determined that the stage 100000011 of the operation result is in the range of 010000010 to 101111111, i.e., the floating point primitive format corresponding to the operation result is a normalized number. Thus, the second process may be: the binary number 010000001 corresponding to 129 is subtracted from the floating point internal format level 100000011 and is equal to 010000010, the level is 10000010 after the highest bit is removed, and the sign bit and the mantissa are unchanged. The floating-point primitive format of the floating-point data shown in table 3 can be as shown in table 2.
Alternatively, the operation result is assumed to be the floating point data shown in table 5. Referring to Table 5, with the stage 100000010001, it can be determined that the stage 100000010001 of the operation result is in the range of 010000000010 to 101111111111, i.e., the floating point primitive format corresponding to the operation result is a normalized number. The second process may thus be: the corresponding binary number 010000000001 is subtracted 1025 from the floating point internal format level 100000010001 to equal 010000010000, the level is 10000010000 after removing the most significant bit, and the sign bit and mantissa are unchanged. The floating point primitive format of the floating point data shown in table 5 can be as shown in table 4.
Alternatively, if the operation result is the floating point data shown in table 9, and it can be known from table 9 that the stage code is 010000000, it can be determined that the stage code 010000000 of the operation result is in the range of 001101010 and 010000000, that is, the floating point primitive format corresponding to the operation result is an denormal number. The second process may thus be: changing the gradation 010000000 in table 9 to all 0 s and removing one bit results in a new gradation 00000000, and right-shifting the mantissa in table 9 by a second predetermined number of bits, wherein right-shifting by one bit 1 is performed first and then all right-shifting by 0 s is performed when right-shifting is performed, and, considering that the floating point data shown in table 9 is of a single precision type, the second predetermined number of bits = set value 129 — decimal value 128=1 corresponding to the gradation 010000000 of the operation result in the floating point internal format before the second processing is performed. Therefore, when the mantissa 00000000001000000000000 in table 9 is shifted right by 1bit by the right shift method described above to obtain a new mantissa 10000000000100000000000, the format of the floating point data in table 9 can be converted from the floating point internal format to the floating point original format based on the new stage and the new mantissa. The floating point primitive format of the floating point data shown in table 9 may be as shown in table 8.
Further alternatively, assuming that the operation result is the floating point data shown in table 11, referring to table 11, it can be known that the level code is 001111111101, and it can be determined that the level code 001111111101 of the operation result is in the range of 001101101001 to 010000000000, that is, the floating point primitive format corresponding to the operation result is an unnormal number. The second process may thus be: changing the gradation 001111111101 in the table 11 to all 0 and removing one bit results in a new gradation 0000000, and right-shifting the mantissa in the table 11 by a second predetermined number of bits, wherein the right-shifting is performed by one bit 1 first and then all 0's, and, considering that the floating point data shown in the table 11 is of double precision type, the second predetermined number of bits = the set value 1025-the decimal value 1021=4 corresponding to the gradation 001111111101 of the operation result in the floating point internal format before the second processing is performed. Therefore, when the mantissa 0100110000101111000001000000000000000000000010100000 in table 11 is right-shifted by 4 bits by the above-mentioned right shift method to obtain a new mantissa 0001010011000010111100000100000000000000000000001010, the format of the floating point data in table 11 can be converted from the floating point internal format to the floating point original format based on the new stage and the new mantissa. The floating point primitive format of the floating point data shown in table 11 can be as shown in table 10.
Alternatively, the operation result is assumed to be the floating point data shown in table 15. Referring to table 15, the highest three bits of the level code are 000, that is, the floating point primitive format corresponding to the operation result is positive or negative zero. The second process may thus be: the order code removes the most significant bit, and the sign bit and the mantissa are unchanged. The floating point primitive format of the floating point data shown in table 15 may be as shown in table 14.
Alternatively, the operation result is assumed to be the floating point data shown in table 17. Referring to table 17, the highest three bits of the level code are 111, that is, the floating point primitive format corresponding to the operation result is plus or minus infinity. The second process may thus be: the order code removes the most significant bit, and the sign bit and the mantissa are unchanged. The floating point primitive format of the floating point data shown in table 17 may be as shown in table 16.
Alternatively, the operation result is assumed to be the floating point data shown in table 19. Referring to table 19, the highest three bits of the level code are 110, i.e., the floating point primitive format corresponding to the operation result is not. The second process may thus be: the gradation code removes the most significant bit and sets the first two bits of the number from which the most significant bit is removed to 11. The floating point primitive format of the floating point data shown in table 19 may be as shown in table 18.
In summary, in the floating point data processing method provided by the present application, before the floating point data is input to the floating point register file unit from the units other than the floating point arithmetic unit and the floating point register file unit, one bit is added to the stage code of the floating point data to convert the floating point native format into the floating point internal format, and when the floating point data in the floating point register file unit is output to the units other than the floating point arithmetic unit and the floating point register file unit, one bit is removed from the stage code of the floating point data to convert the floating point internal format into the floating point native format. Therefore, the formats of the floating point data in the floating point register file unit and the floating point data in the floating point operation unit are always in a floating point internal format. And because the order code of the floating point data under the floating point internal format is increased by one bit, the range of the value which can be indicated by the order code is larger, even if the operation result obtained by the floating point operation unit based on the floating point data in the floating point register file unit is smaller, the operation result can be represented by the floating point internal format, and the format of the operation result does not need to be converted, so that the efficiency of the floating point operation can be improved.
In the method, when the format of the floating point data is converted from the original floating point format into the internal floating point format and the format of the operation result is converted from the internal floating point format into the original floating point format, the pipeline does not need to be blocked, so that the execution time can be reduced, the full-flow processing can be realized, the control complexity is reduced, and the efficiency of floating point operation is improved.
Meanwhile, format conversion is only needed to be carried out when the floating-point register file unit enters and exits, and because the formats of the floating-point data inside the floating-point register file unit and the floating-point data inside the floating-point operation unit are always in the floating-point internal format, format conversion is not needed, so that a format conversion module does not need to be arranged at the entrance and exit end of each floating-point operation unit, and a format conversion module only needs to be arranged at the entrance and exit end of the floating-point register file unit, so that the performance is improved, the power consumption and the hardware area are reduced, and the cost is reduced.
Example two
Further, based on the floating point data processing method provided in the foregoing embodiment, an embodiment of the present application further provides a floating point data processing apparatus, and fig. 2 is a schematic structural diagram of the floating point data processing apparatus provided in an embodiment of the present application, and as shown in fig. 2, the apparatus may include:
a first conversion module, configured to, when floating-point data is input to the floating-point register file unit by a unit other than the floating-point arithmetic unit and the floating-point register file unit, perform first processing on the floating-point data to convert a format of the floating-point data from a floating-point native format to a floating-point internal format; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format;
the floating-point register file unit is connected with the first conversion module and used for storing floating-point data in a floating-point internal format;
the floating-point operation unit is connected with the floating-point register file unit and is used for performing floating-point operation on floating-point data stored in the floating-point register file unit to obtain an operation result and inputting the operation result into the floating-point register file unit for storage, wherein the operation result is in a floating-point internal format, and when the floating-point operation unit operates on the floating-point data, the floating-point data is in the floating-point internal format; and when the operation result is transmitted to the floating-point register file unit for storage by the floating-point operation unit, the format of the operation result is not converted.
Optionally, the floating-point primitive format meets IEEE754 standards;
the first conversion module is configured to: and increasing the order code of the floating point original format by one bit.
Optionally, the first conversion module is further configured to: when the floating point original format is a normalized number, adding one bit of 0 to the highest bit of the level code of the floating point data in the floating point original format, and taking the binary number obtained by adding one bit of 0 to the highest bit of the level code and the binary number corresponding to the set value as the level code of the floating point data in the floating point internal format;
the value rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025 and is a decimal number.
Optionally, the first conversion module is further configured to: when the floating point original format is an unnormalized number, performing left shift on the mantissa in the floating point original format by using 0 for a first preset digit, and using a binary number corresponding to the difference value as a step code of the floating point data in the floating point internal format, wherein the bit width of the step code of the floating point data in the floating point internal format is the step code bit width of the floating point data in the floating point original format plus one; wherein, the difference value is obtained by subtracting a first preset digit from a set value; the set value and the first preset digit are both decimal numbers, and the value-taking rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025; the first preset digit is the number of zeros of the mantissa in the floating-point original format before the first 1 of the first digit plus one.
Optionally, the floating-point primitive format further includes a special number, where the special number includes a non-number, positive and negative zeros, and positive and negative infinity;
when the floating-point primitive format is a non-number, the first conversion module is further configured to: adding 1bit to the highest bit of the level code in the floating point original format;
when the floating point primitive format is positive or negative zero, the first conversion module is further configured to: adding a bit of 0 to the highest bit of the order code of the floating point data in the original format;
when the floating-point primitive format is positive or negative infinity, the first conversion module is further configured to: adding 1bit to the highest bit of the order code of the floating point data in the original format, and setting two bits after the highest bit as 10.
Optionally, the apparatus further comprises:
and the second conversion module is connected with the floating-point register file unit and is used for performing second processing on the operation result to convert the internal format of the floating point into the original format of the floating point when the floating-point register file unit outputs the operation result to a unit except the floating-point operation unit and the floating-point register file unit.
Optionally, the floating-point primitive format meets IEEE754 standards;
the second conversion module is configured to: removing one bit of the level code of the floating point internal format.
Optionally, the second conversion module is further configured to:
judging whether the order code of the operation result in the floating point internal format is in a range corresponding to the order code converted from the normalized number in the original floating point format into the floating point internal format;
when the level code of the operation result is in the range corresponding to the level code after the normalized number in the floating point original format is converted into the floating point internal format, taking the number obtained by removing the highest bit from the difference between the binary number corresponding to the level code of the operation result and the binary number corresponding to the set value as the level code in the floating point original format after conversion;
the value rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025 and is a decimal number.
Optionally, the second conversion module is further configured to:
judging whether the order code of the operation result in the floating point internal format is in a range corresponding to the order code converted from the denormal number in the floating point original format into the floating point internal format;
and when the order of the operation result is in the range corresponding to the order of the floating point internal format converted from the denormal number of the floating point original format, changing the order of the operation result into all 0 and removing one bit, and performing right shift conversion on the mantissa of the operation result of the floating point internal format to be used as the converted mantissa of the floating point original format.
Optionally, the right shift conversion is to perform right shift of a second preset number of digits on the mantissa, where, when performing the right shift, one digit 1 is used for right shift first, and then all 0's are used for right shift, and the second preset number of digits = a set value — a decimal value corresponding to an order code of an operation result in the floating point internal format before performing the second processing;
wherein, the value rule of the set value comprises: when the floating point data is single precision, the set value is equal to 129; and when the floating point data is of double precision, the set value is 1025, and the second preset digit and the set value are decimal numbers.
Optionally, the second processing module is further configured to:
judging whether the highest three bits of the order code of the operation result in the floating-point internal format are 000, 111 or 110;
when the highest three bits of the order code of the operation result are 000 or 111, removing the highest bits of the order code of the operation result to be used as the order code of the floating point original format corresponding to the operation result;
and when the highest three bits of the order code of the operation result are 110, removing the highest bit of the order code of the operation result, and setting the first two bits of the number obtained after the highest bit is removed as 11 to be used as the order code of the floating point original format corresponding to the operation result.
In summary, in the floating point data processing method and apparatus provided by the present application, before the floating point data is input to the floating point register file unit from the units other than the floating point arithmetic unit and the floating point register file unit, the stage code of the floating point data is increased by one bit to convert the floating point native format into the floating point internal format, and when the floating point data in the floating point register file unit is output to the units other than the floating point arithmetic unit and the floating point register file unit, the stage code of the floating point data is removed by one bit to convert the floating point internal format into the floating point native format. Therefore, the formats of the floating point data in the floating point register file unit and the floating point data in the floating point operation unit are always in a floating point internal format. And because the order code of the floating point data under the floating point internal format is increased by one bit, the range of the value which can be indicated by the order code is larger, even if the operation result obtained by the floating point operation unit based on the floating point data in the floating point register file unit is smaller, the operation result can be represented by the floating point internal format, and the format of the operation result does not need to be converted, so that the efficiency of the floating point operation can be improved.
In the method, when the format of the floating point data is converted from the original floating point format into the internal floating point format and the format of the operation result is converted from the internal floating point format into the original floating point format, the pipeline does not need to be blocked, so that the execution time can be reduced, the full-flow processing can be realized, the control complexity is reduced, and the efficiency of floating point operation is improved.
Meanwhile, format conversion is only needed to be carried out when the floating-point register file unit enters and exits, and because the formats of the floating-point data inside the floating-point register file unit and the floating-point data inside the floating-point operation unit are always in the floating-point internal format, format conversion is not needed, so that a format conversion module does not need to be arranged at the entrance and exit end of each floating-point operation unit, and a format conversion module only needs to be arranged at the entrance and exit end of the floating-point register file unit, so that the performance is improved, the power consumption and the hardware area are reduced, and the cost is reduced.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (22)

1. A floating point data processing method, comprising:
when floating point data are input to a floating point register file unit by a unit except a floating point arithmetic unit and a floating point register file unit, performing first processing on the floating point data to convert the format of the floating point data from a floating point original format to a floating point internal format; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format;
and performing floating-point operation on floating-point data with a format of a floating-point internal format in the floating-point register file unit by using the floating-point operation unit to obtain an operation result, wherein the format of the operation result is the floating-point internal format, and the formats of the floating-point data are all the floating-point internal formats when the floating-point operation unit operates the floating-point data.
2. A floating point data processing method as claimed in claim 1, wherein said floating point primitive format meets the IEEE754 standard, and said first processing comprises: and increasing the order code of the floating point original format by one bit.
3. A floating point data processing method as claimed in claim 2, wherein when the floating point native format is a normalized number, the first processing comprises: adding a bit of 0 to the highest bit of the floating point data in the original floating point format, and taking the binary number corresponding to the sum of the binary number obtained after the highest bit of the floating point data in the original floating point format is added with the binary number corresponding to the set value as the level of the floating point data in the internal floating point format;
the value rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025 and is a decimal number.
4. A floating point data processing method as claimed in claim 2, wherein when the floating point primitive format is an denormal number, the first processing comprises: performing left shift of a first preset digit on the mantissa in the floating point original format by using 0, and taking a binary number corresponding to the difference value as a level code of the floating point data in the floating point internal format, wherein the bit width of the level code of the floating point data in the floating point internal format is the bit width of the level code of the floating point data in the floating point original format plus one; wherein, the difference value is obtained by subtracting a first preset digit from a set value; the first preset digit is the number of zero before the first 1 of the mantissa of the floating point original format plus one; the set value and the first preset digit are decimal numbers, and the value-taking rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025.
5. Floating point data processing method according to claim 2,
the floating-point original format also comprises special numbers, wherein the special numbers comprise nonnumbers, positive and negative zeros and infinite positive and negative numbers;
when the floating-point primitive format is a non-number, the first processing includes: adding 1bit to the highest bit of the level code in the floating point original format;
when the floating point primitive format is positive or negative zero, the first processing includes: adding a bit of 0 to the highest bit of the level code in the floating point original format;
when the floating point primitive format is positive or negative infinity, the first processing includes: and adding 1bit to the highest bit of the order code of the floating point original format, and setting the two bits after the highest bit as 10.
6. A floating point data processing method according to claim 1, characterized in that the method further comprises:
the floating-point operation unit transmits an operation result to the floating-point register file unit for storage, and the format of the operation result is not converted;
when the floating-point register file unit outputs the operation result to a unit except the floating-point operation unit and the floating-point register file unit, performing second processing on the operation result to convert the internal format of the floating point into the original format of the floating point; the numerical value indicated by the operation result in the floating-point original format is equal to the numerical value indicated by the operation result in the floating-point internal format.
7. The floating point data processing method of claim 6, wherein the floating point primitive format meets the IEEE754 standard; the second processing includes: removing one bit of the level code of the floating point internal format.
8. A floating point data processing method according to claim 7, characterized in that the second processing comprises:
judging whether the order code of the operation result in the floating point internal format is in a range corresponding to the order code converted from the normalized number in the original floating point format into the floating point internal format;
when the order of the operation result is in the range corresponding to the order converted from the normalized number in the original floating point format to the order in the internal floating point format, taking the number obtained by removing the highest bit from the difference between the binary number corresponding to the order of the operation result in the internal floating point format and the binary number corresponding to the set value as the converted order in the original floating point format;
and the value-taking rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025 and is a decimal number.
9. A floating point data processing method as claimed in claim 7, wherein said second processing further comprises:
judging whether the order code of the operation result in the floating point internal format is in a range corresponding to the order code converted from the denormal number in the floating point original format into the floating point internal format;
and when the order of the operation result is in the range corresponding to the order converted from the denormal number in the floating-point original format into the order in the floating-point internal format, changing the order of the operation result into all 0 s and removing one bit, and performing right shift conversion on the mantissa of the operation result in the floating-point internal format to be used as the mantissa in the converted floating-point original format.
10. A floating point data processing method as claimed in claim 9, wherein the right shift conversion is a right shift of the mantissa by a second predetermined number of bits, wherein the right shift is performed by first performing the right shift by one bit of 1 and then all by 0;
the second preset digit = set value-decimal value corresponding to the order code of the operation result in the floating point internal format before the second processing is executed;
the value rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; and when the floating point data is of double precision, the set value is 1025, and the second preset digit and the set value are decimal numbers.
11. A floating point data processing method according to claim 7, characterized in that the second processing comprises:
judging whether the highest three bits of the order code of the operation result in the floating-point internal format are 000, 111 or 110;
when the highest three bits of the order code of the operation result are 000 or 111, removing the highest bits of the order code of the operation result to be used as the order code of the floating point original format corresponding to the operation result;
and when the highest three bits of the order code of the operation result are 110, removing the highest bit of the order code of the operation result, and setting the first two bits of the number obtained after the highest bit is removed as 11 to be used as the order code of the floating point original format corresponding to the operation result.
12. A floating point data processing apparatus, comprising:
a first conversion module, configured to, when floating-point data is input to the floating-point register file unit by a unit other than the floating-point arithmetic unit and the floating-point register file unit, perform first processing on the floating-point data to convert a format of the floating-point data from a floating-point native format to a floating-point internal format; the numerical value indicated by the floating point data in the floating point internal format is equal to the numerical value indicated by the floating point data in the floating point original format;
the floating-point register file unit is connected with the first conversion module and used for storing floating-point data in a floating-point internal format;
the floating-point operation unit is connected with the floating-point register file unit and is used for performing floating-point operation on floating-point data stored in the floating-point register file unit to obtain an operation result and inputting the operation result into the floating-point register file unit for storage, wherein the operation result is in a floating-point internal format, and when the floating-point operation unit operates on the floating-point data, the floating-point data is in the floating-point internal format; and when the operation result is transmitted to the floating-point register file unit for storage by the floating-point operation unit, the format of the operation result is not converted.
13. The floating point data processing device of claim 12, wherein the floating point native format satisfies IEEE754 standards;
the first conversion module is configured to: and increasing the order code of the floating point original format by one bit.
14. The floating point data processing apparatus of claim 13, wherein the first conversion module is further configured to: when the floating point original format is a normalized number, adding one bit of 0 to the highest bit of the level code of the floating point data in the floating point original format, and taking the binary number obtained by adding one bit of 0 to the highest bit of the level code and the binary number corresponding to the set value as the level code of the floating point data in the floating point internal format;
the value rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025 and is a decimal number.
15. The floating point data processing apparatus of claim 13, wherein the first conversion module is further configured to: when the floating point original format is an unnormalized number, performing left shift on the mantissa in the floating point original format by using 0 for a first preset digit, and using a binary number corresponding to the difference value as a step code of the floating point data in the floating point internal format, wherein the bit width of the step code of the floating point data in the floating point internal format is the step code bit width of the floating point data in the floating point original format plus one; wherein the first preset digit is the number of zeros of the mantissa in the floating point original format before the first 1 of the first digit plus one; the difference value is obtained by subtracting a set value from a first preset digit; the set value and the first preset digit are both decimal numbers, and the value-taking rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025.
16. Floating point data processing apparatus according to claim 13,
the floating-point original format also comprises special numbers, wherein the special numbers comprise nonnumbers, positive and negative zeros and infinite positive and negative numbers;
when the floating-point primitive format is a non-number, the first conversion module is further configured to: adding 1bit to the highest bit of the level code in the floating point original format;
when the floating point primitive format is positive or negative zero, the first conversion module is further configured to: adding a bit of 0 to the highest bit of the order code of the floating point data in the original format;
when the floating-point primitive format is positive or negative infinity, the first conversion module is further configured to: adding 1bit to the highest bit of the order code of the floating point data in the original format, and setting two bits after the highest bit as 10.
17. The floating point data processing apparatus of claim 12, further comprising:
and the second conversion module is connected with the floating-point register file unit and is used for performing second processing on the operation result to convert the internal format of the floating point into the original format of the floating point when the floating-point register file unit outputs the operation result to a unit except the floating-point operation unit and the floating-point register file unit.
18. The floating point data processing device of claim 17, wherein the floating point native format satisfies IEEE754 standards;
the second conversion module is configured to: removing one bit of the level code of the floating point internal format.
19. The floating point data processing apparatus of claim 18, wherein the second conversion module is further configured to:
judging whether the order code of the operation result in the floating point internal format is in a range corresponding to the order code converted from the normalized number in the original floating point format into the floating point internal format;
when the level code of the operation result is in the range corresponding to the level code after the normalized number in the floating point original format is converted into the floating point internal format, taking the number obtained by removing the highest bit from the difference between the binary number corresponding to the level code of the operation result and the binary number corresponding to the set value as the level code in the floating point original format after conversion;
the value rule of the set value comprises the following steps: when the floating point data is single precision, the set value is equal to 129; when the floating point data is double precision, the set value is 1025 and is a decimal number.
20. The floating point data processing apparatus of claim 18, wherein the second conversion module is further configured to:
judging whether the order code of the operation result in the floating point internal format is in a range corresponding to the order code converted from the denormal number in the floating point original format into the floating point internal format;
and when the order of the operation result is in the range corresponding to the order of the floating point internal format converted from the denormal number of the floating point original format, changing the order of the operation result into all 0 and removing one bit, and performing right shift conversion on the mantissa of the operation result of the floating point internal format to be used as the converted mantissa of the floating point original format.
21. A floating point data processing device as claimed in claim 20, wherein the right shift conversion is a right shift of the mantissa by a second predetermined number of bits, wherein the right shift is performed by first performing the right shift by one bit 1 and then performing the right shift by all 0 s, and wherein the second predetermined number of bits = set-value-decimal value corresponding to the order code of the operation result in floating point internal format before performing the second processing;
wherein, the value rule of the set value comprises: when the floating point data is single precision, the set value is equal to 129; and when the floating point data is of double precision, the set value is 1025, and the second preset digit and the set value are decimal numbers.
22. The floating point data processing apparatus of claim 18, wherein the second processing module is further configured to:
judging whether the highest three bits of the order code of the operation result in the floating-point internal format are 000, 111 or 110;
when the highest three bits of the order code of the operation result are 000 or 111, removing the highest bits of the order code of the operation result to be used as the order code of the floating point original format corresponding to the operation result;
and when the highest three bits of the order code of the operation result are 110, removing the highest bit of the order code of the operation result, and setting the first two bits of the number obtained after the highest bit is removed as 11 to be used as the order code of the floating point original format corresponding to the operation result.
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