CN112510033A - Silicon controlled rectifier and manufacturing method thereof - Google Patents
Silicon controlled rectifier and manufacturing method thereof Download PDFInfo
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- CN112510033A CN112510033A CN202011094759.2A CN202011094759A CN112510033A CN 112510033 A CN112510033 A CN 112510033A CN 202011094759 A CN202011094759 A CN 202011094759A CN 112510033 A CN112510033 A CN 112510033A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 32
- 239000010703 silicon Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 230000000694 effects Effects 0.000 claims abstract description 44
- 230000003071 parasitic effect Effects 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 229910052755 nonmetal Inorganic materials 0.000 claims abstract description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
Abstract
The invention discloses a silicon controlled rectifier, which comprises: the N well and the P well are formed on the P-type semiconductor substrate; the first high-concentration P-type doped region and the first high-concentration N-type doped region are formed on the N well; the second high-concentration N-type doped region and the second high-concentration P-type doped region are formed on the P well; the third high-concentration P-type doped region is formed above the boundary of the N well and the P well and is adjacent to the second high-concentration N-type doped region, and a non-metal silicide layer is formed on the upper surface of the third high-concentration P-type doped region; an N well with a first width is formed between the first high-concentration P-type doped region and the first high-concentration N-type doped region, an N well with a second width is formed between the first high-concentration N-type doped region and the third high-concentration P-type doped region, the width of the first high-concentration N-type doped region is a third width, and the width of the third high-concentration P-type doped region is a fourth width. The invention also discloses a manufacturing method of the silicon controlled rectifier. The invention reduces the current gain of the parasitic NPN triode, and further can reduce the width of a protection ring required by realizing the hysteresis-free effect, thereby saving the layout area.
Description
Technical Field
The invention relates to the field of integrated circuit production and manufacturing, in particular to a silicon controlled rectifier without hysteresis effect. The invention also relates to a manufacturing method of the silicon controlled rectifier without hysteresis effect.
Background
The design of the anti-static protection of the high-voltage circuit has been a technical problem because the core of the high-voltage circuit is formed: the high voltage device (such as LDMOS) is not suitable for esd protection design as the conventional low voltage device itself, because the hysteresis response curve of the high voltage device shows poor characteristics. As shown in fig. 1, the following drawbacks can be derived from the hysteresis effect curve of the conventional high-voltage device:
1) the holding voltage (Vh) is too low and is often greatly lower than the working voltage of the high-voltage circuit, and the latch-up effect is easily caused when the high-voltage circuit works normally;
2) the second breakdown Current (It2) is too low because the LDMOS discharges ESD Current due to local Current Crowding (Localized Current Crowding) due to the device structure characteristics.
Therefore, when the anti-static protection design of the high-voltage circuit is solved, two ideas are usually adopted to realize the following steps:
1) the structure of a high-voltage device used for the anti-static protection module is adjusted, and the hysteresis effect curve of the high-voltage device is optimized, so that the high-voltage device is suitable for anti-static protection design, but the high-voltage device is difficult to practice due to the structural characteristics of the high-voltage device;
2) a certain number of low-voltage anti-static protection devices are connected in series to form an anti-static protection circuit capable of bearing high voltage. Because the characteristics of the low voltage esd protection devices are relatively easy to adjust and control, the industry, especially integrated circuit design companies, often prefer to connect a certain number of low voltage esd protection devices in series.
Because of the requirement of the anti-static protection design window of the high-voltage circuit, there is a certain requirement on the hysteresis effect characteristic of the low-voltage anti-static protection device, and it is often required that the smaller the hysteresis effect window is, the better the hysteresis effect is, and preferably no hysteresis effect is, that is, the holding voltage and the trigger voltage of the hysteresis effect are basically kept consistent. The low-voltage PMOS device is a common electrostatic protection device without hysteresis effect, because the parasitic PNP triode has smaller current gain when hysteresis effect occurs, but the low-voltage PMOS device has the defect that the secondary breakdown current (It2) of the hysteresis effect is smaller, and therefore, the anti-electrostatic protection device without hysteresis effect and with higher secondary breakdown current is researched and developed in the industry.
The industry has proposed a new type of SCR without hysteresis effect (No-Snapback SCR) in 2015, and as shown in fig. 2, experimental data of the new type SCR without hysteresis effect shows that when the size (D2) of N + (28) and P + (22) reaches a certain degree (4um), the new type SCR exhibits the characteristic of No hysteresis effect, as shown in fig. 3, it is very suitable for the requirement of multistage series connection of low-voltage devices for the anti-static protection design of high-voltage circuit. However, the novel silicon controlled rectifier without hysteresis effect has the disadvantage that the size of the device is large, and particularly when multistage series connection is needed, the layout area is large.
Chinese patent No.: CN108183101B discloses a new scr, as shown in fig. 4, it directly connects the originally floating N +28 with the anode, which makes the N +28 reduce the probability that the hole is injected into the N Well (N _ Well60) from P +20 and reaches the N Well/P Well interface, and further reduces, that is, the efficiency of N +28 as the guard ring is further improved, so the width of N +28 can be designed smaller, and the layout area is saved; in addition, the N +28 also has the function of an N-Well (N _ Well60) connection and disconnection point (Pickup), so that the N-Well connection and disconnection point (N +30) in the existing silicon controlled rectifier without hysteresis effect in the figure 2 can be further removed, and the layout area is further saved. Although the scheme further saves the layout area, along with the trend of miniaturization of devices, the technical requirement that the layout area of the silicon controlled rectifier is further reduced due to the requirement of higher layout area is provided.
Disclosure of Invention
In this summary, a series of simplified form concepts are introduced that are simplifications of the prior art in this field, which will be described in further detail in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The technical problem to be solved by the invention is to provide a silicon controlled rectifier which can reduce the size of the whole device, reduce the layout area and has no hysteresis effect compared with the prior art.
The invention aims to solve another technical problem of providing a silicon controlled rectifier manufacturing method which can reduce the size of the whole device and reduce the layout area without hysteresis effect compared with the prior art.
In order to solve the above technical problem, the present invention provides a silicon controlled rectifier, including:
a P-type semiconductor substrate 80;
an N well60 and a P well 70 formed on the upper portion of the P-type semiconductor substrate 80;
a first high concentration P-type doped region 20 and a first high concentration N-type doped region 28 formed at the upper portion of the N-well 60;
a second high concentration N-type doped region 24 and a second high concentration P-type doped region 26 formed on the upper portion of the P well 70;
a third high concentration P-type doped region 22 formed above the boundary between the N-well 60 and the P-well 70 and adjacent to the second high concentration N-type doped region 24; a non-metal silicide layer is formed on the upper surface of the third high-concentration P-type doped region 22;
the first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-type semiconductor substrate 80 or the P-well 70 and the second high-concentration N-type doped region 24 form a parasitic NPN triode structure;
an N-well 60 with a first width S is formed between the first high concentration P-type doped region 20 and the first high concentration N-type doped region 28, an N-well 60 with a second width D1 is formed between the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22, the first high concentration N-type doped region 28 has a third width D2, and the third high concentration P-type doped region 22 has a fourth width D3.
Optionally, the first shallow trench isolation 10 is formed in the N well60 on the left side of the first high concentration P-type doped region 20, adjacent to the first high concentration P-type doped region 20;
a second shallow trench isolation 14 adjacent to the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26 and formed in the P-well 70 between the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26;
the third shallow trench isolation 16, which is adjacent to the second high concentration P-type doped region 26, is formed in the P-well 70 on the right side of the second high concentration P-type doped region 26.
Optionally, the silicon controlled rectifier is further improved, wherein the range of the first width S is 0.2um to 10um, the range of the second width D1 is 0.2um to 2um, the range of the third width D2 is 0.2um to 5um, and the range of the fourth width D3 is 0.2um to 10 um.
Optionally, the scr is further modified to adjust the sustain voltage to achieve the hysteretic-free characteristic by adjusting the first width S, the third width D2 and the fourth width D3.
Optionally, the scr is further modified to reduce the current gain of the parasitic NPN transistor by adjusting the fourth width D3.
Optionally, the silicon controlled rectifier is further improved, and the trigger voltage of the silicon controlled rectifier in the hysteresis effect can be adjusted by adjusting the second width D1.
Optionally, the scr is further modified to connect the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 to serve as an anode of the ESD protection structure through metal, and connect the second high-concentration N-type doped region 24 and the second high-concentration P-type doped region 26 to serve as a cathode of the ESD protection structure through metal when used for ESD protection.
In order to solve the above technical problem, the present invention provides a method for manufacturing a silicon controlled rectifier, comprising the following steps:
s1, forming N well60 and P well 70 in P-type semiconductor substrate 80;
s2, forming a first high-concentration P-type doped region 20 and a first high-concentration N-type doped region 28 in the N well60, forming a second high-concentration N-type doped region 24 and a second high-concentration P-type doped region 26 in the P well60, and forming a third high-concentration P-type doped region 22 at the boundary of the N well60 and the P well 70, wherein the third high-concentration P-type doped region 22 is adjacent to the second high-concentration N-type doped region 24; a non-metal silicide layer is formed on the upper surface of the third high-concentration P-type doped region 22;
the first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-type semiconductor substrate 80 or the P-well 70 and the second high-concentration N-type doped region 24 form a parasitic NPN triode structure;
an N-well 60 with a first width S is formed between the first high concentration P-type doped region 20 and the first high concentration N-type doped region 28, an N-well 60 with a second width D1 is formed between the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22, the first high concentration N-type doped region 28 has a third width D2, and the third high concentration P-type doped region 22 has a fourth width D3.
Optionally, the method for manufacturing the silicon controlled rectifier is further improved, and a step of manufacturing shallow trench isolation is added between the steps S1 and S2;
the first shallow trench isolation 10 is formed in the N-well 60 at the left side of the first high concentration P-type doped region 20 and is adjacent to the first high concentration P-type doped region 20;
the second shallow trench isolation 14 is formed in the P-well 70 between the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26 and is adjacent to the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26;
the third shallow trench isolation 16 is formed in the P-well 70 on the right side of the second high concentration P-type doped region 26 and is adjacent to the second high concentration P-type doped region 26.
Optionally, the method for manufacturing the silicon controlled rectifier is further improved, wherein the first width S ranges from 0.2um to 10um, the second width D1 ranges from 0.2um to 2um, the third width D2 ranges from 0.2um to 5u m, and the fourth width D3 ranges from 0.2um to 10 um.
Optionally, the method for manufacturing the scr is further modified, and in step S2, the sustain voltage is adjusted by adjusting the first width S, the third width D2 and the fourth width D3 to achieve the characteristic of no hysteresis effect.
Optionally, in step S2, the method for manufacturing the scr further improves, and the current gain of the parasitic NPN transistor is reduced by adjusting the fourth width D3.
Optionally, the method for manufacturing the scr is further modified, and in step S2, the trigger voltage of the hysteretic effect is adjusted by adjusting the second width D1.
Optionally, the method for manufacturing the scr is further improved, when the scr is used for ESD protection, the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected to the anode for ESD protection through metal, and the second high-concentration N-type doped region 24 and the second high-concentration P-type doped region 26 are connected to the cathode for ESD protection through metal.
The shallow trench isolation STI 12 in the silicon controlled rectifier without hysteresis effect shown in fig. 4 in the prior art is removed, and then the third high-concentration P-type doped region 22 extends towards the cathode direction to be adjacent to the second high-concentration N-type doped region 24, so that the probability that electrons are injected from the emitter second high-concentration N-type doped region 24 of the parasitic NPN (second high-concentration N-type doped region 24/P well 70/N well60) triode and migrate to reach the interface of the N well60 and the P well 70 is reduced, that is, the current gain (β) of the parasitic NPN triode is reduced, and further the width D2 of the guard ring (first high-concentration N-type doped region 28) required for realizing the hysteresis effect can be reduced, so that the layout area can be saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention, are incorporated in and constitute a part of this specification. The drawings are not necessarily to scale, however, and may not be intended to accurately reflect the precise structural or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of values or properties encompassed by exemplary embodiments in accordance with the invention. The invention will be described in further detail with reference to the following detailed description and accompanying drawings:
fig. 1 is a schematic diagram of the LDMOS hysteresis effect curve of a conventional high-voltage device.
Fig. 2 is a schematic structural diagram of a first conventional scr without hysteresis effect.
Fig. 3 is a relationship diagram of the hysteretic effect curve D2 of the scr without hysteretic effect shown in fig. 2.
Fig. 4 is a schematic structural diagram of a second conventional scr without hysteresis effect.
Fig. 5 is a schematic structural diagram of the present invention.
Fig. 6 is a schematic diagram of the present invention.
Description of the reference numerals
20. 22, 26 represent different high concentration P-type doped regions
24. 28, 30 represent different high concentration N-type doped regions
10. 12, 14, 16 represent different shallow trench isolations
60 denotes an N well
70 denotes a P well
80 denotes a P-type semiconductor substrate
90 denotes a non-metal silicide layer
A represents an anode
C represents a cathode
S represents the width between the first high concentration P type doped region 20 and the first high concentration N type doped region 28
D1 denotes the width between the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22
D2 denotes the widths of the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22 in the prior art structure;
d3 represents the width of the third highly doped P-type region 22 in the inventive structure.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and technical effects of the present invention will be fully apparent to those skilled in the art from the disclosure in the specification. The invention is capable of other embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the general spirit of the invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. The following exemplary embodiments of the present invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technical solutions of these exemplary embodiments to those skilled in the art.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, parameters, components, regions, layers and/or sections, these elements, parameters, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, parameter, component, region, layer or section from another element, parameter, component, region, layer or section. Thus, a first element, parameter, component, region, layer or section discussed below could be termed a second element, parameter, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
A first embodiment;
referring to fig. 5, the present invention provides a scr, comprising:
a P-type semiconductor substrate 80;
an N well60 and a P well 70 formed on the upper portion of the P-type semiconductor substrate 80;
a first high concentration P-type doped region 20 and a first high concentration N-type doped region 28 formed at the upper portion of the N-well 60;
a second high concentration N-type doped region 24 and a second high concentration P-type doped region 26 formed on the upper portion of the P well 70;
a third high concentration P-type doped region 22 formed above the boundary between the N-well 60 and the P-well 70 and adjacent to the second high concentration N-type doped region 24; a non-metal silicide layer 90 is formed on the upper surface of the third high concentration P-type doped region 22;
a first shallow trench isolation 10 is formed on the left side of the first high-concentration P-type doped region 20, a second shallow trench isolation 14 is formed between the second high-concentration N-type doped region 24 and the second high-concentration P-type doped region 26, and a third shallow trench isolation 16 is formed on the right side of the second high-concentration P-type doped region 26;
the first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, the N-well 60, the P-type semiconductor substrate 80 or the P-well 70 and the second high-concentration N-type doped region 24 form a parasitic NPN triode structure, the N-well 60 with the first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, the N-well 60 with the second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the width of the first high-concentration N-type doped region 28 is a third width D2, and the width of the third high-concentration P-type doped region 22 is a fourth width D3.
Accordingly, based on the comparison of the prior art structure shown in fig. 4, it can be found that the width D3 of the third high concentration P-type doped region 22 in fig. 5 should be theoretically greater than the width D3 of the third high concentration P-type doped region 22 in fig. 4.
The silicon controlled rectifier provided by the invention is formed by further improving the structure shown in figure 4 of the existing silicon controlled rectifier without hysteresis effect. The shallow trench isolation STI 12 in the silicon controlled rectifier without hysteresis effect is removed, and then the third high-concentration P-type doped region 22 extends towards the cathode direction to be adjacent to the second high-concentration N-type doped region 24, so that the probability that electrons are injected from the emitter second high-concentration N-type doped region 24 of the parasitic NPN (second high-concentration N-type doped region 24/P well 70/N well60) triode and migrate to reach the interface of the N well60 and the P well 70 is reduced, that is, the current gain (beta) of the parasitic NPN triode is reduced, and further the width D2 of the guard ring (first high-concentration N-type doped region 28) required for realizing the hysteresis effect can be reduced, and therefore, the layout area can be saved.
A second embodiment;
with continued reference to fig. 5, the present invention provides a scr comprising:
a P-type semiconductor substrate 80;
an N well60 and a P well 70 formed on the upper portion of the P-type semiconductor substrate 80;
a first high concentration P-type doped region 20 and a first high concentration N-type doped region 28 formed at the upper portion of the N-well 60;
a second high concentration N-type doped region 24 and a second high concentration P-type doped region 26 formed on the upper portion of the P well 70;
a third high concentration P-type doped region 22 formed above the boundary between the N-well 60 and the P-well 70 and adjacent to the second high concentration N-type doped region 24; a non-metal silicide layer 90 is formed on the upper surface of the third high concentration P-type doped region 22;
a first shallow trench isolation 10 adjacent to the first high concentration P-type doped region 20 and formed in the N-well 60 at the left side of the first high concentration P-type doped region 20;
a second shallow trench isolation 14 adjacent to the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26 and formed in the P-well 70 between the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26;
a third shallow trench isolation 16 adjacent to the second high concentration P-type doped region 26 and formed in the P-well 70 at the right side of the second high concentration P-type doped region 26;
the first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-type semiconductor substrate 80 or the P-well 70 and the second high-concentration N-type doped region 24 form a parasitic NPN triode structure;
an N-well 60 with a first width S is formed between the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28, an N-well 60 with a second width D1 is formed between the first high-concentration N-type doped region 28 and the third high-concentration P-type doped region 22, the width of the first high-concentration N-type doped region 28 is a third width D2, and the width of the third high-concentration P-type doped region 22 is a fourth width D3;
wherein, the first width S scope is 0.2um ~ 10um, and the second width D1 scope is 0.2 ~ 2um, and the third width D2 scope is 0.2um ~ 5um, and the fourth width D3 scope is 0.2um ~ 10 um.
It should be further noted that, regardless of the first embodiment or the second embodiment, the sustain voltage can be adjusted by adjusting the first width S, the third width D2 and the fourth width D3 to achieve the hysteresis-free effect characteristic.
In either of the first and second embodiments, the current gain of the parasitic NPN transistor can be reduced by adjusting the fourth width D3.
In any of the first and second embodiments, the trigger voltage of the hysteresis effect can be adjusted by adjusting the second width D1.
Accordingly, when the first or second embodiment is used for ESD protection, the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected to serve as an anode of the ESD protection structure through metal, and the second high-concentration N-type doped region 24 and the second high-concentration P-type doped region 26 are connected to serve as a cathode of the ESD protection structure through metal, and the specific application structure is shown in fig. 6.
Exemplary embodiments according to the present invention are described herein with reference to schematic cross-sectional views of preferred embodiments (and intermediate structures) as exemplary embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features at its edges and/or a gradient change in implant concentration, rather than just a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation also in the region between the buried region and the surface through which the implantation passes. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of the regions in a device and are not intended to limit the scope of exemplary embodiments in accordance with the invention.
A third embodiment;
the invention provides a manufacturing method of a silicon controlled rectifier, which comprises the following steps:
s1, forming N well60 and P well 70 in P-type semiconductor substrate 80;
s2, forming a first high-concentration P-type doped region 20 and a first high-concentration N-type doped region 28 in the N well60, forming a second high-concentration N-type doped region 24 and a second high-concentration P-type doped region 26 in the P well60, and forming a third high-concentration P-type doped region 22 at the boundary of the N well60 and the P well 70, wherein the third high-concentration P-type doped region 22 is adjacent to the second high-concentration N-type doped region 24; a non-metal silicide layer 90 is formed on the upper surface of the third high concentration P-type doped region 22;
the first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-type semiconductor substrate 80 or the P-well 70 and the second high-concentration N-type doped region 24 form a parasitic NPN triode structure;
an N-well 60 with a first width S is formed between the first high concentration P-type doped region 20 and the first high concentration N-type doped region 28, an N-well 60 with a second width D1 is formed between the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22, the first high concentration N-type doped region 28 has a third width D2, and the third high concentration P-type doped region 22 has a fourth width D3.
A fourth embodiment;
the invention provides a manufacturing method of a silicon controlled rectifier, which comprises the following steps:
s1, forming N well60 and P well 70 in P-type semiconductor substrate 80;
then, manufacturing shallow trench isolation;
the first shallow trench isolation 10 is formed in the N-well 60 at the left side of the first high concentration P-type doped region 20 and is adjacent to the first high concentration P-type doped region 20;
the second shallow trench isolation 14 is formed in the P-well 70 between the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26 and is adjacent to the second high concentration N-type doped region 24 and the second high concentration P-type doped region 26;
the third shallow trench isolation 16 is formed in the P-well 70 on the right side of the second high concentration P-type doped region 26 and is adjacent to the second high concentration P-type doped region 26.
S2, forming a first high-concentration P-type doped region 20 and a first high-concentration N-type doped region 28 in the N well60, forming a second high-concentration N-type doped region 24 and a second high-concentration P-type doped region 26 in the P well60, and forming a third high-concentration P-type doped region 22 at the boundary of the N well60 and the P well 70, wherein the third high-concentration P-type doped region 22 is adjacent to the second high-concentration N-type doped region 24; a non-metal silicide layer 90 is formed on the upper surface of the third high concentration P-type doped region 22;
the first high-concentration P-type doped region 20, the N-well 60 and the P-well 70 form a parasitic PNP triode structure, and the N-well 60, the P-type semiconductor substrate 80 or the P-well 70 and the second high-concentration N-type doped region 24 form a parasitic NPN triode structure;
an N-well 60 with a first width S is formed between the first high concentration P-type doped region 20 and the first high concentration N-type doped region 28, an N-well 60 with a second width D1 is formed between the first high concentration N-type doped region 28 and the third high concentration P-type doped region 22, the first high concentration N-type doped region 28 has a third width D2, and the third high concentration P-type doped region 22 has a fourth width D3.
Wherein, the first width S scope is 0.2um ~ 10um, and the second width D1 scope is 0.2 ~ 2um, and the third width D2 scope is 0.2um ~ 5um, and the fourth width D3 scope is 0.2um ~ 10 um.
It should be further noted that, in any of the third embodiment and the fourth embodiment, the sustain voltage can be adjusted by adjusting the first width S, the third width D2 and the fourth width D3 to achieve the hysteresis-free effect characteristic.
In any of the third and fourth embodiments, the current gain of the parasitic NPN transistor can be reduced by adjusting the fourth width D3.
In any of the third and fourth embodiments, the trigger voltage of the hysteresis effect can be adjusted by adjusting the second width D1.
Accordingly, when either the third or fourth embodiment is used for ESD protection, the first high-concentration P-type doped region 20 and the first high-concentration N-type doped region 28 are connected by metal to serve as an anode of the ESD protection structure, and the second high-concentration N-type doped region 24 and the second high-concentration P-type doped region 26 are connected by metal to serve as a cathode of the ESD protection structure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present invention has been described in detail with reference to the specific embodiments and examples, but these are not intended to limit the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (14)
1. A silicon controlled rectifier, comprising:
a P-type semiconductor substrate (80);
an N well (60) and a P well (70) formed on the upper portion of a P-type semiconductor substrate (80);
a first high concentration P-type doped region (20) and a first high concentration N-type doped region (28) formed on the upper part of the N well (60);
a second high concentration N-type doped region (24) and a second high concentration P-type doped region (26) formed on the upper part of the P well (70);
a third high concentration P-type doped region (22) formed above the boundary of the N-well (60) and the P-well (70) and adjacent to the second high concentration N-type doped region (24); a non-metal silicide layer is formed on the upper surface of the third high-concentration P-type doped region (22);
an N well (60) with a first width (S) is formed between the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28), an N well (60) with a second width (D1) is formed between the first high-concentration N-type doped region (28) and the third high-concentration P-type doped region (22), the width of the first high-concentration N-type doped region (28) is a third width (D2), and the width of the third high-concentration P-type doped region (22) is a fourth width (D3).
2. The silicon controlled rectifier of claim 1 further comprising:
a first shallow trench isolation (10) which is adjacent to the first high-concentration P-type doped region (20) and is formed in the N well (60) on the left side of the first high-concentration P-type doped region (20);
a second shallow trench isolation (14) which is adjacent to the second high-concentration N-type doped region (24) and the second high-concentration P-type doped region (26) and is formed in the P well (70) between the second high-concentration N-type doped region (24) and the second high-concentration P-type doped region (26);
and a third shallow trench isolation (16) which is adjacent to the second high-concentration P-type doped region (26) and is formed in the P well (70) on the right side of the second high-concentration P-type doped region (26).
3. The silicon controlled rectifier of claim 1 wherein: the first width (S) range is 0.2um ~ 10um, the second width (D1) range is 0.2 ~ 2um, the third width (D2) range is 0.2um ~ 5um, the fourth width (D3) range is 0.2um ~ 10 um.
4. The silicon controlled rectifier of claim 1 wherein: the non-hysteresis effect characteristic can be realized by adjusting the first width (S), the third width (D2) and the fourth width (D3) to adjust the maintaining voltage.
5. The silicon controlled rectifier of claim 1 wherein: which can reduce the current gain of the parasitic NPN transistor by adjusting the fourth width (D3).
6. The silicon controlled rectifier of claim 1 wherein: the trigger voltage of the hysteresis effect can be adjusted by adjusting the second width (D1).
7. The SCR of any of claims 1-6, wherein: when the ESD protection structure is used for ESD protection, the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28) are connected through metal to serve as an anode of the ESD protection structure, and the second high-concentration N-type doped region (24) and the second high-concentration P-type doped region (26) are connected through metal to serve as a cathode of the ESD protection structure.
8. A method for manufacturing a silicon controlled rectifier is characterized by comprising the following steps:
s1, forming an N well (60) and a P well (70) in a P-type semiconductor substrate (80);
s2, forming a first high-concentration P-type doped region (20) and a first high-concentration N-type doped region (28) in the N well (60), forming a second high-concentration N-type doped region (24) and a second high-concentration P-type doped region (26) in the P well (60), and forming a third high-concentration P-type doped region (22) at the boundary of the N well (60) and the P well (70), wherein the third high-concentration P-type doped region (22) is adjacent to the second high-concentration N-type doped region (24); a non-metal silicide layer is formed on the upper surface of the third high-concentration P-type doped region (22);
an N well (60) with a first width (S) is formed between the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28), an N well (60) with a second width (D1) is formed between the first high-concentration N-type doped region (28) and the third high-concentration P-type doped region (22), the width of the first high-concentration N-type doped region (28) is a third width (D2), and the width of the third high-concentration P-type doped region (22) is a fourth width (D3).
9. The method of claim 8, wherein: adding a step of manufacturing shallow trench isolation between the steps S1 and S2;
the first shallow trench isolation (10) is formed in the N well (60) on the left side of the first high-concentration P-type doped region (20) and is adjacent to the first high-concentration P-type doped region (20);
the second shallow trench isolation (14) is formed in the P well (70) between the second high-concentration N-type doped region (24) and the second high-concentration P-type doped region (26) and is adjacent to the second high-concentration N-type doped region (24) and the second high-concentration P-type doped region (26);
a third shallow trench isolation (16) is formed in the P-well (70) on the right side of the second high concentration P-type doped region (26) and adjacent to the second high concentration P-type doped region (26).
10. The method of claim 8, wherein: the first width (S) ranges from 0.2um to 10um, the second width (D1) ranges from 0.2um to 2um, the third width (D2) ranges from 0.2um to 5um, and the fourth width (D3) ranges from 0.2um to 10 um.
11. The method of claim 8, wherein: in step S2, the hysteresis-free effect characteristic is achieved by adjusting the sustain voltage by adjusting the first width (S), the third width (D2), and the fourth width (D3).
12. The method of claim 8, wherein: in step S2, the current gain of the parasitic NPN transistor is reduced by adjusting the fourth width (D3).
13. The method of claim 8, wherein: in step S2, the trigger voltage at the time of hysteresis effect is adjusted by adjusting the second width (D1).
14. The method of manufacturing a silicon controlled rectifier as claimed in any one of claims 8 to 13, wherein: when the high-concentration N-type doped region is used for ESD protection, the first high-concentration P-type doped region (20) and the first high-concentration N-type doped region (28) are connected with an anode for ESD protection through metal, and the second high-concentration N-type doped region (24) and the second high-concentration P-type doped region (26) are connected with a cathode for ESD protection through metal.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602404A (en) * | 1995-01-18 | 1997-02-11 | National Semiconductor Corporation | Low voltage triggering silicon controlled rectifier structures for ESD protection |
| KR20160050817A (en) * | 2014-10-31 | 2016-05-11 | 심진섭 | Apparatus for preventing high voltage electrostatic discharge |
| CN108183101A (en) * | 2017-12-28 | 2018-06-19 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602404A (en) * | 1995-01-18 | 1997-02-11 | National Semiconductor Corporation | Low voltage triggering silicon controlled rectifier structures for ESD protection |
| KR20160050817A (en) * | 2014-10-31 | 2016-05-11 | 심진섭 | Apparatus for preventing high voltage electrostatic discharge |
| CN108183101A (en) * | 2017-12-28 | 2018-06-19 | 上海华力微电子有限公司 | Without echo effect thyristor type esd protection structure and its implementation |
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