CN112510003B

CN112510003B - Semiconductor packaging structure and manufacturing method thereof

Info

Publication number: CN112510003B
Application number: CN202011373144.3A
Authority: CN
Inventors: 陈佳
Original assignee: Joulwatt Technology Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2023-07-18
Anticipated expiration: 2040-11-30
Also published as: CN112510003A

Abstract

The invention provides a semiconductor packaging structure, which increases the adsorption force of a PI layer by slotting the surface of a passivation layer and can absorb partial stress generated at an interface, thereby reducing the warping risk of the PI layer. The quality and the service life of the semiconductor device are increased. The invention also provides a manufacturing method of the semiconductor packaging structure.

Description

Semiconductor packaging structure and manufacturing method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor packaging structure and a manufacturing method thereof.

Background

In recent years, with the development of high-power supply chips with high current, redistribution layer (RDL) wiring has been widely used, but after packaging, when high-speed temperature, humidity and bias test (bias HAST) experiments are performed, metal diffusion problems (mainly at the bottom of RDL) occur in RDLs with different adjacent potentials, so that short circuits occur in different RDLs.

In patent CN107808865a, a package structure for inhibiting surface migration of metal ions in a humid environment is disclosed, as shown in fig. 1, in this patent, a dielectric layer design with different heights is adopted, so that two adjacent RDLs 340 (1) and 340 (2) are located at different heights, where a raised dielectric layer 330 (1) is located under the RDL340 (1), and by means of this raised dielectric layer 330 (1), the height 332 of the RDL340 (1) is higher than the height of the RDL340 (2), so that the distance 334 between two adjacent RDLs is enlarged, so that the migration path of metal ions is enlarged, and the risk of short-circuiting between adjacent metals is reduced.

However, this approach to increasing the path, while somewhat mitigating the risk of shorting, does not essentially address metal ion migration in humid environments. One approach is to coat the surface of the RDL with a Polymer (PI) that is used to prevent moisture intrusion and thus metal diffusion on the RDL (moisture intrusion, which accelerates copper migration).

However, PI itself is an absorbent material, and in a long-term humid environment, PI layers are also subject to moisture intrusion, thereby degrading insulation between adjacent RDLs. On the other hand, the PI layer and the dielectric layer (usually an oxide layer) on the surface of the device have different young's modulus parameters, so that the interface between the PI layer and the dielectric layer has stronger stress, and the stress can lead to the PI layer to warp and form a certain-layer separation, and finally lead to electrochemical drift between two adjacent RDLs and current leakage or short circuit between adjacent metal layers.

Accordingly, there is a need to improve upon the deficiencies of the prior art and to provide a new package structure.

Disclosure of Invention

In view of the above, the present invention is directed to a new semiconductor package structure, which can overcome the problem of short circuit caused by metal ion migration between RDLs in the prior art, thereby improving the performance and service life of the device.

The semiconductor package structure according to the object of the present invention comprises

The substrate comprises a first dielectric layer positioned on the surface;

a redistribution conductive layer disposed on the first dielectric layer, the redistribution conductive layer including a first RDL segment and a second RDL segment adjacent the first RDL segment,

a semiconductor device structure disposed under the first dielectric layer, the semiconductor device structure including a first device conductive line electrically connected to the first RDL segment, a second device conductive line electrically connected to the second RDL segment, and a third metal line disposed between the first device conductive line and the second device conductive line, wherein,

the first dielectric layer is provided with at least one slot corresponding to the area above the third metal line, the slot blocks at least one leakage path of the first RDL section and the second RDL section, and

and a second dielectric layer is covered on at least the first dielectric layer between the first RDL section and the second RDL section, and the second dielectric layer is filled in the grooves.

Preferably, the slot is a strip slot, and the length direction of the strip slot is consistent with the length direction of the first RDL segment.

Preferably, the slot is a hole slot.

Preferably, the hole-shaped slot comprises a hole array formed by a plurality of holes, and the hole array is one of a regular array, a staggered array or an irregular array.

Preferably, the depth of the slot is such that the portion of the third metal line located below is exposed to the bottom of the slot.

Preferably, the first RDL segment and the second RDL segment are electrically isolated from each other; when the semiconductor device works, a potential difference exists between the first RDL section and the second RDL section, and the third metal wire is not connected with any potential or the potential of the third metal wire is the same as the higher potential between the first RDL section and the second RDL section.

Preferably, the third metal layer is a dummy metal line.

Preferably, the first dielectric layer is a passivation layer, and the second dielectric layer is a PI layer.

According to an object of the present invention there is provided a method of manufacturing a semiconductor package as described above,

providing a substrate, manufacturing a device structure on the substrate, wherein the device structure comprises a first dielectric layer positioned on the surface of the substrate, and a semiconductor device structure positioned below the first dielectric layer, and the semiconductor device structure comprises a first device conductive wire, a second device conductive wire and a third metal wire arranged between the first device conductive wire and the second device conductive wire;

manufacturing a redistribution conductive layer on the first dielectric layer, etching the redistribution conductive layer to form a first RDL section and a second RDL section, exposing the first dielectric layer between the first RDL section and the second RDL section, wherein the first RDL section is electrically connected with the first device conductive wire, and the second RDL section is electrically connected with the second device conductive wire;

etching a first dielectric layer between the first RDL section and the second RDL section to form at least one slot, and enabling the slot to be located above the third metal line;

and manufacturing a second dielectric layer, wherein the second dielectric layer at least covers the first dielectric layer between the first RDL section and the second RDL section, and the second dielectric layer is filled in the grooves.

Compared with the prior art, the invention has the following technical effects:

1. by adding slots on the leakage paths, the migration path distance of metal ions is increased, and the risk of short circuit between adjacent RDLs is reduced.

2. The grooves enable the PI layer to be embedded into the grooves, the adhesion force of the PI layer is increased, the combination between the PI layer and the passivation layer is tighter, the layering phenomenon caused by stress is reduced, and the effect of blocking metal ion migration is better achieved.

3. When the depth of the groove is such that the dummy metal wire is exposed, metal ions migrate into the groove and are attached by the dummy metal wire, so that the metal ions migrated to the groove cannot escape, and the problem of short circuit caused by metal ion migration is fundamentally solved.

Drawings

Fig. 1 is a schematic diagram of a prior art semiconductor package structure.

Fig. 2 is a cross-sectional view of the package structure of the present invention.

Fig. 3 is a top view of a package structure according to a first embodiment of the present invention.

Fig. 4 is a top view of a package structure according to a second embodiment of the present invention.

Fig. 5 is a top view of a package structure according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the specific embodiments shown in the drawings, but these embodiments are not limited to the present invention, and structural, method, or functional modifications made by those skilled in the art based on these embodiments are included in the scope of the present invention.

As described in the background art, in the conventional semiconductor package structure, although metal ions cannot migrate between adjacent RDLs by covering the PI layer, a large stress is generated on the interface due to the difference between the young's modulus of the PI layer and the passivation layer below, so that the PI layer is separated and separated, thereby reducing the blocking effect on the metal ions. For a long time, the device still faces the risk of short circuits.

Therefore, in order to solve the above problems, the present invention proposes a new packaging structure, which increases the contact area between the PI layer and the passivation layer by grooving the passivation layer, and the stress at the interface between the PI layer and the passivation layer will make the PI layer embedded in the grooving firmly grasp, so that the PI layer can be better attached to the passivation layer. In addition, the invention also provides that the open groove is arranged on the dummy metal wire, and the dummy metal wire is exposed at the bottom of the open groove, and because the dummy metal wire generally has the same potential as the device metal wire with higher potential, metal ions can be adsorbed by the dummy metal wire when moving into the open groove, so that the metal ions can not escape, and the problem of short circuit caused by metal ion migration is fundamentally solved.

The technical scheme of the invention will be described in detail through the following specific embodiments.

Referring to fig. 2, fig. 2 is a schematic cross-sectional view of the semiconductor package structure of the present invention. As shown in the drawing, the semiconductor package structure includes a substrate 10, a semiconductor device or a part of a device structure (not shown) having a specific function, such as a PN junction for conducting or cutting off a semiconductor, and a metal or nonmetal device conductive layer 12 for providing a corresponding potential of the PN junction, which is formed in the substrate 10 through a process of manufacturing the semiconductor device. Typically, the device conductive layer 12 may comprise different layers, each of which is patterned by patterning to form a different conductive line pattern. In fig. 2, only the top device conductive layer 12 is shown, which is commonly referred to as a top metal layer (top metal) in a typical process.

On the other hand, in order to satisfy the physical strength or electrical performance of the semiconductor device or part of the device structure inside the substrate 10, the surface of the substrate 10 needs to be provided with the first dielectric layer 11, and in one practical application, the first dielectric layer 11 is formed on the surface of the substrate 10 in the form of a passivation layer (passivation layer), so as to at least cover the internal device structure, especially a metal layer (top metal) located on top of the device structure, thereby achieving the protection and electrical isolation effects.

The first dielectric layer 11 is provided with a redistribution conductive layer 13 (RDL), and the redistribution conductive layer 13 is patterned to form different RDL segments, each RDL segment occupying a corresponding position to satisfy input/output characteristics between the semiconductor device and an external electronic component. Basically, the redistribution conductive layer 13 includes at least a first RDL segment 131 and a second RDL segment 132 adjacent to the first RDL segment 131, where the first RDL segment 131 and the second RDL segment 132 are electrically isolated from each other, and when the semiconductor device is operated, a potential difference exists between the first RDL segment 131 and the second RDL segment 132, such as a high potential is connected to the first RDL segment 131 and a low potential is connected to the second RDL segment 132, thereby forming a potential difference. The potential difference may come from the operating characteristics requirements of the semiconductor device itself, or may be a response and matching requirement to an external device.

In general, the pattern of the redistribution layer 13 has a certain correspondence with the device conductive layer 12 disposed under the first dielectric layer 1, and the two are electrically connected through conductive via pillars disposed in the first dielectric layer 11. As shown in fig. 2, in the device conductive layer 12, a first device conductive line 121 electrically connected to the first RDL segment 131 and a second device conductive line 122 electrically connected to the second RDL segment 132 are included, and the first device conductive line 121 and the second device conductive line 122 are spatially extended to a desired location for connection to an external device through the first RDL segment 131 and the second RDL segment 132. Meanwhile, a third metal line 123 is further disposed between the first device conductive line 121 and the second device conductive line 122, and in one embodiment, the third metal line 123 is, for example, a dummy metal line, to compensate the technical density of the device and avoid the influence of noise in the device on the key signal. In one embodiment, the third metal line 123 is floated, i.e., does not have any potential connected thereto, and in another embodiment, is connected to a high potential, i.e., has the same potential as the higher potential of the first RDL segment 131 or the second RDL segment 132. The first device conductive line 121, the second device conductive line 122, and the third metal line 123 run substantially uniformly.

Referring to fig. 2 again, the region of the first dielectric layer 11 above the third metal line 123 is provided with at least one slot 111, and the slot 111 blocks at least one leakage path of the first RDL segment 131 and the second RDL segment 132. That is, if metal ion migration occurs in the first RDL segment 131 and the second RDL segment 132, the slot 111 will allow metal ions to fall into the slot 111 as shown by the arrows representing the trajectories of the metal ions. In this way, on the one hand, the metal ion migration path can be increased, and on the other hand, the resistance to be overcome by the metal ion migration is also increased.

On the first dielectric layer 11, there is also provided a second dielectric layer 14, the second dielectric layer 14 covering the area between the first RDL segment 131 and the second RDL segment 132, and the second dielectric layer 14 is filled in the slot 111. The second dielectric layer 14, such as a polymer layer (PI), is filled over the redistribution layer 13 to isolate individual RDL segments. Because the slotting is arranged on the area between the first RDL segment 131 and the second RDL segment 132, which is equivalent to increasing the roughness of the surface of the first dielectric layer 11, the contact area of the second dielectric layer 14 is increased, and when stress occurs at the interface of the two layers of dielectrics, the slotting can be used for releasing to a certain extent, so that the risks of falling and tilting at the interface are avoided.

Referring to fig. 3, fig. 3 is a top view of a package structure according to a first embodiment of the present invention. As shown, in this first embodiment, the slot 111 is a stripe slot, and the length direction of the stripe slot coincides with the length direction of the first RDL segment 131 (or the second RDL segment 132). That is, if metal ion migration occurs, the length direction of the strip-shaped slot is perpendicular to the ion migration direction, so that the ion migration path can be blocked to the greatest extent. The illustrated embodiment only shows the case of 1 slot, and as a simple extension, a plurality of parallel grooves can be arranged, so that the difficulty of ion migration can be increased.

Referring to fig. 4, fig. 4 is a top view of a package structure according to a second embodiment of the present invention. As shown, in this embodiment, the slot 111' is a hole slot, which includes an array of holes. The number of holes may be at least 1 depending on the length and width of the third metal line 123. The hole array in fig. 4 is a regular matrix, and a dislocation matrix may also be formed, that is, the holes between adjacent rows are arranged in a dislocation manner, so that the blocking effect on the leakage path may be increased. It can also be arranged in an irregular array, and by randomly covering on the migration path of the metal ions, the probability of blocking the metal ions is greatly increased.

Referring to fig. 5, fig. 5 is a cross-sectional view of a package structure according to a third embodiment of the invention. As shown, in this third embodiment, the depth of the groove 111 "is such that the portion of the third metal line 123 located below is exposed to the bottom of the groove 111". That is, when the first dielectric layer 11 is etched, the first dielectric layer 11 is etched through, so that the third metal line 123 below is exposed. This has the advantage that since the third metal line is normally at a high potential or floating, if it itself is at a high potential, escaping metal ions from the high potential fall into the slot 111 "and then contact the third metal line 123 to be adsorbed. And if it floats, after the metal ions contact the third metal line 123, the potential thereof is pulled up by the third metal line 123 to also have the effect of a high potential. Therefore, by utilizing the characteristics of the third metal line 123, the escaping metal ions from the high potential can be trapped, and the problem of electric leakage can be fundamentally solved.

The method for manufacturing the package structure of the present invention is described below.

The manufacturing method of the semiconductor packaging structure comprises the following steps:

s1, providing a substrate, and manufacturing a device structure on the substrate, wherein the device structure comprises a first dielectric layer positioned on the surface of the substrate, and a semiconductor device structure positioned below the first dielectric layer, and the semiconductor device structure comprises a first device conductive wire, a second device conductive wire and a third metal wire arranged between the first device conductive wire and the second device conductive wire;

s2, manufacturing a redistribution conductive layer on the first dielectric layer, etching the redistribution conductive layer to form a first RDL section and a second RDL section, exposing the first dielectric layer between the first RDL section and the second RDL section, wherein the first RDL section is electrically connected with the first device conductive wire, and the second RDL section is electrically connected with the second device conductive wire;

s3, etching the first dielectric layer between the first RDL section and the second RDL section to form at least one slot, and enabling the slot to be located above the third metal line;

s4, manufacturing a second dielectric layer, wherein the second dielectric layer at least covers the first dielectric layer between the first RDL section and the second RDL section, and the second dielectric layer is filled in the grooves.

In a preferred embodiment, the depth of the slot is such that the portion of the third metal line lying below is exposed to the bottom of the slot. Therefore, the escaped metal ions can be captured by the third metal wire after falling into the slot, so that the problem of electric leakage is fundamentally solved.

In summary, the present invention provides a semiconductor package structure, which increases the adsorption force of the PI layer by slotting the surface of the passivation layer and can absorb the stress generated at part of the interface, thereby reducing the risk of PI layer warpage. The quality and the service life of the semiconductor device are increased.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. A semiconductor package structure, characterized in that: comprising

The substrate comprises a first dielectric layer positioned on the surface;

2. The semiconductor package according to claim 1, wherein: the slotting is a strip slotting, and the length direction of the strip slotting is consistent with the length direction of the first RDL section.

3. The semiconductor package according to claim 1, wherein: the slot is a hole slot.

4. A semiconductor package according to claim 3, wherein: the hole-shaped slot comprises a hole array formed by a plurality of holes, and the hole array is one of a regular array, a staggered array or an irregular array.

5. The semiconductor package according to any one of claims 1 to 4, wherein: the depth of the slot is such that the portion of the third metal line located below is exposed to the bottom of the slot.

6. The semiconductor package according to claim 5, wherein: the first RDL section and the second RDL section are electrically isolated from each other; when the semiconductor device works, a potential difference exists between the first RDL section and the second RDL section, and the third metal wire is not connected with any potential or the potential of the third metal wire is the same as the higher potential between the first RDL section and the second RDL section.

7. The semiconductor package according to claim 1, wherein: the third metal line is a dummy metal line.

8. The semiconductor package according to claim 1, wherein: the first dielectric layer is a passivation layer, and the second dielectric layer is a PI layer.

9. A method of fabricating a semiconductor package according to any one of claims 1-8, wherein:

10. The method for manufacturing a semiconductor package according to claim 9, wherein: the depth of the slot is such that the portion of the third metal line located below is exposed to the bottom of the slot.