TWI731431B - Pad structure - Google Patents

Abstract

A pad structure includes a conductive layer, a pad layer, a protective layer and a dielectric layer. The conductive layer is located above the substrate. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the substrate and between the conductive layer and pad layer. The conductive layer includes a number of effective blocks, and a proportion of a block area of a block of the effective blocks to a total block area of the effective blocks ranges between 40%~50%. The block has a hollow portion, wherein the hollow portion has a hollow area, and a ratio of the hollow area to the block area ranged between 0.1 and 0.5.

Description

Pad structure

The present invention relates to a pad structure, and more particularly to a pad structure with a conductive layer.

In the conventional manufacturing process of the CUP (Circuit Under Pad) structure, the force exerted by the tool on the CUP structure during the wire bonding process and the force exerted by the tool on the CUP structure during the circuit test process easily cause the dielectric layer between the two conductive layers of the CUP structure to occur. Cracks or cracks in the intermetal dielectric layer of the same conductive layer. Therefore, how to propose a new CUP structure to improve the aforementioned problems is one of the directions of the industry in this technical field.

The present invention relates to a pad structure, which can improve the aforementioned conventional problems.

An embodiment of the present invention provides a pad structure. The pad structure includes a plurality of conductive layers, a pad layer, a protective layer and a dielectric layer. The conductive layer is part of a circuit. The protective layer covers the pad layer and has an opening to expose a part of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and completely separates the conductive layer and the pad layer in the area of the opening. The conductive layer includes several effective blocks. One of the effective blocks has a block area of the first block and one of the effective blocks has a total block area. The ratio is between 40% and 50%. The first block has at least one hollow part, the hollow part has a hollow area, and the ratio of the hollow area to the block area is between 0.1 and 0.5.

Another embodiment of the present invention provides a pad structure. The pad structure includes a plurality of conductive layers, a pad layer, a protective layer and a dielectric layer. The conductive layer is part of a circuit. The protective layer covers the pad layer and has an opening to expose a part of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and separates the conductive layer and the pad layer in the area of the opening. The conductive layer includes a first block and a second block. The first block and the second block have a first width and a second width, respectively, and there is a first block and a second block between the first block and the second block. For an interval, the first width, the second width, and the first interval are dimensions along the same direction. The first width and the second width are both greater than a threshold width, and the first interval is greater than a threshold interval.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

10: substrate

100: pad structure

110: conductive layer

111: The first block

111a: hollow part

112: second block

113: The third block

114: fourth block

114’: block

120: mating layer

130: protective layer

130a: opening

140: Dielectric layer

145: Dielectric materials

A1: Total block area

A2: The total area of the hollow

A3: Block area

S12: first interval

S34: second interval

T1, T2: minimum spacing

W1: first width

W2: second width

W3: third width

W4: Fourth width

W4’: width

FIG. 1A is a schematic diagram of a pad structure according to an embodiment of the present invention.

FIG. 1B is a top view of the conductive layer of the pad structure of FIG. 1A.

Figures 2A to 2H show schematic diagrams of the hollow parts of other embodiments.

3A to 3B show schematic diagrams of conductive layers in other embodiments.

Figures 4A~4B show the design process diagram of the conductive layer of the pad structure in Figure 1B.

Please refer to FIGS. 1A and 1B. FIG. 1A is a schematic diagram of the pad structure 100 according to an embodiment of the present invention, and FIG. 1B is a top view of the conductive layer 110 of the pad structure 100 in FIG. 1A.

As shown in FIG. 1A, the pad structure 100 can be formed on a substrate 10, which is, for example, a circuit board or a wafer. In one embodiment, the at least one pad structure 100 and the substrate 10 are, for example, at least a part of a chip, where the chip is, for example, a central processing unit (CPU).

As shown in FIG. 1A, the pad structure 100 includes a plurality of conductive layers 110, a pad layer 120, a protective layer 130 and a plurality of dielectric layers 140. The protective layer 130 covers the pad layer 120 and has an opening 130a to expose a part of the pad layer 120, so that bonding wires (not shown) are formed on the pad layer 120 through the opening 130a. At least one of the dielectric layers 1405 is formed between the conductive layers 110 to separate the conductive layers 110. One of the dielectric layers 1405 is formed between the conductive layers 110 and the substrate 10 to separate the conductive layers 110 and the substrate 10. One of these dielectric layers 1405 is formed between the conductive layer 110 and the pad layer 120 to separate the conductive layer 110 and the pad layer 120.

The conductive layer 110 is formed on the substrate 10 and the conductive layer 110 also includes a dielectric material 145 therein. In this embodiment, the pad structure 100 is, for example, a CUP structure, so the conductive layers 110 are a part of at least one circuit. As shown in FIG. 1A, in the area of the opening 130a, the conductive layers 110 are separated from each other by the dielectric layer 140, but outside the top view area of the opening 130a, the two conductive layers 110 can pass through the conductive holes penetrating the dielectric layer 140 (conductive via) (not shown) is electrically connected. Similarly, in the area of the opening 130a, the pad layer 120 and the conductive layer 110 penetrate the dielectric layer 140 are separated from each other, but outside the top-view area of the opening 130a, the pad layer 120 and the conductive layer 110 can be electrically connected through a conductive hole (not shown) penetrating the dielectric layer 140.

As shown in FIG. 1B, the conductive layer 110 includes several blocks (such as the thick-lined area in FIG. 1B), such as a first block 111, a second block 112, a third block 113, and a fourth block 114 . The first block 111, the second block 112, the third block 113, and the fourth block 114 are separated from each other, and each block is a continuous extension block. The first block 111, the second block 112, the third block 113, and the fourth block 114 are all projected from the conductive layer 110 to the portion of the opening 130a (that is, the dashed frame shown in FIG. 1B). In addition, the embodiment of the present invention does not limit the number of blocks, which may be less than four or more than four.

As shown in FIG. 1B, among these blocks, a block with a block area greater than a threshold value may have at least one hollow portion 111a. For example, the block area of the first block 111 is greater than the threshold value, so the first block 111 has at least one hollow part 111a. The area of the block here refers to the top-view area shown in FIG. 1B, that is, the area surrounded by the outer boundary of the first block 111 (the part beyond the opening 130a is defined by the boundary of the opening 130a). Each hollow part 111a can be filled with a dielectric material 145. The dielectric material 145 is an inter-metal dielectric (IMD). In addition, the dielectric material 145 can also be filled between the two blocks. Compared with the block without the hollow part 111a, the first block 111 with the hollow part 111a can increase the stiffness of the conductive layer 110, avoid the deformation of the conductive layer 110 caused by the force of the wire bonding process, and avoid the dielectric layer Cracks occurred in 140 and dielectric material 145.

The aforementioned threshold value may be a preset ratio of an area to the total area A1 of a plurality of valid blocks, and the preset ratio is, for example, between 40% and 50%. Advance one In other words, among these blocks, the block area of the first block 111, the block area of the second block 112, and the block area of the third block 113 are larger than an effective block area, so the first block The block 111, the second block 112, and the third block 113 are defined as valid blocks. "Effective blocks" refer to blocks that are eligible to be included in the calculation of the total block area A1. The total block area A1 is the sum of the block area of the first block 111, the block area of the second block 112, and the block area of the third block 113. Since the block area of the fourth block 114 is smaller than the effective block area, it is not included in the calculation of the total block area A1. In an embodiment, the effective block area is, for example, 10% of the closed area of the opening 130a.

Only the effective block with a block area between 40% and 50% of the total area A1 needs to form the hollow part 111a. In this embodiment, among these effective blocks, only the block area of the first block 111 is between 40% and 50% of the total area A1, so only the hollow portion 111a is formed in the first block 111. In another embodiment, the threshold may be higher than 50% or lower than 40%. When the threshold value is lower, the conductive layer 110 is hollowed out, which will cause the resistance of the conductive layer 110 to increase. When the threshold value is higher, the hollow portion of the conductive layer 110 is reduced, and the effect of improving the rigidity of the conductive layer 110 is not significant. Since the threshold value of the embodiment of the present invention is between 40% and 50%, the dual effects of the excellent conductivity of the conductive layer 110 and the improvement of rigidity can be taken into consideration.

The sum of the areas of all the hollow parts 111a of the first block 111 is the total hollow area A2. In an embodiment, the ratio (A2/A3) of the total hollow area A2 of the first block 111 to the block area A3 of the first block 111 is between 0.1 and 0.5. In this way, the conductive layer 110 has sufficient rigidity to resist the force applied during the wire bonding process, so as to avoid the hollow part. The dielectric material 145 in 111a is cracked. The aforementioned block area A3 is, for example, the area surrounded by the outer boundary of the first block 111.

As shown in FIG. 1B, the shape of the hollow portion 111a is, for example, a rectangle, and the minimum distance T1 between the hollow portion 111a and the outer boundary of the first block 111 is, for example, between 5 μm and 10 μm. The minimum distance T2 between two adjacent hollow portions 111a is, for example, between 5 μm and 10 μm.

As shown in FIG. 1B, the first block 111 and the second block 112 have a first width W1 and a second width W2, respectively. There is a first interval S12 between the first block 111 and the second block 112. A width W1, a second width W2, and a first interval S12 are the dimensions along the same direction. Both the first width W1 and the second width W2 are greater than a threshold width, and the first interval S12 is greater than the threshold interval. In this way, the conductive layer 110 can provide sufficient rigidity to resist the force applied during the wire bonding process, and prevent the dielectric material 145 from cracking due to the deformation of the conductive layer 110. In one embodiment, the aforementioned threshold width is, for example, equal to or greater than 10 microns, and the aforementioned threshold interval is, for example, equal to or greater than 2 microns (minimum 2 microns).

In addition, if the width of the block is smaller than the threshold width, the interval between the two blocks may not be considered to be enlarged. For example, as shown in Figure 1B, the third block 113 and the fourth block 114 have a third width W3 and a fourth width W4, respectively, and there is a second interval S34 between the third block 113 and the fourth block 114 . Both the third width W3 and the fourth width W4 are smaller than the threshold width, indicating that the block has a certain rigidity (the larger the width, the larger the block area, the lower the block rigidity), so the second interval S34, such as the second interval, may not be considered S34 can be smaller than the threshold interval.

Please refer to FIGS. 2A to 2H, which illustrate a schematic diagram of the hollow portion 111a of other embodiments. It can be seen from these drawings that in the same block, the shape of one of the hollow portions 111a can be a polygon, such as a square, a rectangle, a strip, a trapezoid, etc., but it can also be a circle or an ellipse. In addition, the shapes of any two of the plurality of hollow portions 111a may be the same or different. Several hollow parts 111a can be arranged parallel to each other. The hollow part 111a can be arranged obliquely or in parallel with respect to the side of the block.

Please refer to FIGS. 3A to 3B, which show schematic diagrams of the conductive layer 110 in other embodiments. It can be seen from these figures that the width W4' of the block 114' is smaller than the threshold width, so the interval S14 between two adjacent blocks 114' and the first block 111 can be smaller than the threshold interval.

Although the foregoing embodiment is described by taking one of the conductive layers 110 as an example, this is not intended to limit the embodiment of the present invention. Any of the aforementioned conductive layers 110 can have the aforementioned structure, and will not be repeated here.

Please refer to FIGS. 4A to 4B, which illustrate the design process diagram of the conductive layer 110 of the pad structure 100 in FIG. 1B. The design process of each conductive layer 110 of the pad structure 100 is the same as the following process.

First, as shown in FIG. 4A, a preliminary designed pattern of the conductive layer 110' is provided. The pattern of the conductive layer 110' may be determined according to the circuit function of the pad structure 110 and/or the substrate 10, which is not limited in the embodiment of the present invention.

Then, the area of the opening 130a is defined.

Then, several blocks of the conductive layer 110' are determined, each block is a continuous extension block, and any two blocks are separated from each other. According to this principle, it is determined in the conductive layer 110' The first block 111', the second block 112, the third block 113, and the fourth block 114. Next, calculate the block area of each block. For example, the block area of the first block 111', the block area of the second block 112, the block area of the third block 113, and the block area of the fourth block 114 are obtained by calculation. Then, the blocks whose block area is smaller than the effective block area are excluded. In this example, the block area of the fourth block 114 is smaller than the effective block area, so the fourth block 114 is not considered in the subsequent design process.

Then, among these blocks, the block with a block area greater than a threshold value is selected. For example, the total block area of the first block 111', the second block 112, and the third block 113 is A1, and the threshold value is, for example, 40%-50%. Among the first block 111', the second block 112 and the third block 113, only the block area of the first block 111' is between 40% and 50% of the total block area A1, so the first block is selected The block 111 is used as an object for forming the hollow part 111a.

Then, as shown in FIG. 4B, at least one hollow portion 111a is formed in the first block 111' to form the first block 111. In the actual semiconductor manufacturing process, the hollow portion 111a is filled with the dielectric material 145. Since the first block 111 has a hollow portion 111a and is filled with the dielectric material 145, the rigidity of the first block 111 can be improved.

Then, the rigidity of the conductive layer 110 can be increased by increasing the gap between the two regions to prevent the dielectric layer 140 between the two conductive layers 110 (shown in the pad structure 100 in FIG. 1A) from cracking during the wire bonding process . For example, in any two adjacent blocks, it is determined whether the width of each block is greater than the threshold width, wherein the width direction of each block is in the same direction; if so, it is determined whether the interval between the two blocks is smaller than the threshold interval. If the interval between the two blocks is smaller than the threshold interval, the interval between the two blocks is enlarged to be substantially equal to or greater than the threshold interval.

For further example, as shown in FIG. 4B, the first width W1 of the first block 111 and the second width W2 of the second block 112 are greater than the threshold width, and the difference between the first block 111 and the second block 112 The interval S12' is smaller than the threshold interval, so the interval S12' between the first block 111 and the second block 112 can be enlarged to the interval S12 shown in Figure 1B, wherein the interval S12 is substantially equal to or greater than the threshold interval .

In another embodiment, if the interval between the first block 111 and the second block 112 is greater than the threshold interval, a zone with a width smaller than the threshold width can be added between the first block 111 and the second block 112 The block is, for example, the fourth block 114' shown in FIG. 3A.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

110: conductive layer

111: The first block

111a: hollow part

112: second block

113: The third block

114: fourth block

130a: opening

145: Dielectric materials

S12: first interval

S34: second interval

T1, T2: minimum spacing

W1: first width

W2: second width

W3: third width

W4: Fourth width

Claims (10)

A pad structure is formed on a substrate and includes: a conductive layer, which is a part of a circuit; a pad layer; and a protective layer covering the pad layer and having an opening to expose part of the pad Layer; a dielectric layer formed between the conductive layer and the pad layer and completely isolated the conductive layer and the pad layer in the area of the opening; wherein the conductive layer includes a plurality of effective areas, A ratio of a block area of a first block of one of the effective blocks to a total block area of one of the effective blocks is between 40% and 50%, and the first block has a hollow portion , The hollow part has a hollow area, and the ratio of the hollow area to the area of the block is between 0.1 and 0.5. A pad structure is formed on a substrate and includes: a conductive layer, which is a part of a circuit; a pad layer; and a protective layer covering the pad layer and having an opening to expose part of the pad Layer; a dielectric layer formed between the conductive layer and the pad layer and completely separate the conductive layer and the pad layer in the area of the opening; wherein the conductive layer includes a first block And a second block, the first block and the second block have a first width and a second width, respectively, a first interval is formed between the first block and the second block, the The first width, the second width and the first width An interval is a dimension along the same direction, the first width and the second width are both greater than a threshold width, and the first interval is greater than a threshold interval; wherein, the threshold width is equal to or greater than 10 microns, and the threshold interval is equal to Or larger than 2 microns. As for the pad structure described in item 1 or 2, wherein the first block is the part where the conductive layer is projected to the opening. In the pad structure described in item 1 or 2 of the scope of patent application, the area of the block is the area surrounded by the outer boundary of the first block. As for the pad structure described in item 1 of the scope of patent application, the area of each effective block is greater than 10% of the opening area of one of the openings. In the pad structure described in claim 1, wherein the minimum distance between the hollow portion and the outer boundary of the first block is between 5 μm and 10 μm. As for the pad structure described in claim 1, wherein the first block includes a plurality of hollow portions, and the minimum distance between two adjacent hollow portions is between 5 μm and 10 μm. As for the pad structure described in claim 1, wherein the first block includes a plurality of hollow parts, and the hollow parts are parallel to each other. In the pad structure described in item 1 of the scope of patent application, the shape of the hollow portion is polygonal, circular or elliptical. In the pad structure described in item 2 of the scope of patent application, the first block and the second block are the portions of the conductive layer projected to the opening.

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