JP2013105986A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a mechanical strength of a semiconductor device having an air gap without increasing the number of processes.SOLUTION: In a semiconductor device manufacturing method, an annular via 1R is formed by connecting a conductive material required for a semiconductor device, such as an outline via of a via array; a region of an insulation film 2 is surrounded by the annular via 1R; in formation of an air gap, the region surrounded by the conductive material remains to form a non-air gap region 4 and the insulation film 2 is removed from the other region of the insulation film 2 to form an air gap region 3.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a multilayer wiring structure and a manufacturing method thereof.

  In order to increase the speed of the semiconductor device, it is important to suppress the wiring delay. The wiring delay is determined by the product of wiring resistance and wiring capacitance. Wiring resistance is reduced by using a highly conductive wiring material, and interwiring capacitance is reduced by using an interlayer insulating film having a low dielectric constant. Currently, low-resistance copper is used as the wiring material. However, there is only an expensive metal material such as silver or gold as the low-resistance material to further reduce the wiring resistance, which further suppresses wiring delay. The key is to further reduce the inter-wiring capacitance. Therefore, a method of providing an air gap has been proposed as a method of lowering the dielectric constant further than that of a low dielectric constant insulating film.

  However, the mechanical strength is reduced by the air gap, which causes the deterioration of the aluminum slide and via due to the stress, the collapse of the upper layer, and the like, affecting the yield.

  Patent Document 1 discloses forming a reinforcing insulating layer in order to compensate for a decrease in mechanical strength due to an air gap.

WO2007 / 020688

  The formation of the reinforcing insulating layer disclosed in Patent Document 1 requires the formation of a mask pattern for forming the reinforcing insulating layer, resulting in an increase in the number of processes and an increase in cost.

  In the present invention, an area where the insulating film is removed as an air gap and a non-air gap area where the insulating film is not removed are separated by a conductive material used for wiring, vias, etc. Strength is also improved.

That is, according to one embodiment of the present invention,
Wiring formed on the substrate;
An air gap formed around at least a side surface of the wiring;
There is provided a semiconductor device having at least a part of the air gap and a first insulating material surrounded by a conductive material in the same layer.

Also, according to one embodiment of the present invention,
Forming a layer of a first insulating material on a substrate;
Forming a recess including at least one annular recess in the layer made of the first insulating material;
Burying a conductive material in the recess;
Removing the first insulating material to form an air gap except for the first insulating material surrounded by the conductive material embedded in the annular recess,
A method for manufacturing a semiconductor device is provided.

  In the present invention, since the air gap region and the non-air gap region in which the insulating film is left are separated by using a conductive material to be formed, an insulating layer having excellent mechanical strength is included without increasing the number of steps. A non-air gap region can be formed.

It is a plane layout figure of a wiring pattern. FIGS. 2A and 2B are plan views showing a state before and after forming an air gap in the via array VA1 shown in FIG. 1, and FIGS. 2A1 and 2A2 show a via array having a conventional structure to which the present invention is not applied. (B1) and (b2) show via arrays to which the present invention is applied. FIG. 3 is a plan view showing a state before and after forming an air gap in the via array VA2 shown in FIG. 1, and FIG. 3 (a) shows a via array having a conventional structure to which the present invention is not applied before forming an air gap; 3 (b1) and 3 (b2) show the states before and after the formation of the air gap in the via array to which the present invention is applied. 2A and 2B are plan views showing an example in which the via array VA1 shown in FIG. 1 is a plurality of annular vias, where FIG. 1A shows before the air gap is formed, and FIG. It is process sectional drawing explaining the manufacturing process of the multilayer wiring structure which concerns on the example of 1 embodiment of this invention. It is a top view of wiring and a dummy pattern concerning another example of an embodiment. It is an enlarged view of the area | region C of FIG. It is sectional drawing in the AB line | wire of FIG. 6, and shows the example which formed the multilayer wiring structure. It is a flowchart explaining the process of the pattern data generation which concerns on another example of embodiment. It is a top view which shows the modification of the pattern shown in FIG. It is a top view which shows the other modification of the pattern shown in FIG.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these exemplary embodiments.

Embodiment 1
FIG. 1 is a plan layout diagram of a wiring pattern to which the present invention is applied, and shows a lower layer wiring extending in the Y direction and an upper layer wiring extending in the X direction at the same time. Normally, the wiring width of signals etc. that are wired over the entire area of the semiconductor chip, including the power supply wiring, is wired with a large width to reduce the wiring resistance, and vias that conduct between the upper and lower wiring layers are not in such a thick wiring. It is formed in a plurality of arrays. For example, in the via array VA1, 6 × 6 vias are arrayed, and in the via array VA2, 2 × 2 vias are arrayed. The thin wiring portion is connected by a single via SV.

  In this embodiment, by connecting the vias outside the plurality of arrayed vias in an annular shape, the insulating film included in the annular via is not removed when the insulating film is removed when forming the air gap. Thus, a non-air gap region is obtained, which makes it possible to improve the mechanical strength.

  FIG. 2 is a plan view showing a state before and after the air gap is formed in the via array VA1 shown in FIG. Among these, FIGS. 2A1 and 2A2 show via arrays having a conventional structure to which the present invention is not applied, and FIGS. 2B1 and 2B2 show via arrays to which the present invention is applied.

  In the via array having the conventional structure, as shown in FIG. 2A2, all of the insulating film 2 between the vias 1 is removed, and an air gap region 3 is also formed between the vias. On the other hand, in the via array to which the present invention is applied, as shown in FIG. 2 (b1), an annular via 1R in which outer vias are connected to each other and a via 1 similar to the conventional one are provided inside the via 1R. The insulating film 2 is separated by 1R. When the insulating film 2 is removed to form the air gap, the insulating film on the outer periphery of the via 1R is removed to form the air gap region 3, but the insulating film 2 inside the via 1R is not removed, and the non-air gap region 4 is removed. Is formed.

  Thus, by making the outer contour of the arrayed vias annular, the inner insulating film can be left without being affected by the etching at the time of forming the air gap. As a result, since the wiring width is large and the insulating film in the via portion having a large stress is not removed, a decrease in mechanical strength can be suppressed without increasing the manufacturing process and manufacturing cost.

  The reason why vias are formed in the array is that it is difficult to form large vias and small vias simultaneously on the wafer surface in the process, and uniform vias can be formed by aligning the via dimensions. It is to be done. In the annular via 1R to which the present invention is applied, the width is the same as that of the normal via 1 and can be formed simultaneously with the normal via 1.

  The annular via 1R can also be applied to the via array VA2 shown in FIG. That is, as shown in FIG. 3A, if at least four vias 1 are arranged in a 2 × 2 manner, as shown in FIG. 3B1, the vias are connected to each other to form a ring. Via 1R. Then, as shown in FIG. 3 (b2), when the insulating film 2 is removed to form the air gap, the insulating film on the outer periphery of the via 1R is removed to form the air gap region 3, but the insulation inside the via 1R is removed. The film 2 is not removed, and a non-air gap region 4 is formed. In addition, the strength of the via itself is thus reinforced by making it annular.

  On the other hand, the via array VA1 may be connected to each via arranged in 2 × 2 to form an array of a plurality of annular vias R1 as shown in FIG. Also in this case, as shown in FIG. 4B, when the insulating film 2 is removed to form the air gap, the insulating film on the outer periphery of the via 1R is removed to form the air gap region 3, but the inner side of the via 1R. The insulating film 2 is not removed, and a non-air gap region 4 is formed.

  FIG. 5 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to this embodiment. First, a wiring layer is formed in multiple layers according to a conventional method. Here, as the wiring 11, for example, a copper wiring can be used. After such a copper wiring forms a barrier metal and a seed film (not shown) in a recess (wiring groove) formed in the insulating film 12 of each layer, It can be formed by a so-called damascene method in which a copper film is formed by electrolytic plating and the copper film is embedded by CMP (chemical mechanical polishing). At this time, the via may be formed simultaneously with the wiring by a so-called dual damascene method in which the first etching for forming a via hole serving as a via pattern in the insulating film 12 and the second etching for forming a wiring groove are continuously performed. it can. For the via arrays VA1 and VA2, the annular via 1R according to this embodiment is formed. For example, silicon oxide (first insulating material) can be used for the insulating film 12, and an insulating material having an etching selectivity with respect to the insulating film 12 as an etching stopper film and a diffusion prevention film between the wiring layers. A film made of (second insulating material), for example, a silicon nitride film 13 is formed (see FIG. 5A). A protective layer 14 made of a silicon nitride film is also formed on the uppermost wiring layer. In this example, an example in which five wiring layers are formed is shown, but the present invention is not limited to this, and any multilayer wiring structure having at least two layers may be used.

  Next, the insulating film 12 is removed to form an air gap. Prior to this removal, an opening 15 for removing the insulating film 12 is formed (FIG. 5B). The opening 15 is formed so as to penetrate all the insulating films 12 forming the air gap and avoid the wiring 11.

  A chemical solution, for example, hydrofluoric acid is injected from the opening 15 and the insulating film 12 is removed to form the air gap region 3 (herein, also referred to as an air gap layer since it is viewed in the layer direction). At this time, the insulating film 12 surrounded by the annular via 1 </ b> R is not removed and remains as the non-air gap region 4. Thereafter, the injected hydrofluoric acid or the like is washed and removed by washing with water or the like, and dried to obtain the structure of FIG.

  In addition to forming the vias simultaneously with the wiring by the dual damascene method as described above, the via hole is formed in the insulating film made of the first insulating material having the via height to form the via, and then the first via for forming the wiring is formed. An insulating film made of the above insulating material may be laminated to connect the wiring and the via. Further, the wiring material is not limited to copper, and other conductive materials such as aluminum may be used. From the viewpoint of reducing the wiring resistance, it is preferable to use copper or a copper alloy. Further, when wire bonding is required such as the uppermost layer wiring, aluminum wiring may be more advantageous than copper wiring. The conductive material can be appropriately selected according to the purpose.

  Further, the shape of the annular via 1R is not limited to the illustrated rectangular shape, and may be formed in a polygonal shape such as a hexagon or an octagon, or a circular shape.

  Further, when there is no adjacent via array in a weak portion, a dummy via array may be formed and reinforced by applying the present invention.

Embodiment 2
In Embodiment 2, a mode in which the non-air gap region 4 is formed using another conductive layer will be described.

  As described in the first embodiment, wiring formed by a damascene method such as a copper wiring is planarized by a CMP method. At this time, when the difference in density of the pattern becomes large, so-called dishing, in which the insulating film is drowned at a rough portion, occurs. Therefore, in order to suppress such dishing and maintain the flatness of the polished surface, it is a common practice to provide a dummy pattern separately from the wiring pattern.

  In this embodiment, a configuration in which the non-air gap region 4 is formed by connecting the dummy patterns with a wiring material will be described.

  FIG. 6 is a plan view showing an example of this embodiment. A dummy pattern (CMP dummy 22) formed of the same material as that of the wiring 21 is disposed around the wiring 21, and each CMP dummy 22 is connected by a connection portion 23 of the wiring material. In the region surrounded by the CMP dummy 22 and the connection portion 23, an insulating film remains to form a non-air gap region 4, and an air gap region 3 is formed around the wiring 21. The air gap regions 3 separated via the non-air gap region 4 are connected to each other by a communication path 24. In the figure, reference numeral 25 denotes an opening serving as a chemical solution inlet when forming the air gap region. Each air gap region 3 is connected to the air gap region 3 via the communication path 24 from the opening 25 so that the insulating film can be removed. FIG. 7 is an enlarged view of a region C surrounded by a broken line in FIG. FIG. 8 is a cross-sectional view taken along the line AB of FIG. 6 and shows an example in which a multilayer wiring structure is formed.

  FIG. 9 shows a flowchart of pattern data generation according to the present embodiment.

  First, pattern data of the normal wiring 21 and the CMP dummy 22 is generated by a conventional method (S1). Next, a wiring group (signal line group) including at least one wiring is grouped without interposing a dummy pattern (S2). Each wiring group is connected by at least one path (communication path 24) (S3). After confirming that all the wiring groups are connected, a wiring (connecting portion 23) pattern that connects the dummy patterns of the adjacent CMP dummy 22 is generated using the path (communication path 24) connecting the wiring groups as a prohibited region (see FIG. S4). Pattern data is output as described above, and a mask pattern is manufactured based on the pattern data.

  Thereafter, using this mask pattern, as described in the first embodiment, a wiring, a CMP dummy, and a connection portion are formed for each wiring layer by the damascene method. By removing the insulating film, the multilayer wiring structure shown in FIG. 8 can be obtained.

  In the example shown in FIG. 6, adjacent CMP dummies 22 are connected by one connecting portion 23, so that one non-air gap is formed in an area surrounded by four CMP dummies 22 arranged at each of the rectangular vertices. Although the example in which the region 4 is formed is shown, the present invention is not limited to this, and a plurality of connection portions may be used for connection. For example, FIG. 10 shows an example in which two non-air gap regions 4 are formed between two adjacent CMP dummies 22 by connecting adjacent CMP dummies 22 with two connecting portions 23. . Thus, the mechanical strength can be further improved by connecting the CMP dummy 22 with two or more connecting portions 23. However, if the number of connection portions is excessively increased, the original purpose of the CMP dummy may be impaired. Therefore, it is important to arrange the connection portions so as not to impair the function as the CMP dummy.

  Further, it is not necessary for all CMP dummy 22 to be connected by a connecting portion, and as shown in FIG. 11, the connecting portion 23 can be arranged at a portion that becomes a boundary with the air gap region 3. As a result, a CMP dummy 22a connected by the connecting portion 23 and a CMP dummy 22b not connected by the connecting portion 23 exist. In this way, it is possible to reduce the increase in load during CMP by reducing the number of connection portions 23 as much as possible. Alternatively, a dummy wiring that connects the CMP dummy 22 that are separated from each other may be disposed as a connection portion 23 along the boundary with the air gap region 3 to form the non-air gap region 4 that leaves an insulating film.

1 via 1R annular via 2 insulating film 3 air gap region 4 non-air gap region 11 wiring 12 insulating film 13 silicon nitride film 14 protective film 15 opening 21 wiring 22 CMP dummy 23 connecting portion 24 communication path 25 opening VA1, VA2 via array

Claims (20)

Wiring formed on the substrate;
An air gap formed around at least a side surface of the wiring;
A semiconductor device comprising: at least a part of the air gap; and a first insulating material surrounded by a conductive material in the same layer.   The semiconductor device according to claim 1, wherein the conductive material is an annularly formed via connected under the wiring.   The semiconductor device according to claim 2, wherein the annularly formed via is formed by connecting at least four corresponding vias having the same size as a single via formed.   4. The semiconductor device according to claim 2, comprising the via formed in an annular shape and at least one independent via in an inner periphery of the annular formed via.   The wiring is a wiring formed by a damascene method, and has a dummy pattern of the same material as that of the wiring to be a CMP dummy via an air gap in a plane direction with respect to the wiring, and the first insulating material is at least 2 2. The semiconductor device according to claim 1, wherein two dummy patterns are arranged in a region where the dummy patterns are connected by a connection portion made of the same material as the wiring.   One connecting portion is arranged between adjacent dummy patterns, and the first insulating material is arranged in a region surrounded by the four dummy patterns arranged at each of the rectangular vertices and the connecting portion. Item 6. The semiconductor device according to Item 5.   6. The semiconductor according to claim 5, wherein at least two connection portions are disposed between adjacent dummy patterns, and the first insulating material is disposed in a region surrounded by the two adjacent dummy patterns and the connection portions. apparatus.   A plurality of wiring groups including one or a plurality of wirings in a plane direction are provided, each wiring group is separated by the dummy pattern, and an air gap surrounding at least two adjacent wiring groups is a communication path between the dummy patterns. The semiconductor device according to claim 5, wherein the semiconductor device is in communication with each other.   The wiring has a multilayer wiring structure of at least two layers, and an air gap of each layer is separated in a layer thickness direction by a layer of a second insulating material different from the first insulating material. The semiconductor device according to any one of the above. Forming a layer of a first insulating material on a substrate;
Forming a recess including at least one annular recess in the layer made of the first insulating material;
Burying a conductive material in the recess;
Removing the first insulating material to form an air gap except for the first insulating material surrounded by the conductive material embedded in the annular recess,
A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 10, wherein the recess is a via hole that forms a via connected to a wiring, and includes at least one annular via hole.   The method of manufacturing a semiconductor device according to claim 10, wherein the recess includes a via hole that forms a via connected to a wiring and a wiring groove that forms the wiring, and the annular recess is at least one of the via holes.   The method of manufacturing a semiconductor device according to claim 12, wherein the via hole and the wiring groove are formed by a dual damascene method.   The method for manufacturing a semiconductor device according to claim 11, comprising an independent via hole in an inner peripheral region of the annular via hole.   11. The method of manufacturing a semiconductor device according to claim 10, wherein the recess includes a wiring groove for forming a wiring, a dummy pattern recess serving as a CMP dummy, and a connection recess for connecting the dummy patterns.   The method of manufacturing a semiconductor device according to claim 15, wherein the concave portion for connecting portion is a single groove that connects the adjacent concave portions for dummy pattern.   The method of manufacturing a semiconductor device according to claim 15, wherein the recess for the connection portion is at least two grooves that connect the adjacent recesses for the dummy pattern. Data for forming the concave portion is
Generating data including a wiring pattern and a dummy pattern;
Grouping into a wiring group including one or more wirings without interposing a dummy pattern;
Setting a route connecting each wiring group;
Generating a connection part pattern for connecting the dummy patterns with the path as a prohibited area; and
The method of manufacturing a semiconductor device according to claim 15, wherein the semiconductor device is generated by a data generation step comprising:   19. The method according to claim 15, further comprising a step of forming a conductive material on the insulating film in which the concave portion is formed, and then planarizing the conductive material by a chemical mechanical polishing method to bury the conductive material in the concave portion. Semiconductor device manufacturing method. At least two layers including a layer made of the first insulating material, a layer made of a second insulating material different from the first insulating material, and a wiring formed in the layer made of the first insulating material Forming a multilayer wiring structure;
Forming an opening exposing the layer made of the first insulating material of each layer;
20. The method for manufacturing a semiconductor device according to claim 10, further comprising a step of removing the first insulating material of each layer collectively through the opening.

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