CN112509937A - Electric on-off test method for double-sided substrate - Google Patents
Electric on-off test method for double-sided substrate Download PDFInfo
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- CN112509937A CN112509937A CN202011376754.9A CN202011376754A CN112509937A CN 112509937 A CN112509937 A CN 112509937A CN 202011376754 A CN202011376754 A CN 202011376754A CN 112509937 A CN112509937 A CN 112509937A
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The invention discloses an electric on-off test method of a double-sided substrate, which comprises the following steps of 1, in the preparation process of the double-sided substrate, etching is not carried out on a front side electroplating seed layer, and the front side electroplating seed layer is reserved; step 2, completing the back process of the double-sided substrate on the double-sided substrate with the front side electroplating seed layer, etching the back side electroplating seed layer, then carrying out a first single-side probe test on the back side salient points of the double-sided substrate, and measuring the electric connection and disconnection relation between every two back side salient points; and step 3: etching the front electroplating seed layer in the area except the front salient points, carrying out a second single-sided probe test on the front salient points of the double-sided substrate, and measuring the electrical connection and disconnection relation between every two front salient points; and 4, step 4: and (3) combining the first single-sided probe test result in the step (2) and the second single-sided probe test result in the step (3) to obtain the electrical connection test result between the salient points on the front surface and the back surface of the double-sided substrate. The method solves the problem of the electrical connection and disconnection test of the silicon switching substrate wafer, and is suitable for automatic mass production test.
Description
Technical Field
The invention belongs to the technical field of advanced electronic packaging, and particularly belongs to an electric on-off test method of a double-sided substrate.
Background
For many years, the technology development speed of packaging substrates including ceramic substrates and organic substrates is far slower than that of integrated circuit IC chips, at present, the advanced integrated circuit IC chips mostly adopt a micro-bump array outer pin form, the number of pins is thousands, the pin density is increased, and meanwhile, the large size and low-K dielectric layers of the IC chips are extremely challenging for traditional packaging substrates such as ceramic substrates and organic substrates with poor flatness and obvious thermal mismatch. TSV silicon Interposer substrates (Si interposers) are introduced as bridges between advanced integrated circuit IC chips and traditional package substrates such as ceramic substrates, organic substrates, and the like. One or more IC chips are assembled on the TSV silicon transfer substrate in a micro mode, and the interconnection among the IC chips is completed by using low-loss and high-density metal wiring on the surface of the TSV silicon transfer substrate, so that the number and density of the whole outer pins are reduced; the IC chip on the TSV silicon transfer substrate is transferred to the traditional packaging substrates such as the ceramic substrate and the organic substrate by utilizing the electrical interconnection of the TSV conductive through holes in the vertical direction. The TSV silicon Interposer (Si Interposer) provides a good chip integration platform: the high-speed signal interconnection is supported by good thermal matching, RCL parasitic influence is reduced, power consumption and ESD requirements are reduced, signal conduction, heat transfer, mechanical support and mechanical stress buffering are achieved, and technical gaps between an IC chip and a traditional packaging substrate are made up.
Typically, the TSV silicon interposer substrate has distributed on both its top and bottom surfaces pin pads or (micro) bumps that are electrically interconnected in the vertical direction by TSV conductive vias. The thickness of the TSV Silicon interposer substrate is mainly in the range of 200 to 50 microns due to the limitation of the diameter and the aspect ratio of the TSV (Through-Silicon-Via) hole and the consideration of the electrical signal transmission capability of the TSV hole. Because the silicon material is brittle and fragile, especially for large-size (8 inches and 12 inches) TSV silicon transfer substrate wafers with the thickness of less than 100 micrometers, the TSV silicon transfer substrate wafers are large in warpage, weak in stress capacity and high in risk of fragment and fragment, and a traditional flying probe platform is difficult to directly carry out double-sided flying probe testing.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an electric on-off testing method of a double-sided substrate, which solves the electric on-off testing problem of an ultrathin large-size silicon transfer substrate wafer, is compatible with the existing commercial equipment, and is suitable for automatic mass production testing.
In order to achieve the purpose, the invention provides the following technical scheme:
an electrical on-off test method for a double-sided substrate comprises the following processes,
and 4, combining the first single-sided probe test result in the step 2 and the second single-sided probe test result in the step 3 to obtain an electrical connection test result between the salient points on the front surface and the back surface of the double-sided substrate.
Preferably, in step 1, in the preparation process of the double-sided substrate, the blind holes and the front-side metal wiring are firstly completed, and after the front-side under-bump metal layer and the front-side bump are prepared, the complete electroplating seed layer is reserved.
Furthermore, the front metal wirings are horizontally and electrically connected and arranged on the front surface of the silicon substrate, when the front metal wirings are in a plurality of layers, the front metal wirings of each layer are electrically insulated through a medium between the front metal layers, and the front metal wirings of each layer are electrically connected through connecting holes between the layers.
Preferably, in step 2, before the first single-sided probe test is performed on the back bump, the front surface of the double-sided substrate and the front surface carrier are temporarily bonded together, the back surface of the double-sided substrate is thinned, so that the blind holes form conductive through holes, then the back surface metal wiring and the back surface bump are sequentially performed, and the electroplating seed layer is etched, so that the back surface process of the double-sided substrate is completed.
Further, in step 3, before the front side salient points are subjected to the second single-side probe test, the back side of the double-sided substrate and the back side carrier are temporarily bonded together, the front side carrier is debonded, the front side carrier is removed, and the front side of the double-sided substrate is exposed.
Furthermore, the back metal wirings are horizontally and electrically connected and arranged on the back of the silicon substrate, when the back metal wirings are in a plurality of layers, the back metal wirings of each layer are electrically insulated through a back metal interlayer medium, and the back metal wirings of each layer are electrically connected through connecting holes among the layers.
Preferably, the front bump lower metal layer or the back bump lower metal layer is prepared by adopting patterned electroplating.
Preferably, in step 2, when the back side bumps are subjected to the first single-side probe test, all the front side bumps are in a parallel short circuit relationship.
Preferably, the double-sided substrate is a TSV silicon via substrate, a TGV glass via substrate or an organic substrate.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides an electric on-off testing method of a double-sided substrate, which combines wafer-level electric on-off probe testing with a preparation process flow of the double-sided substrate, converts the through hole vertical electric interconnection on-off detection of the original double-sided substrate wafer needing double-sided probe testing into two single-sided probe tests, and realizes the interconnection on-off testing which can be completed only by the double-sided probe testing through the two single-sided probe tests in the preparation process. The electric connection and disconnection relation between the front salient point and the back salient point of the TSV silicon switching substrate is judged by measuring the electric connection and disconnection relation between the back salient points of the TSV silicon switching substrate and the electric connection and disconnection relation between the front salient points of the TSV silicon switching substrate in sequence, and the electric connection and disconnection test problem of the ultrathin double-sided substrate is solved by replacing one-time double-sided probe test with two-time single-sided probe test.
Furthermore, the front side and the back side of the double-sided substrate are temporarily bonded with the slide glass, so that the two single-sided testing processes are carried out under the condition that the double-sided substrate wafer is bonded with the slide glass, although the thickness of the double-sided substrate wafer is very thin and generally less than 200 microns, because the double-sided substrate wafer is supported and protected by the slide glass, the problem of splintering and fragmenting in the processes of transferring, testing and holding is avoided, the implementation of the testing process is facilitated, and the automatic mass production testing operation is carried out.
Drawings
Fig. 1 is a schematic cross-sectional view of a TSV silicon interposer substrate according to an embodiment of the invention.
FIG. 2 is a schematic diagram of an electrical connection relationship between bumps on the upper and lower surfaces of a TSV silicon interposer substrate in accordance with an embodiment of the present invention.
FIG. 3 is a diagram of electrical connections between bumps on the upper and lower surfaces of a TSV silicon interposer substrate in accordance with an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view of a substrate with a TSV blind via, a front side multi-layer metal wiring, and a front side bump according to an embodiment of the invention.
Fig. 5 is a schematic cross-sectional view illustrating a back process of a TSV silicon via substrate according to an embodiment of the invention.
Fig. 6 is a diagram of an electrical connection relationship between bumps on the upper and lower surfaces when a first single-sided probe test is performed on the bumps on the back surface of the TSV silicon interposer substrate according to the embodiment of the invention.
Fig. 7 is a schematic cross-sectional view illustrating the TSV silicon interposer substrate after the back side is temporarily bonded to the back side carrier 16 and the front side carrier 14 on the front side of the TSV silicon interposer substrate is removed according to an embodiment of the present invention.
FIG. 8 is a cross-sectional view of a portion of a front under bump metallurgy layer etched away in a local area according to an embodiment of the invention.
In the drawings: 1 is a silicon substrate; 2 is a conductive through hole; 3 is a front metal wiring; 4 is a front metal interlayer medium; 5 is a front electroplating seed layer; 6 is a salient point lower metal layer on the front surface; 7 is a salient point on the front surface; 8 is back metal wiring; 9 is a back metal interlayer medium; 10 is a back side plating seed layer; 11 is a back bump lower metal layer; 12 is a back bump; 13 is a front temporary bonding glue layer; 14 is a front slide; 15 is a back temporary bonding glue layer; and 16 is a back slide.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
The invention provides an electric on-off test method of a double-sided substrate, which is not only suitable for electric on-off test of an ultrathin TSV silicon transfer substrate wafer, but also suitable for electric on-off test of an ultrathin TGV glass transfer substrate wafer, and simultaneously can be used for electric on-off test of an ultrathin organic substrate, namely suitable for electric on-off test of all ultrathin double-sided substrates. In the following embodiments, a TSV silicon interposer is taken as an example.
Examples
As shown in fig. 1, the TSV conductive via 2 penetrating the silicon substrate 1 achieves electrical connection between the upper and lower surfaces of the silicon substrate 1. The front metal wiring 3 is arranged on the upper surface of the silicon substrate 1 in a horizontal electric connection mode, the number of the front metal wiring 3 is at least 1, when the front metal wiring 3 is multiple layers, the front metal wiring 3 of each layer is electrically insulated through a front metal interlayer dielectric 4, and the front metal wiring 3 of each layer is electrically connected through a connecting hole between the layers. The front surface bump 7 is electrically connected to the front surface metal wiring 3 through a front surface Under Bump Metallurgy (UBM) 6. Correspondingly, the back metal wiring 8 is horizontally and electrically connected and arranged on the lower surface of the silicon substrate 1, the number of the back metal wiring 8 is at least 1, when the back metal wiring 8 is multilayer, the back metal wiring 8 is electrically insulated through a back metal interlayer dielectric 9, and the back metal wiring 8 is electrically connected through a connecting hole between the layers. The back bump 12 is electrically connected to the back metal wiring 8 through a back Under Bump Metallurgy (UBM) 11.
As shown in fig. 2, the electrical connection relationship between the bumps on the upper and lower surfaces of the TSV silicon interposer substrate is as follows, the front bumps a1, B1, a2, B2, A3, B3, a4 and B4 are respectively electrically connected with the back bumps a1 ', B1', a2 ', B2', A3', B3', a4 'and B4' through the corresponding TSV conductive vias 2, and the electrical connection and disconnection relationship between two bumps is divided into four cases: (1) as shown in fig. 2, the convex points A1, B1, A1 'and B1': bumps a1 and B1 are not electrically conductive in the front-side metal wiring layer, nor are bumps a1 'and B1' electrically conductive in the back-side metal wiring layer. (2) As shown in fig. 2, the convex points A2, B2, A2 'and B2': bumps a2 and B2 are not electrically conductive in the front-side metal wiring layer, and bumps a2 'and B2' are electrically conductive in the back-side metal wiring layer. (3) As with bumps A3, B3 and A3', B3' in fig. 2, bumps A3 and B3 are electrically conductive in the front-side metal wiring layer, and bumps A3 'and B3' are not electrically conductive in the back-side metal wiring layer. (4) As shown in fig. 2, the convex points A4, B4, A4 'and B4': bumps A3 and B3 have electrical continuity in the front-side metal wiring layer, and bumps A3 'and B3' have electrical continuity in the back-side metal wiring layer.
As shown in fig. 3, fig. 3 is a simplified diagram of the electrical connection relationship between the bumps on the upper and lower surfaces of fig. 2, showing the electrical connection and disconnection relationship between two bumps on the upper and lower surfaces of the TSV silicon interposer substrate. The ports a1, B1, a2, B2, A3, B3, a4 and B4 represent bumps (or pads) on the front side (upper surface) of the TSV silicon interposer substrate, and the ports a1 ', B1', a2 ', B2', A3', B3' and a4 'and B4' represent bumps (or pads) on the back side (lower surface) of the TSV silicon interposer substrate. The TSV conductive via 2 between the upper and lower surfaces is shown by a line. Whether multiple bumps (or pads) on one surface are routed to another surface through one TSV via, or one bump (or pad) on one surface is routed to another surface through multiple TSV vias, is simplified into one bump and one TSV hole.
As shown in fig. 4, after the TSV silicon interposer completes the preparation of the TSV blind via, the front-side metal wiring 3, the front-side under bump metal layer (UBM)6, and the front-side bump 7, the front-side plating seed layer 5 under the front-side under bump metal layer (UBM)6 in other regions on the surface is not etched, but the front-side plating seed layer 5 under the front-side under bump metal layer (UBM)6 is completely retained, and all the front-side bumps 7 are electrically connected together through the front-side plating seed layer 5 under the front-side under bump metal layer (UBM)6, so as to test the buried-down pen for the single-side probe on the back side of the subsequent. The front temporary bonding glue layer 13 temporarily bonds the front surface of the TSV silicon interposer substrate and the front carrier 14 together.
As shown in fig. 5, after the backside Under Bump Metallurgy (UBM)11 and the backside bump 12 are prepared, the backside plating seed layer 10 under the backside Under Bump Metallurgy (UBM)11 in other regions of the surface is etched away normally, unlike the front side.
As shown in fig. 6, fig. 6 is a diagram illustrating an electrical connection relationship between upper and lower surface bumps when a first single-sided probe test is performed on the backside bump of the TSV silicon interposer substrate. All the front bumps 7 are in parallel short circuit relation.
As shown in fig. 7, fig. 7 is a schematic cross-sectional view of the TSV silicon interposer substrate after temporarily bonding the backside of the TSV silicon interposer substrate to the backside carrier 16 and removing the front carrier 14 on the front side of the TSV silicon interposer substrate. The front surface of the TSV silicon transfer substrate is exposed, and the front surface electroplating seed layer 5 below the front surface under bump metal layer (UBM)6 still keeps the whole surface of the TSV silicon transfer substrate intact. The temporary bonding between the back surface of the TSV silicon interposer substrate and the back carrier 16 is realized through a back temporary bonding glue layer 15.
As shown in fig. 8, fig. 8 is a schematic cross-sectional view of the front side plating seed layer 5 under the front side Under Bump Metallurgy (UBM)6 after being etched away. The front plating seed layer 5 under the front Under Bump Metallurgy (UBM) in the other region than the region of the front Under Bump Metallurgy (UBM)6 and the front under bump metallurgy (7) in fig. 7 is etched away, so that the front bumps are separated and the front Under Bump Metallurgy (UBM)6 is separated, as shown in fig. 8. And carrying out a second single-sided probe test on the salient points on the front side of the TSV silicon transfer substrate.
And then removing the back carrier 16 shown in fig. 8 after debonding, so as to form the finished product of the TSV silicon interposer substrate shown in fig. 1.
In summary, the process of preparing the TSV silicon interposer substrate is as follows: (1) firstly, preparing TSV blind holes on a silicon substrate 1, then preparing a front metal wiring 3, and then preparing front salient points 7 to finish front process preparation of the TSV silicon transfer substrate; (2) temporarily bonding the TSV silicon interposer substrate subjected to the front-side process and the front-side carrier 14 together to perform a back-side process of the TSV silicon interposer substrate; (3) thinning the back of the TSV silicon transfer substrate to expose the bottom conductive material of the TSV blind holes so that the TSV blind holes are changed into TSV conductive through holes 2, and then sequentially performing back metal wiring 8 and back salient points 12 to finish back process preparation of the TSV silicon transfer substrate; (4) and separating the TSV silicon transfer substrate from the back slide 16 to complete the preparation of the TSV silicon transfer substrate.
The front bump under metal layer (UBM)6 or the back bump under metal layer (UBM)11 is usually prepared by a patterned electroplating method, that is, a whole front electroplating seed layer 5 under the front bump under metal layer (UBM) or a back electroplating seed layer 10 under the back bump under metal layer (UBM) is prepared by PVD, evaporation and sputtering methods, and then photoresist is coated thereon, and the pattern of the front bump under metal layer (UBM)6 or the back bump under metal layer (UBM)11 is exposed and developed, and then the front bump under metal layer (UBM)6 or the back bump under metal layer (UBM)11 with a certain thickness is electroplated; when the front bump 7 or the back bump 12 is an electroplating bump, the front bump 7 or the back bump 12 is directly electroplated after the front bump under-metal layer (UBM)6 or the back bump under-metal layer (UBM)11 is electroplated; and then etching the front electroplating seed layer 5 under the front Under Bump Metallurgy (UBM) or the back electroplating seed layer 10 under the back Under Bump Metallurgy (UBM) at other places, and separating the front Under Bump Metallurgy (UBM) patterns or separating the back Under Bump Metallurgy (UBM) patterns. When the front bump 7 or the back bump 12 is not an electroplating bump, or the front bump 7 or the back bump 12 is not needed on the front or the back of the TSV silicon interposer substrate, but only a pad is formed on the front under bump metal layer (UBM)6 or the back under bump metal layer (UBM)11 for subsequent use, the pad pattern on the front under bump metal layer (UBM)6 or the back under bump metal layer (UBM)11 needs to be subjected to surface treatment, such as nickel-palladium-gold plating or nickel-gold plating. In summary, no matter whether the front surface or the back surface of the TSV silicon interposer substrate needs the bump or the pad, the Under Bump Metallurgy (UBM) is needed, a whole layer of the plating seed layer under the Under Bump Metallurgy (UBM) is deposited on the whole area of the surface of the TSV silicon interposer substrate in the preparation process of the Under Bump Metallurgy (UBM), and finally the plating seed layer under the Under Bump Metallurgy (UBM) in the non-bump or non-pad region on the TSV silicon interposer substrate is etched.
Aiming at the ultra-thin TSV silicon transfer substrate wafer, particularly the TSV silicon transfer substrate wafer with the thickness less than 150 microns is thin, fragile and fragile, the risk of double-sided probe test is high, and the implementation is not easy. According to the invention, the wafer level electrical on-off probe test is combined with the preparation process flow of the TSV silicon switching substrate, and the TSV interconnection on-off test which can be completed only by the double-sided probe test is realized through two single-sided probe tests in the preparation process.
A method for testing the electrical connection and disconnection of a TSV silicon through connection substrate comprises the following specific implementation processes:
step 1: after the TSV silicon via substrate wafer is completed with the TSV blind holes, the front-side metal wiring 3, the front-side Under Bump Metallurgy (UBM)6 and the front-side bump 7, the front-side plating seed layer 5 under the front-side Under Bump Metallurgy (UBM) at other positions on the surface is not etched, but the complete front-side plating seed layer 5 under the front-side Under Bump Metallurgy (UBM) is retained, as shown in fig. 4.
Step 2: temporarily bonding the front surface of the TSV silicon switching substrate and the front surface carrier 14 together, thinning the back surface of the TSV silicon switching substrate, exposing the bottom conductive material of the TSV blind holes, sequentially performing back surface metal wiring 8 and back surface salient points 12, etching off a back surface electroplating seed layer 10 under a back surface salient point lower metal layer (UBM) at other places of the back surface, and completing the back surface process preparation of the TSV silicon switching substrate, as shown in figure 5. At this time, a first single-sided probe test is performed on the back bump 12 of the TSV silicon transfer substrate, and the electrical connection and disconnection relation between every two bumps of the back bump 12 is measured.
And step 3: temporarily bonding the back surface of the TSV silicon interposer substrate and the back surface carrier 16 together, de-bonding the front surface carrier 14 on the front surface of the TSV silicon interposer substrate, removing the front surface carrier 14 on the front surface of the TSV silicon interposer substrate, and cleaning to expose the front surface of the TSV silicon interposer substrate, as shown in fig. 7.
And 4, step 4: and etching the TSV silicon switch-over substrate front surface Under Bump Metal (UBM)6 and the front surface electroplating seed layer 5 under the front surface Under Bump Metal (UBM) in other regions except the front surface bump, as shown in figure 8. And carrying out a second single-sided probe test on the front side salient points 7 of the TSV silicon transfer substrate wafer, and measuring the connection relation between every two salient points of the front side salient points 7.
And 5: and synthesizing the two single-sided probe test results to obtain the test result of the electrical connection between the salient points on the upper surface and the lower surface of the TSV silicon switching substrate.
In the preparation process of the TSV silicon transfer substrate, the test and the process are combined, the electric disconnection relation between the front salient points 7 and the back salient points 12 of the TSV silicon transfer substrate is judged by measuring the electric disconnection connection relation between the back salient points 12 of the TSV silicon transfer substrate and the electric disconnection relation between the front salient points 7, two successive single-sided probe tests are used for replacing one double-sided probe test, and the problem of the electric disconnection test of the ultrathin double-sided substrate is solved.
When the two back bumps 12 are probed to measure the electrical continuity between the two back bumps, the front bumps are electrically connected in parallel. The electrical connection relationship between the front bump 7 and the back bump 12 on the TSV silicon interposer substrate is shown in fig. 2 and fig. 3, and can be regarded as a four-port network, and each four-port network determines the on-off relationship between four ports according to the on-off relationship between two ports. There are four cases: in the first case: one TSV via (and its front and back RDL layers and front and back bumps) is electrically isolated from the other TSV via (and its front and back RDL layers and front and back bumps), which is often found between signal, address and control line vias, between power and ground lines, and between signal, address, control and power and ground lines; in the second case: one TSV and the other TSV are electrically connected together in the front RDL layer, which is mostly the case when two or more front bumps on the TSV silicon switch-over substrate have the same pin definition and can be used for power and ground pins; in the third case: one TSV and the other TSV are electrically connected together in the back RDL layer, which is mostly the case when two or more back bumps on the TSV silicon transfer substrate have the same pin definition and can be used for power and ground pins; in a fourth case: one TSV via and another TSV via are electrically connected together in both the front RDL layer and the back RDL layer, which is often the case when two or more front bumps and two or more back bumps have the same pin definition, such as power and ground pins
In the above four cases, the electrical connection relationship between the two bumps at the two ends of the TSV through hole, and whether the electrical connection relationship between the two bumps can be directly detected in the two consecutive single-sided probe tests disclosed in the present invention, and the electrical connection relationship between the two bumps can be indirectly detected and indirectly determined according to the synthesis of the two consecutive single-sided probe test results, as shown in tables 1 to 4.
In the first case described above: the short circuit relation between the front side bumps A1 and B1 and the corresponding back side bumps A1 'and B1' can be directly detected by performing the first single-side probe test on the back side bumps of the TSV silicon transfer substrate, but the open circuit relation between the front side bumps A1, B1, A1 'and B1' cannot be detected, but the open circuit relation between the front side bumps A1, B1, A1 'and B1' can be judged by performing the second single-side probe test on the front side bumps of the TSV silicon transfer substrate wafer, so that the electrical connection and disconnection relation between the front side bumps A1, B1, A1 'and B1' under the first condition can be judged by combining the two single-side probe tests.
In the second case described above: the short circuit relationship between the front and back bumps a2, B2, a2 'and B2' cannot be judged by performing the first single-sided probe test on the back bump of the TSV silicon interposer substrate, but the short circuit relationship between the front and back bumps a2, B2, a2 'and B2' can be judged by performing the second single-sided probe test on the front bump of the TSV silicon interposer substrate wafer, so the electrical on-off relationship between the front and back bumps a2, B2, a2 'and B2' in the second case can be judged by combining the two single-sided probe tests.
In the third case described above: the first single-sided probe test of the back bump of the TSV silicon switching substrate can judge whether the short-circuit relation between the front bump A3 and B3 and the corresponding back bump A3 'and B3' is normal, although the short-circuit relation between the front bump A3, the back bump B3, the short-circuit relation between the A3 'and the back bump B3' cannot be judged, the judgment of the short-circuit relation between the front bump A3 and the back bump B3, the short-circuit relation between the A3 'and the short-circuit relation between the B3' and the back bump A3 are of reference significance; although the short-circuit relationship between the front bump A3 and the back bump B3 can not be determined by performing the second single-sided probe test on the front bump of the TSV silicon interposer substrate wafer, the short-circuit relationship between the front bump A3 and the back bump B3', between the front bump B3 and the back bump A3', and between the back bump A3 'and the back bump B3' are also meaningful for reference, and the short-circuit relationship between the front bump A3 and the back bump B3', between the front bump B3 and the back bump A3', and between the back bump A3 'and the back bump B3' can be indirectly determined by combining the results of the two probe tests. Therefore, the electrical connection and disconnection relationship between the bumps A3, B3, A3 'and B3' on the front side and the back side in the second case can be judged by combining the two single-sided probe tests.
In the fourth case described above: no matter the first single-sided probe test is performed on the back bump of the TSV silicon interposer substrate, or the second single-sided probe test is performed on the front bump of the TSV silicon interposer substrate, the short-circuit relationship between the front and back bumps a4, B4, a4 ', and B4' under the fourth condition cannot be determined exactly. However, since the front side bumps A4 and B4 are electrically connected together in the front side RDL layer, the back side bumps A4 'and B4' are electrically connected together in the back side RDL layer, the pin definitions of the front side bumps A4 and B4 are the same, and the pin definitions of the back side bumps A4 'and B4' are also the same, the front side bumps A4 and B4 can be regarded as the same point in the test network, and the back side bumps A4 'and B4' can also be regarded as the same point, and the four-port network (A4, B4, A4 ', B4') can be regarded as a two-port network (A4+ B4 and A4 '+ B4'), and the two-port network (A4+ B4, A4 '+ B4') can be reconfigured with other front side bumps and back side bumps on the silicon interposer substrate to determine the electrical disconnection relationship between A4+ B4 and A4 '+ B4'.
TABLE 1 electrically isolating two TSV vias (and their front and back RDL layers and front and back bumps)
TABLE 2 case of two TSV vias electrically connected through the front side RDL layer
TABLE 3 case of two TSV vias electrically connected through the backside RDL layer
TABLE 4 cases where two TSV vias are electrically connected through both the front RDL layer and the back RDL layer
Claims (9)
1. An electrical on-off test method of a double-sided substrate is characterized by comprising the following processes,
step 1, in the preparation process of the double-sided substrate, the front side electroplating seed layer (5) is not etched, and the front side electroplating seed layer (5) is reserved;
step 2, completing the back process of the double-sided substrate on the double-sided substrate with the front side electroplating seed layer (5) reserved, etching the back side electroplating seed layer (10), then carrying out a first single-side probe test on the back side salient points (12) of the double-sided substrate, and measuring the electric connection and disconnection relation between every two back side salient points (12);
step 3, etching the front electroplating seed layer (5) in the area except the front salient points (7), carrying out a second single-sided probe test on the front salient points (7) of the double-sided substrate, and measuring the electrical connection and disconnection relation between every two front salient points (7);
and 4, combining the first single-sided probe test result in the step 2 and the second single-sided probe test result in the step 3 to obtain an electrical connection test result between the salient points on the front surface and the back surface of the double-sided substrate.
2. The method for testing the electrical connection and disconnection of the double-sided substrate according to claim 1, wherein in the step 1, the blind holes, the front-side metal wiring (3), the front-side under bump metal layer (6) and the front-side bumps (7) are firstly prepared in the double-sided substrate preparation process, and then the complete electroplating seed layer (5) is reserved.
3. The double-sided substrate electrical on-off test method as claimed in claim 2, wherein the front metal wiring (3) is horizontally electrically connected to the front surface of the silicon substrate (1), when the front metal wiring (3) is multi-layered, the front metal wiring (3) of each layer is electrically insulated by the front metal interlayer dielectric (4), and the electrical connection between the front metal wiring (3) of each layer is realized by the connection hole between the layers.
4. The method for testing the electrical connection and disconnection of the double-sided substrate according to claim 1, wherein in the step 2, before the first single-sided probe test is carried out on the back bump (12), the front surface of the double-sided substrate and the front surface carrier (15) are temporarily bonded together, the back surface of the double-sided substrate is thinned, so that the blind hole forms the conductive through hole (2), then the back metal wiring (8) and the back bump (12) are sequentially carried out, and the electroplating seed layer (10) is etched, so that the back process of the double-sided substrate is completed.
5. The method for electrical connection and disconnection testing of a double-sided substrate as claimed in claim 4, wherein in step 3, the back surface of the double-sided substrate and the back surface carrier (16) are temporarily bonded together, the front surface carrier (15) is debonded, and the front surface carrier (15) is removed to expose the front surface of the double-sided substrate before the front surface bumps (7) are subjected to the second single-sided probe test.
6. The double-sided substrate electrical on-off test method as claimed in claim 4, wherein the back metal wiring (8) is arranged in a horizontal electrical connection on the back side of the silicon substrate (1), when the back metal wiring (8) is multi-layered, the back metal wiring (8) of each layer is electrically insulated by a back metal interlayer dielectric (9), and the electrical connection between the back metal wiring (8) of each layer is realized by a connection hole between each layer.
7. The method for testing the electrical continuity of a double-sided substrate according to claim 1, wherein the front under bump metallurgy (6) or the back under bump metallurgy (11) is prepared by patterned electroplating.
8. The method for electrically connecting and disconnecting a double-sided substrate as claimed in claim 1, wherein in the step 2, all the front-side bumps (7) are in a parallel short circuit relationship when the back-side bumps (12) are subjected to the first single-sided probe test.
9. The method of claim 1, wherein the double-sided substrate is a TSV silicon via substrate, a TGV glass via substrate or an organic substrate.
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