CN105140142A - Adapter plate process for sample testing electrical property of wafers - Google Patents
Adapter plate process for sample testing electrical property of wafers Download PDFInfo
- Publication number
- CN105140142A CN105140142A CN201510487385.3A CN201510487385A CN105140142A CN 105140142 A CN105140142 A CN 105140142A CN 201510487385 A CN201510487385 A CN 201510487385A CN 105140142 A CN105140142 A CN 105140142A
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- CN
- China
- Prior art keywords
- keyset
- electric connection
- connection point
- back side
- adapter plate
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The invention provides an adapter plate process for sample testing electrical property of wafers, comprising the following steps: manufacturing a needle clamp, setting probes on the needle clamp, manufacturing an adapter plate, setting front face electric connecting points on the front face of the adapter plate, setting TSV holes in the adapter plate through a TSV process, conducting the front face electric connecting points on the front face of the adapter plate to the back face; the front face electric connecting points on the front face of the adapter plate being mutually corresponding to the probes on the needle clamp; manufacturing a RDL re-wiring layer on the back face of the adapter plate, setting back face electric connecting points on the RDL re-wiring layer, each back face electric connecting point being in one-to-one correspondence with test points on to-be-tested wafers; bonding the surfaces of the to-be-tested wafers with the back face of the adapter plate through a temporary bonding process; choosing bonding adhesive with anisotropism conductive capacity and capable of conducting longitudinally and incapable of conducting transversely as the bonding adhesive, enabling the test points on the to-be-tested wafers to be in corresponding electric connection with the electric connecting points on the back face of the adapter plate; and inserting needles on the front face of the adapter plate. The adapter plate process can perform electrical performance test on the wafers with high-density test points.
Description
Technical field
The present invention relates to a kind of semiconductor assembly and test field, the keyset technique that especially a kind of fabrication is taken a sample test.
Background technology
Along with electronic product popularizing in human society, wafer manufacture and encapsulation more and more become very important industry.
But along with the more and more advanced person of wafer manufacturing process, the testing electrical property of wafer is counted and is also got more and more, more and more closeer, especially when technique reaches below 28nm, testing weld pad growing number in unit chip area is close, and develops for the pin card of testing electrical property the paces obviously can not having caught up with wafer development.This is mainly because when solder pad space length reaches the nm order of magnitude, and the pin on the pin card tested traditional cantilever type or rectilinear pin card have been difficult to implanted, or also can face electrical interference after implanting, or the problem that useful life is too short.
But the test of wafer is related to the integrity problem of follow-up packages and devices application, even if therefore difficulty of test strengthens, to take a sample test or necessary, so be badly in need of selecting a kind of technique can taking a sample test fabrication.
Chinese patent application CN200810086130.6 discloses a kind of crystal round test approach, it in essence or the probes touch pad of use pin card carries out wafer sort, this patent application is mainly for solving the micro dust particle pollution problem that may cause in test, but when the test point closeness on wafer is higher, some above-mentioned problems still can be faced.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide the keyset technique that a kind of fabrication is taken a sample test, can carry out testing electrical property to the wafer of high density test point, the technical solution used in the present invention is:
The keyset technique that fabrication is taken a sample test, comprises the steps:
Step S1, makes pin card, probe is established by pin card;
Step S2, makes a keyset, establishes front electric connection point, in keyset, establish TSV hole by TSV technique in the front of keyset, the front electric connection point of keyset is conducting to the back side of keyset; Front electric connection point on keyset is mutually corresponding with the probe on pin card;
Step S3, makes RDL wiring layer again at the keyset back side, and establish back side electric connection point on RDL again wiring layer, the test point one_to_one corresponding on each back side electric connection point and wafer to be measured; Meanwhile, back side electric connection point electrical connection corresponding with front electric connection point;
Step S4, provides bonding glue, crystal column surface to be measured and the keyset back side is bonded together by interim bonding technology; Described bonding glue is the bonding glue of longitudinally conduction and horizontal nonconducting anisotropic conductive ability, such that the test point on wafer to be measured is corresponding with the back side electric connection point on keyset to be electrically connected;
Step S5, by the front electric connection point of the probe alignment keyset on pin card, to the acupuncture treatment of keyset front, carries out the testing electrical property of wafer to be measured.
Further,
When the test point of crystal column surface to be measured is pad, the back side electric connection point of keyset is be arranged on the pad of RDL again on wiring layer to add the salient point that the pad of this RDL wiring layer is again established;
When the test point of crystal column surface to be measured is salient point, the back side electric connection point of keyset is be arranged on the pad of RDL again on wiring layer.
Further,
The front electric connection point of keyset is pad, salient point or soldered ball.
The invention has the advantages that: the present invention is by a kind of keyset technique of design, and this keyset is at frontal design electric connection point, and the density of this face electric connection point can match with existing pin card.Then by TSV technique, front electric connection point is conducting to the back side of wafer, last only needs to be rerouted technique by one deck RDL, produce with the corresponding back side electric connection point of the test point of wafer to be measured, by interim bonding, keyset is followed wafer bonding to be measured, make keyset back side electric connection point corresponding with wafer sort point, keyset front electric connection point is energized, gets final product the electrical of test wafer.。
Accompanying drawing explanation
Fig. 1 is pin card and wafer schematic diagram to be measured in prior art.
Fig. 2 keyset of the present invention makes front electric connection point and TSV hole schematic diagram.
Fig. 3 is that the keyset back side of the present invention makes RDL wiring layer and back side electric connection point schematic diagram again.
Fig. 4 is the interim bonding schematic diagram of keyset of the present invention and wafer to be measured.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
When the conductiving point of wafer to be measured is too intensive, traditional pin card just cannot be used to carry out wafer sort.As shown in Figure 1, wafer 1 surface to be measured have the very high conductiving point 101(of dense degree wherein a part need to carry out electrical testing, be test point 101 '), these conductiving points 101 can be pad or salient point; Pin card 2 is provided with probe 201, and traditional pin card can not plant so intensive probe 201, otherwise can face as in background technology the problem that runs into.
Embodiment one.
The present invention proposes the keyset technique that a kind of fabrication is taken a sample test, as described below, the testing electrical property of wafer high density test point can be carried out well.
Step S1, makes pin card 2, pin card 2 is established probe 201;
The dense degree of probe 201 is lower than the highly the densest degree allowed, and is advisable not cause the rear electrically interference of implantation.As shown in Figure 2.
Step S2, makes a keyset 3, establishes front electric connection point 301, in keyset 3, establish TSV hole 302 by TSV technique in the front of keyset 3, the front electric connection point 301 of keyset 3 is conducting to the back side of keyset 3; Front electric connection point 301 on keyset 3 is mutually corresponding with the probe 201 on pin card 2;
Front electric connection point 301 can be pad (pad), salient point or soldered ball.TSV hole and silicon through hole.
Step S3, makes RDL wiring layer 303 again at keyset 3 back side, and establish back side electric connection point 304 on RDL again wiring layer 303, each back side electric connection point 304 and the test point 101 ' one_to_one corresponding on wafer 1 to be measured; Meanwhile, back side electric connection point 304 and front electric connection point 301 are by the RDL corresponding electrical connection of wiring layer 303 again;
Specifically can carry out rewiring and definition pad at keyset 3 back side by newly-designed mask.
Because the test point 101 ' dense degree on wafer 1 to be measured is higher, the back side electric connection point 304 of keyset 3 is consistent with test point 101 ' dense degree, therefore higher than the closeness of front electric connection point 301, and also can higher than the closeness of probe 201.
In the present embodiment, conductiving point 101 and the test point 101 ' on wafer 1 surface to be measured are pad, in order to ensure the back side electric connection point 304 of keyset 3 and wafer 1 to be measured pad better corresponding be electrically connected and shorten connect distance, the back side electric connection point 304 of keyset 3 adds for being arranged on the pad of RDL again on wiring layer 303 salient point that the pad of this RDL wiring layer 303 is again established; This kind of situation as shown in Figure 3.
Step S4, provides bonding glue 4, is bonded together on wafer 1 surface to be measured by interim bonding technology with keyset 3 back side; The bonding glue that described bonding glue 4 is longitudinal conduction and horizontal nonconducting anisotropic conductive ability, such that the test point 101 ' on wafer 1 to be measured is corresponding with the back side electric connection point 304 on keyset 3 to be electrically connected; As shown in Figure 4.
In this example, namely the salient point of the RDL of pad and the keyset 3 on wafer 1 surface to be measured again on wiring layer 303 is electrically connected.Interim bonding technology uses glue can be the photoresistance with anisotropic conductive ability, and conducting resinl etc., can realize the longitudinal conductivity between corresponding pad or salient point and not affect adjacent conducting end.
Step S5, aims at the front electric connection point 301 of keyset 3 by the probe 201 on pin card 2, to the acupuncture treatment of keyset 3 front, carry out the testing electrical property of wafer to be measured.
After having tested, carry out tearing bonding technology open, and clean wafer 1 to be measured and keyset 3, keyset reuses after cleaning.
Embodiment two.
When the conductiving point 101 on wafer 1 surface to be measured and test point 101 ' are for salient point, the back side electric connection point 304 of keyset 3 is for being arranged on the pad of RDL again on wiring layer 303.
Other is with embodiment one.
Claims (3)
1. the keyset technique taken a sample test of fabrication, is characterized in that, comprise the steps:
Step S1, makes pin card (2), pin card (2) is established probe (201);
Step S2, make a keyset (3), front electric connection point (301) is established in the front of keyset (3), in keyset (3), establish TSV hole (302) by TSV technique, the front electric connection point (301) of keyset (3) is conducting to the back side of keyset (3); Front electric connection point (301) on keyset (3) is mutually corresponding with the probe (201) on pin card (2);
Step S3, RDL wiring layer (303) is again made at keyset (3) back side, and on RDL again wiring layer (303), establish back side electric connection point (304), each back side electric connection point (304) and test point (101 ') one_to_one corresponding on wafer to be measured (1); Meanwhile, back side electric connection point (304) and front electric connection point (301) corresponding electrical connection;
Step S4, provides bonding glue (4), is bonded together on wafer to be measured (1) surface by interim bonding technology with keyset (3) back side; The bonding glue that described bonding glue (4) is longitudinal conduction and horizontal nonconducting anisotropic conductive ability, such that the test point (101 ') on wafer to be measured (1) is corresponding with the back side electric connection point (304) on keyset (3) to be electrically connected;
Step S5, probe (201) on pin card (2) is aimed at the front electric connection point (301) of keyset (3), to the acupuncture treatment of keyset (3) front, carry out the testing electrical property of wafer to be measured (1).
2. the keyset technique taken a sample test of fabrication as claimed in claim 1, is characterized in that:
When the test point (101 ') on wafer to be measured (1) surface is for pad, the back side electric connection point (304) of keyset (3) adds for being arranged on the pad of RDL again on wiring layer (303) salient point that the pad of this RDL wiring layer (303) is again established;
When the test point (101 ') on wafer to be measured (1) surface is for salient point, the back side electric connection point (304) of keyset (3) is for being arranged on the pad of RDL again on wiring layer (303).
3. the keyset technique taken a sample test of fabrication as claimed in claim 1, is characterized in that:
The front electric connection point (301) of keyset (3) is pad, salient point or soldered ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510487385.3A CN105140142A (en) | 2015-08-10 | 2015-08-10 | Adapter plate process for sample testing electrical property of wafers |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510487385.3A CN105140142A (en) | 2015-08-10 | 2015-08-10 | Adapter plate process for sample testing electrical property of wafers |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109581173A (en) * | 2018-11-30 | 2019-04-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of TSV switching board test device and method based on micro-nano mitron array |
| CN110010511A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of test mode of radio frequency chip system in package mould group |
| CN111293109A (en) * | 2020-02-25 | 2020-06-16 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
| CN112509937A (en) * | 2020-11-30 | 2021-03-16 | 西安微电子技术研究所 | Electric on-off test method for double-sided substrate |
| CN113471103A (en) * | 2021-06-09 | 2021-10-01 | 上海华虹宏力半导体制造有限公司 | Probe module |
| CN114137383A (en) * | 2022-02-08 | 2022-03-04 | 广东科翔电子科技股份有限公司 | High-precision Mini-LED board electric measurement method |
| CN116718891A (en) * | 2023-06-06 | 2023-09-08 | 无锡芯光互连技术研究院有限公司 | Test method of adapter plate and structure for testing adapter plate |
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| US20130099812A1 (en) * | 2011-10-21 | 2013-04-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Probe Cards for Probing Integrated Circuits |
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| CN103399225A (en) * | 2013-07-26 | 2013-11-20 | 华进半导体封装先导技术研发中心有限公司 | Test structure containing transferring plate |
| CN103926430A (en) * | 2014-04-23 | 2014-07-16 | 华进半导体封装先导技术研发中心有限公司 | Through-silicon via patch board testing method |
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| CN102012470A (en) * | 2009-09-04 | 2011-04-13 | 日月光半导体（上海）股份有限公司 | Electrical test adapter plate of sealing base plate and method thereof |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110010511A (en) * | 2018-10-10 | 2019-07-12 | 浙江集迈科微电子有限公司 | A kind of test mode of radio frequency chip system in package mould group |
| CN110010511B (en) * | 2018-10-10 | 2023-11-17 | 浙江集迈科微电子有限公司 | Test mode of radio frequency chip system-in-package module |
| CN109581173A (en) * | 2018-11-30 | 2019-04-05 | 华进半导体封装先导技术研发中心有限公司 | A kind of TSV switching board test device and method based on micro-nano mitron array |
| CN111293109A (en) * | 2020-02-25 | 2020-06-16 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
| WO2021168953A1 (en) * | 2020-02-25 | 2021-09-02 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method therefor |
| CN111293109B (en) * | 2020-02-25 | 2021-11-23 | 武汉新芯集成电路制造有限公司 | Bonding structure and manufacturing method thereof |
| CN112509937A (en) * | 2020-11-30 | 2021-03-16 | 西安微电子技术研究所 | Electric on-off test method for double-sided substrate |
| CN112509937B (en) * | 2020-11-30 | 2023-06-30 | 珠海天成先进半导体科技有限公司 | Electric on-off test method for double-sided substrate |
| CN113471103A (en) * | 2021-06-09 | 2021-10-01 | 上海华虹宏力半导体制造有限公司 | Probe module |
| CN113471103B (en) * | 2021-06-09 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Probe module |
| CN114137383A (en) * | 2022-02-08 | 2022-03-04 | 广东科翔电子科技股份有限公司 | High-precision Mini-LED board electric measurement method |
| CN116718891A (en) * | 2023-06-06 | 2023-09-08 | 无锡芯光互连技术研究院有限公司 | Test method of adapter plate and structure for testing adapter plate |
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Application publication date: 20151209 |
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| RJ01 | Rejection of invention patent application after publication |