CN112505410A - PWM control sequential sampling period transient frequency measuring circuit - Google Patents
PWM control sequential sampling period transient frequency measuring circuit Download PDFInfo
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Abstract
A PWM control time sequence sampling period transient frequency measuring circuit adopts DDS technology to carry out frequency division processing on a reference time sequence, thereby obtaining a standard sampling time period signal; the DDS technology is adopted to carry out frequency division processing on the PWM control time sequence, and on the premise of ensuring the frequency stability of the original PWM control time sequence to be unchanged, on one hand, the frequency of the PWM control time sequence is reduced through the digital frequency division technology, and the purpose of widening the frequency range of the PWM control time sequence is met; on the other hand, after digital frequency division processing, a measured clock signal with very accurate frequency can be obtained; introducing a measuring module, and judging the optimal phase difference of the PWM control time sequence and the reference time sequence at the moment according to the inherent minimum resolution measuring range of the measuring module when the edge of the periodic sampling clock signal comes, so that the corresponding counter can work; the measurement of the transient frequency in the sampling period of the PWM control time sequence can be completed, and the measurement precision can be improved according to the requirement.
Description
Technical Field
The invention belongs to the technical field of transient frequency in a PWM sampling period, and particularly relates to a PWM control timing sequence sampling period transient frequency measuring circuit.
Background
The stepping motor is also called as a pulse motor, works based on the most basic electromagnet principle, is an electromagnet capable of freely rotating, and the action principle of the stepping motor is that electromagnetic torque is generated by means of the change of air gap permeance, and the original model of the stepping motor originates from 1830 to 1860 years; attempts to apply this to the electrode feed mechanism of the hydrogen arc lamp for control purposes started around 1870, which is considered to be the first stepper motor. In the early twentieth century, stepping motors were widely used in automatic telephone exchanges. Due to the strong competition of western capitalization for colonists, stepper motors are widely used in independent systems such as ships and airplanes which lack ac power. In the late fifties of the twentieth century, the invention of the transistor was gradually applied to the stepping motor, and the digital control became easier. After the eighties, the control modes of the stepping motor are more flexible and diversified due to the fact that the low-cost microcomputer appears in a multifunctional posture.
The biggest difference of the stepping motor relative to other control motors is that the stepping motor receives a digital control signal (an electric pulse signal) and converts the digital control signal into an angular displacement or a linear displacement corresponding to the digital control signal, and the stepping motor is an execution element for completing digital mode conversion. With the development of electronic technology, various Pulse Width Modulation (PWM) techniques have appeared, including: the pulse width PWM method is characterized in that pulse trains with equal pulse width are used as PWM waveforms, frequency modulation can be realized by changing the period of the pulse trains, voltage regulation can be realized by changing the width or duty ratio of the pulses, and the voltage and frequency coordinated change can be realized by adopting a proper control method, so that the aim of controlling the charging current can be achieved by adjusting the period of the PWM and the duty ratio of the PWM.
The value of the analog signal may be continuously varied with no limitation in time and amplitude resolution. A 9V cell is an analog device because its output voltage is not exactly 9V, but varies over time and can take any real value. Similarly, the current drawn from the battery is not limited to a set of possible values. Analog signals differ from digital signals in that the values of the latter can usually only fall within a predetermined set of possible values, for example in the set 0V, 5V.
The analog voltage and the analog current can be directly used to control parameters, such as the volume of a car radio. In a simple analog radio, the volume knob is connected to a variable resistor. When the knob is turned, the resistance value becomes larger or smaller, and the current flowing through the resistance value is increased or reduced, so that the current value for driving the loudspeaker is changed, and the volume is correspondingly increased or reduced. Like a radio, the output of an analog circuit scales linearly with the input.
While analog control may seem intuitive and simple, it is not always very economical or feasible. One such point is that the analog circuitry tends to drift over time and is therefore difficult to adjust, and the precision analog circuitry that can solve this problem can be very large, bulky (e.g. older home stereo equipment) and expensive. Analog circuits may also generate significant heat, the power consumption of which is proportional to the product of the voltage and current across the active element. Analog circuits may also be sensitive to noise, and any disturbance or noise may change the magnitude of the current value.
The cost and power consumption of the system can be greatly reduced by controlling the analog circuits in a digital manner. In addition, many microcontrollers and DSPs already contain PWM controllers on chip, which makes the implementation of digital control easier.
The Pulse Width Modulation (PWM) control method is to control the on/off of the switching device of the inverter circuit, so that a series of pulses with equal amplitude are obtained at the output end, and these pulses are used to replace sine waves or required waveforms. That is, a plurality of pulses are generated in a half cycle of an output waveform, and the equivalent voltage of each pulse is a sine waveform, so that the obtained output is smooth and has few low-order harmonics. The width of each pulse is modulated according to a certain rule, so that the magnitude of the output voltage of the inverter circuit can be changed, and the output frequency can also be changed.
In certain situations, the transient frequency within the PWM sampling period of the control stepper motor needs to be measured, and therefore a corresponding measurement circuit is required.
Disclosure of Invention
In view of the above, the present invention provides a PWM control timing sampling period transient frequency measurement circuit that overcomes, or at least partially solves, the above problems.
In order to solve the above technical problem, the present invention provides a PWM control timing sampling period transient frequency measurement circuit, which includes: the device comprises a first isolation amplifier, a first DDS frequency dividing unit, a measuring module, a second DDS frequency dividing unit, a second isolation amplifier, a travel time counting unit, a latch unit, a processor and a PC, wherein the first isolation amplifier is respectively connected with the first DDS frequency dividing unit, the measuring module and the travel time counting unit, the first DDS frequency dividing unit is connected with the processor, the measuring module is respectively connected with the second isolation amplifier and the processor, the second DDS frequency dividing unit is connected with the second isolation amplifier, the second isolation amplifier is connected with the travel time counting unit, the travel time counting unit is respectively connected with the latch unit and the processor, the latch unit is connected with the processor, the processor is connected with the PC, and the first isolation amplifier receives a reference timing signal, and the second DDS frequency division unit receives a PWM control timing signal, and the PC receives a software parameter setting signal and outputs a measurement result output signal.
Preferably, the measurement module comprises: and the input end of the FPGA module is respectively connected with the first isolation amplifier and the second isolation amplifier, and the output end of the FPGA module is connected with the processor.
Preferably, the FPGA module includes: the data preprocessor comprises an NOT gate, a coarse value counter, a dynamic memory and a data preprocessor, wherein the input end of the NOT gate is connected with the first isolation amplifier, the output end of the NOT gate is respectively connected with the coarse value counter and the dynamic memory, the coarse value counter is connected with the dynamic memory, the dynamic memory is respectively connected with the first isolation amplifier and the second isolation amplifier, and the data preprocessor is respectively connected with the dynamic memory and the processor.
Preferably, the output end of the first isolation amplifier is connected to the external clock input end of the first DDS frequency dividing unit.
Preferably, an external communication port of the first DDS frequency dividing unit is connected to an input end of the processor.
Preferably, a 48-bit frequency control register is arranged inside the first DDS frequency dividing unit.
Preferably, the expression of the frequency division value of the frequency control register is:
wherein D is the frequency division value, f is the frequency of the sampling time signal to be frequency-divided, and f0 is the reference timing frequency.
Preferably, the processor is connected with the PC through an RS232 serial interface.
Preferably, the timing unit includes a second timing counter, and the latch unit includes a second latch, wherein the second timing counter is connected to the second isolation amplifier and the processor, respectively, and the second latch is connected to the second timing counter and the processor, respectively.
Preferably, the timing unit includes a third timing counter, and the latch unit includes a third latch, wherein the third timing counter is connected to the first isolation amplifier and the processor, respectively, and the third latch is connected to the third timing counter and the processor, respectively.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: according to the PWM control time sequence sampling period transient frequency measuring circuit, a DDS technology is adopted to carry out frequency division processing on a reference time sequence, so that a standard sampling time period signal is obtained; the DDS technology is adopted to carry out frequency division processing on the PWM control time sequence, and on the premise of ensuring the frequency stability of the original PWM control time sequence to be unchanged, on one hand, the frequency of the PWM control time sequence is reduced through the digital frequency division technology, and the purpose of widening the frequency range of the PWM control time sequence is met; on the other hand, after digital frequency division processing, a measured clock signal with very accurate frequency can be obtained; introducing a measuring module, and judging the optimal phase difference of the PWM control time sequence and the reference time sequence at the moment according to the inherent minimum resolution measuring range of the measuring module when the edge of the periodic sampling clock signal comes, so that the corresponding counter can work; the measurement of the transient frequency in the sampling period of the PWM control time sequence can be completed, and the measurement precision can be improved according to the requirement.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a timing diagram of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention
FIG. 3 is a schematic diagram of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a portion of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention;
fig. 5 is a schematic signal transmission diagram of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a portion of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a part of a PWM control timing sampling period transient frequency measurement circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments and examples, and the advantages and various effects of the present invention will be more clearly apparent therefrom. It will be understood by those skilled in the art that these specific embodiments and examples are for the purpose of illustrating the invention and are not to be construed as limiting the invention.
Throughout the specification, unless otherwise specifically noted, terms used herein should be understood as having meanings as commonly used in the art. Accordingly, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. If there is a conflict, the present specification will control.
Unless otherwise specifically stated, various raw materials, reagents, instruments, equipment and the like used in the present invention are commercially available or can be prepared by existing methods.
Referring to fig. 1-7, in the embodiment of the present application, the present invention provides a PWM control timing sampling period transient frequency measurement circuit, including: the device comprises a first isolation amplifier, a first DDS frequency dividing unit, a measuring module, a second DDS frequency dividing unit, a second isolation amplifier, a travel time counting unit, a latch unit, a processor and a PC, wherein the first isolation amplifier is respectively connected with the first DDS frequency dividing unit, the measuring module and the travel time counting unit, the first DDS frequency dividing unit is connected with the processor, the measuring module is respectively connected with the second isolation amplifier and the processor, the second DDS frequency dividing unit is connected with the second isolation amplifier, the second isolation amplifier is connected with the travel time counting unit, the travel time counting unit is respectively connected with the latch unit and the processor, the latch unit is connected with the processor, the processor is connected with the PC, and the first isolation amplifier receives a reference timing signal, and the second DDS frequency division unit receives a PWM control timing signal, and the PC receives a software parameter setting signal and outputs a measurement result output signal.
As shown in fig. 1, in the embodiment of the present application, when the sampling period signal (with a width of T) is in the high level period, the first pulse of the PWM control timing is a rising pulse, the enable terminal of the counter is enabled, and the reference timing and the PWM control timing are counted respectively. Here, the time width of the enable signal (actual gate signal) is exactly equal to the complete cycle number of the PWM control timing, which is the key to ensure that the PWM control timing can maintain constant accuracy under any frequency condition.
In the embodiment of the present application, as shown in fig. 2, a more precise measurement means is provided in the upper diagram in the practical implementation, because the PWM control timing and the reference time base timing are triggered at exactly the same time during the practical sampling process, which puts a high demand on the counting statistic module, and this is solved: when the trigger edge pulse of the sampling period comes, the rising pulse of the next PWM control time sequence is waited, and the corresponding counter is enabled to carry out the operations of 'starting counting' and 'finishing counting' at the moment. It can be seen from the figure that there are time differences Δ t1, Δ t2 between the enabling counter time points a and B and the next edge pulse of the reference timing signal, the magnitude of the specific difference depends on the time difference between the PWM control timing and the reference timing signal at time a or time B, and the magnitude of the specific difference is not a constant fixed time difference relationship, which may cause different errors in each sampling, which is also the reason for improving the counting accuracy. For the method that a high-stability and high-frequency clock frequency source is needed to be adopted in a practical system to further improve the measurement, the time differences delta t1 and delta t2 are reduced to the minimum value or even 0 so as to improve the measurement accuracy.
Referring to fig. 3, in the embodiment of the present application, the reference timing generally uses a 10MHz clock signal as a standard reference input, and the frequency output of the reference source signal can be regarded as a relatively stable clock source, and a standard sampling time period signal can be obtained by performing a digital synthesis frequency division technique on the stable reference source clock signal. Regarding the PWM control time sequence, people pay attention to the frequency range of the PWM control time sequence in the frequency stability measuring link, in order to widen the application range of the whole measuring device and meet the requirement of high-frequency signal measurement, on the premise of ensuring that the inherent stability of the PWM control time sequence source is not influenced, the invention introduces the prior mature DDS chip and technology, and the phase of continuous signals is sampled from the Nyquist sampling
Starting with sampling, quantizing, encoding the signal to form a positiveChord function tables, present in EPROM.
During synthesis, the phase increment is changed by changing the frequency control word of the phase accumulator, and the difference of the phase increment causes the difference of the number of sampling points in one week. Frequency of angle of incidence
Under the condition of unchanging sampling frequency, the frequency control word of the phase accumulator is changed, the changed phase/amplitude is quantized into a digital signal, and a comprehensive signal required by people can be obtained through D/A conversion and a low-pass filter.
Because of the good input and output signal-to-noise ratio, after the PWM control time sequence is processed by the second DDS frequency division unit, a signal with the same stability as the original PWM control time sequence and lower frequency can be obtained. In the scheme, the original PWM control time sequence frequency division of higher frequency is converted into the PWM control time sequence of lower frequency, and the function of a PLL frequency multiplication module in the second DDS frequency division unit is not adopted, so that better signal-to-noise ratio output can be obtained at the output end of the second DDS frequency division unit. And for the tested frequency signals (such as 10.123456789MHz) with low accuracy, a very precise periodic signal (such as 1.000000000MHz) can be obtained after frequency division by the second DDS frequency division unit.
In order to improve the precision of the whole measurement, the invention introduces a measurement module, when a periodic sampling signal starts/ends and a PWM control time sequence and a reference time sequence start/end are counted, the phase relation of two paths of signals is firstly judged, so that the rising edges of the next PWM control time sequence after the periodic sampling signal arrives and the reference time sequence are superposed as much as possible, and when the time difference of the rising edges of two pulses is ns magnitude, the traditional pulse counting method for measuring the pulse width is not applicable any more. This is because the narrower the pulse to be measured, the higher the required clock frequency and the higher the performance requirements of the chip.
In an embodiment of the present application, the measurement module includes: and the input end of the FPGA module is respectively connected with the first isolation amplifier and the second isolation amplifier, and the output end of the FPGA module is connected with the processor. The FPGA module built-in gate circuit of the invention provides a new time interval measuring method by using the absolute transmission time of signals passing through the logic gate circuit, and the measuring principle is shown in figure 4. The time interval between the START signal and the STOP signal is determined by the number of not-gates, and the transmission time of the not-gates can be accurately determined by the integrated circuit process. The FPGA module comprises: the data preprocessor comprises an NOT gate, a coarse value counter, a dynamic memory and a data preprocessor, wherein the input end of the NOT gate is connected with the first isolation amplifier, the output end of the NOT gate is respectively connected with the coarse value counter and the dynamic memory, the coarse value counter is connected with the dynamic memory, the dynamic memory is respectively connected with the first isolation amplifier and the second isolation amplifier, and the data preprocessor is respectively connected with the dynamic memory and the processor.
In the selected FPGA module, whether the specific time difference value of a group of reference time Sequence (START) rising edges and PWM control time Sequence (STOP) rising edges at the moment reaches the minimum resolution range or not is judged through the FPGA module, namely the reference time sequence and the PWM control time sequence have the minimum phase difference at the moment, so that a corresponding counter can work through a processor, and finally the counter reading of the PWM control time sequence and the reference time sequence in the whole sampling period range is accurate as much as possible, and the precision of the whole frequency stability measurement is improved.
Referring to fig. 5, in the embodiment of the present application, the reference frequency signal f0 is sent to the external clock input terminal of the first DDS frequency dividing unit after passing through the first isolation amplifier, and is used as the external reference clock for the first DDS frequency dividing unit, and the external communication port of the first DDS frequency dividing unit is connected to the processor for receiving the control word command and the bidirectional data transmission from the processor. Actually, 2 48-bit frequency control registers (F0, F1) are arranged in a first DDS frequency dividing unit chip, a reference frequency signal F0 of the circuit is 10MHz, when the PLL frequency doubling function in the first DDS frequency dividing unit is not used, and 1 is fully filled in the 48-bit frequency control register F0, the first DDS frequency dividing unit outputs a 10MHz frequency signal, so that in order to obtain a standard sampling time period signal T (e.g., 1 second, 10 seconds), a corresponding frequency dividing value needs to be set for the frequency control register F0 in the first DDS frequency dividing unit, and a specific calculation formula is as follows:
wherein D is the frequency division value, f is the frequency of the sampling time signal required to be divided, f0 is the reference time sequence frequency, and f0 in the circuit is 10 MHz. For f of 1Hz (1 second) and 0.1Hz (10 seconds), the division value D should be 248X 10-7 or 248X 10-8. The specific sampling time T is set by a user through PC end software according to the requirement in the actual sampling process, and the frequency division value is calculated by applying the formula after the sampling time T set by the user is obtained by the processor through the communication between the RS232 serial interface and the PC end. And the processor writes a frequency division value D into a corresponding buffer of the first DDS frequency division unit according to the serial communication time sequence corresponding to the first DDS frequency division unit to obtain a final sampling time signal T output of the first DDS frequency division unit.
Referring to fig. 6, in the embodiment of the present application, the frequency signal fx to be measured is sent to two DDS frequency dividing units respectively after passing through the third isolation amplifier. When the PWM control timing frequency is hundreds of mega even hundreds of mega hertz, the second DDS frequency dividing unit is designed to divide the frequency signal to be measured by 1/100 frequency division in the present invention, considering the limitation of the travel time counter to the range of the frequency to be measured. And the PWM control time sequence is directly sent to the external clock input end of the second DDS frequency division unit after passing through the third isolation amplifier and is used as a reference clock when the second DDS frequency division unit works. An external communication port of the second DDS frequency division unit is connected to the processor, 248 multiplied by 10 < -2 > frequency division values obtained by the processor according to the formula are written into a buffer area of the second DDS frequency division unit through a serial communication time sequence, 1/100 frequency division rate signals obtained by the second DDS frequency division unit are sent to the first travel time counter for coarse frequency measurement, the processor reads a value sampled by the first travel time counter by the first latch, records the frequency value at the moment, and the frequency value is multiplied by 100 to obtain a coarse frequency value F of the PWM control time sequence.
The other path is sent to a third DDS frequency division unit through the PWM control time sequence of a third isolation amplifierAnd the external clock input end is used as a reference clock when the third DDS frequency division unit works. Meanwhile, an external communication port of the third DDS frequency division unit is connected to the processor, and the processor calculates a frequency division value for communication with the third DDS frequency division unit according to the formula (1):
f is a coarse frequency value of a PWM control time sequence obtained through counting of the first travel time counter and operation of the processor, 1MHz is taken as F, the obtained specific frequency division value is written into a third DDS frequency division unit cache region through the serial communication time sequence, a 1MHz frequency signal is obtained through the third DDS frequency division unit, and the obtained frequency signal is sent to the low-pass filtering module to obtain a final 1MHz frequency signal to be output.
As shown in fig. 1 to 7, in the embodiment of the present application, the timing unit includes a second timing counter, and the latch unit includes a second latch, wherein the second timing counter is connected to the second isolation amplifier and the processor, respectively, and the second latch is connected to the second timing counter and the processor, respectively.
As shown in fig. 1 to 7, in the embodiment of the present application, the timing unit includes a third timing counter, and the latch unit includes a third latch, wherein the third timing counter is connected to the first isolation amplifier and the processor, respectively, and the third latch is connected to the third timing counter and the processor, respectively.
As shown in fig. 7, in the embodiment of the present application, a 1MHz frequency signal obtained by processing a frequency signal to be measured by a second DDS frequency dividing unit and a 10MHz reference time sequence are respectively sent to a precise time interval measuring module, specifically to a STOP and START pin terminal of a corresponding time processing chip. The processor enables the precise time interval module to carry out phase measurement on two paths of STOP and START frequency signals according to a rising edge of a sampling time signal T obtained by processing a reference time sequence by the first DDS frequency division unit, transmits a measurement result to the processor for processing, and judges a group of STOP and START frequency according to a minimum resolution measurement range of the precise time interval measurement moduleWhether the rising edge of the rate signal reaches the minimum time difference, i.e., the time difference Δ t1, Δ t2 between the PWM control timing and the reference timing in fig. 7 is minimum, then the processor stops the measurement operation of the fine time interval module and enables the first and second travel time counters to start the counting operation. When the processor detects that the falling edge of the sampling time signal T arrives, the precise time interval measuring module is enabled again to carry out phase measurement on two paths of STOP and START frequency signals, when the time difference delta T1 and delta T2 of the two paths of signals at the moment is judged to be minimum, the processor STOPs the measuring work of the precise time interval measuring module, enables the second latch and the third latch to respectively latch the count values of the second travel time counter and the third travel time counter, and enables a new round of sampling counting after the second travel time counter and the third travel time counter are cleared through the processor. In a complete sampling period T, reading values N1 and N2 of the second travel time counter and the third travel time counter stored by the second latch and the third latch are transmitted to the processor, the processor transmits measurement results N1 and N2 to the PC terminal through an RS232 serial interface, and the PC terminal software calculates to obtain corresponding PWM control time sequence real-time frequency values y1 and y2 … … yi (i is 1, 2 and 3 … … N-1, and N is a positive integer). And simultaneously, a measurement result and a real-time PWM control time sequence measurement curve are displayed on a screen by utilizing a Visual Basic programming environment and a DirectX graphic processing technology at a PC terminal. The calculation result of the PWM control time sequence frequency stability is obtained according to the alendron variance or the Hadamard variance. When the measured real-time frequency value is used to calculate the frequency stability specifically based on the alendron variance or hadamard variance, the result needs to be divided by the average value of the real-time frequency of the PWM control timing sequence
The calculation method of (2) is to take the frequency value of the PWM control timing within n sampling periods T as an addition average.
According to the PWM control time sequence sampling period transient frequency measuring circuit, a DDS technology is adopted to carry out frequency division processing on a reference time sequence, so that a standard sampling time period signal is obtained; the DDS technology is adopted to carry out frequency division processing on the PWM control time sequence, and on the premise of ensuring the frequency stability of the original PWM control time sequence to be unchanged, on one hand, the frequency of the PWM control time sequence is reduced through the digital frequency division technology, and the purpose of widening the frequency range of the PWM control time sequence is met; on the other hand, after digital frequency division processing, a measured clock signal with very accurate frequency can be obtained; introducing a measuring module, and judging the optimal phase difference of the PWM control time sequence and the reference time sequence at the moment according to the inherent minimum resolution measuring range of the measuring module when the edge of the periodic sampling clock signal comes, so that the corresponding counter can work; the measurement of the transient frequency in the sampling period of the PWM control time sequence can be completed, and the measurement precision can be improved according to the requirement.
Finally, it should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "first" and "second" in this application are to be understood as terms.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A PWM controlled timing sample period transient frequency measurement circuit, the circuit comprising: the device comprises a first isolation amplifier, a first DDS frequency dividing unit, a measuring module, a second DDS frequency dividing unit, a second isolation amplifier, a travel time counting unit, a latch unit, a processor and a PC, wherein the first isolation amplifier is respectively connected with the first DDS frequency dividing unit, the measuring module and the travel time counting unit, the first DDS frequency dividing unit is connected with the processor, the measuring module is respectively connected with the second isolation amplifier and the processor, the second DDS frequency dividing unit is connected with the second isolation amplifier, the second isolation amplifier is connected with the travel time counting unit, the travel time counting unit is respectively connected with the latch unit and the processor, the latch unit is connected with the processor, the processor is connected with the PC, and the first isolation amplifier receives a reference timing signal, and the second DDS frequency division unit receives a PWM control timing signal, and the PC receives a software parameter setting signal and outputs a measurement result output signal.
2. The PWM control timing sampling period transient frequency measurement circuit according to claim 1, wherein the measurement module comprises: and the input end of the FPGA module is respectively connected with the first isolation amplifier and the second isolation amplifier, and the output end of the FPGA module is connected with the processor.
3. The PWM control timing sampling period transient frequency measurement circuit according to claim 2, wherein the FPGA module comprises: the data preprocessor comprises an NOT gate, a coarse value counter, a dynamic memory and a data preprocessor, wherein the input end of the NOT gate is connected with the first isolation amplifier, the output end of the NOT gate is respectively connected with the coarse value counter and the dynamic memory, the coarse value counter is connected with the dynamic memory, the dynamic memory is respectively connected with the first isolation amplifier and the second isolation amplifier, and the data preprocessor is respectively connected with the dynamic memory and the processor.
4. The PWM controlled timing sampling period transient frequency measurement circuit according to claim 1, wherein the output terminal of the first isolation amplifier is connected to the external clock input terminal of the first DDS frequency dividing unit.
5. The PWM control timing sampling period transient frequency measurement circuit according to claim 1, wherein an external communication port of the first DDS frequency dividing unit is connected to an input of the processor.
6. The PWM control timing sampling period transient frequency measurement circuit according to claim 1, wherein a 48-bit frequency control register is disposed inside the first DDS frequency dividing unit.
7. The PWM control timing sampling period transient frequency measurement circuit according to claim 6, wherein the frequency division value of the frequency control register is expressed by:
wherein D is the frequency division value, f is the frequency of the sampling time signal to be frequency-divided, and f0 is the reference timing frequency.
8. The PWM control timing sampling period transient frequency measurement circuit according to claim 1, wherein said processor is connected to said PC via an RS232 serial interface.
9. The PWM-controlled timing sampling period transient frequency measurement circuit according to claim 1, wherein the timing counter unit comprises a second timing counter, and the latch unit comprises a second latch, wherein the second timing counter is connected to the second isolation amplifier and the processor, respectively, and the second latch is connected to the second timing counter and the processor, respectively.
10. The PWM-controlled timing sampling period transient frequency measurement circuit according to claim 1, wherein the timing counter unit comprises a third timing counter, and the latch unit comprises a third latch, wherein the third timing counter is connected to the first isolation amplifier and the processor, respectively, and the third latch is connected to the third timing counter and the processor, respectively.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023036090A1 (en) * | 2021-09-13 | 2023-03-16 | 北京车和家信息技术有限公司 | Pulse width modulation signal acquisition method and apparatus, computer device, and storage medium |
| CN117634385A (en) * | 2022-08-24 | 2024-03-01 | 上海合见工业软件集团有限公司 | Method, system and storage medium for simulating IC design on FPGA |
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023036090A1 (en) * | 2021-09-13 | 2023-03-16 | 北京车和家信息技术有限公司 | Pulse width modulation signal acquisition method and apparatus, computer device, and storage medium |
| CN117634385A (en) * | 2022-08-24 | 2024-03-01 | 上海合见工业软件集团有限公司 | Method, system and storage medium for simulating IC design on FPGA |
| CN117634385B (en) * | 2022-08-24 | 2024-06-21 | 上海合见工业软件集团有限公司 | Method, system and storage medium for simulating IC design on FPGA |
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