CN112492404B

CN112492404B - Multiplexing interface device and MAC system

Info

Publication number: CN112492404B
Application number: CN202011301949.7A
Authority: CN
Inventors: 张贞雷; 刘同强; 周玉龙; 王贤坤
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2023-05-23
Anticipated expiration: 2040-11-19
Also published as: CN112492404A

Abstract

The invention discloses a multiplexing interface device and a MAC system, which comprises a first interface controller, an interface conversion module, an output interface selector and a clock generation module. The multiplexing interface device can simultaneously provide different types of PHY interfaces, and select corresponding interface output according to the interface type adapted to the PHY connected currently, so that the flexibility of MAC is improved and the burden of a user is reduced; meanwhile, the clock generating module can complete clock conversion of different interfaces, so that the burden of a user and the complexity of actual use are further reduced.

Description

Multiplexing interface device and MAC system

Technical Field

The present invention relates to the field of communication interfaces, and in particular, to a multiplexing interface device and a MAC system.

Background

As shown in fig. 1, the conventional data interaction manner between the MAC (ethernet media connection controller) and the PHY (physical interface transceiver) is that the MAC only outputs one interface for communication with the PHY, such as MII (Media Independent interface ), RMII (Reduced Media Independant Interface, reduced MII interface), GMII (Gigabit Media Independant Interface, gigabit MII interface), RGMII (Reduced Gigabit Media Independant Interface, reduced GMII interface), and only one type of interface on one PHY, so when one MAC communicates with a different PHY, an additional interface protocol conversion module is often required to be added to implement interface adaptation between the MAC and the PHY.

For example, when the MAC only outputs the GMII interface, the user 1 needs to realize the protocol conversion of the GMII-RGMII by itself when the PHY of the RGMII interface is applied to the user 1; when the user 2 applies the PHY of the MII interface, the user 2 is required to implement GMII-MII protocol conversion by itself. That is, for different application scenarios, additional workload of interface protocol conversion is required to implement interface adaptation between MAC and PHY, which greatly reduces flexibility of MAC and increases burden of users. Meanwhile, each interface has different working rates, and the working clocks corresponding to the different working rates are different, so that a user can complete interface conversion and clock conversion, and the burden of the user and the complexity of actual use are further increased.

Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.

Disclosure of Invention

The invention aims to provide a multiplexing interface device and an MAC system, wherein the multiplexing interface device can simultaneously provide PHY interfaces of different types, and select corresponding interface output according to the interface type adapted to the PHY connected currently, so that the flexibility of the MAC is improved and the burden of a user is reduced; meanwhile, the clock generating module can complete clock conversion of different interfaces, so that the burden of a user and the complexity of actual use are further reduced.

In order to solve the above technical problems, the present invention provides a multiplexing interface device, including:

the first interface controller is arranged on the MAC and used for outputting a first interface;

the interface conversion module is connected with the first interface controller and is used for converting the first interface into different types of interface output;

the output interface selector is respectively connected with the first interface controller, the interface conversion module and the PHY and is used for selecting a target interface matched with the currently connected PHY from interfaces of different types connected with the output interface selector;

and the clock generation module is respectively connected with the MAC, the first interface controller and the interface conversion module, and is used for generating clock signals meeting the current communication requirements of the MAC and the currently connected PHY according to the current working rate of the MAC and the interface type matched with the currently connected PHY, and correspondingly providing the clock signals to the clock signal line of the target interface.

Preferably, the first interface controller is a GMII controller for outputting a GMII interface;

and the interface conversion module comprises:

the RGMII conversion submodule is respectively connected with the GMII controller and the output interface selector and is used for converting the GMII interface into RGMII interface for output;

The MII conversion submodule is respectively connected with the GMII controller and the output interface selector and is used for converting the GMII interface into MII interface output;

and the RMII conversion sub-module is respectively connected with the MII conversion sub-module and the output interface selector and is used for converting the MII interface into an RMII interface for output.

Preferably, the GMII interface includes a gtx_clk signal indicating a transmit clock generated by the clock generation module, a tx_er signal indicating a transmit data error, a tx_en signal indicating transmit enable, a TXD [7:0] signal indicating transmit data, an rx_clk signal indicating a receive clock generated by the PHY, an rx_dv signal indicating that receive data is valid, an rx_er signal indicating a receive data error, an RXD [7:0] signal indicating receive data, a CRS signal indicating carrier sense, a COL signal indicating collision sense, an MDIO signal indicating management data, an MDC signal indicating management data clock.

Preferably, the RGMII interface includes a gtx_clk signal, a tx_ctl signal for transmitting both tx_en signal and tx_er signal, a TXD [3:0] signal representing transmission data, an rx_clk signal, an rx_ctl signal for transmitting both rx_dv signal and rx_er signal, an RXD [3:0] signal representing reception data, a CRS signal, a COL signal, an MDIO signal, an MDC signal; wherein the RGMII interface multiplexes the same signal as the GMII interface;

Correspondingly, the RGMII conversion submodule comprises:

the transmission clock rising edge sampling unit is respectively connected with the GTX_CLK signal and the TXD [7:0] signal, and is used for sampling the low 4-bit signal at the rising edge of the GTX_CLK signal to obtain a low 4-bit transmission signal; outputting the TX_EN signal to the TX_CTL signal at the rising edge of the GTX_CLK signal;

the transmitting clock falling edge sampling unit is respectively connected with the GTX_CLK signal and the TXD [7:0] signal, and is used for sampling the high 4-bit signal at the falling edge of the GTX_CLK signal to obtain a high 4-bit transmitting signal; outputting the TX_ER signal to the TX_CTL signal on a falling edge of the GTX_CLK signal;

the input end is respectively connected with the rising edge sampling unit of the sending clock and the falling edge sampling unit of the sending clock, and the output end is used as a MUX selector of TXD [3:0] signals and used for controlling the low 4-bit sending signals and the high 4-bit sending signals to be alternately output according to the current working rate of the MAC;

the receiving clock rising edge sampling unit is respectively connected with the RX_CLK signal and the RXD [3:0] signal and is used for sampling the RXD [3:0] signal on the rising edge of the RX_CLK signal to obtain a high 4-bit receiving signal; sampling the RX_CTL signal at the rising edge of the RX_CLK signal and outputting the sampled RX_CTL signal to the RX_DV signal;

The receiving clock falling edge sampling unit is respectively connected with the RX_CLK signal and the RXD [3:0] signal and is used for sampling the RXD [3:0] signal at the falling edge of the RX_CLK signal to obtain a low 4-bit receiving signal; sampling the RX_CTL signal at the falling edge of the RX_CLK signal and outputting the sampled RX_CTL signal to the RX_ER signal;

and the input end is respectively connected with the receiving clock rising edge sampling unit and the receiving clock falling edge sampling unit, and the output end is used as a COM combination module of TXD [7:0] signals and used for combining and outputting the low 4-bit receiving signals and the high 4-bit receiving signals according to the current working rate of the MAC.

Preferably, the MII interface includes TX_CLK, TX_ER, TX_EN, TXD [3:0] and RX_CLK, RX_DV, RX_ER, RXD [3:0] and CRS signals, COL, MDIO and MDC signals representing a transmit clock generated by the PHY; wherein the MII interface multiplexes the same signals as the GMII interface;

correspondingly, the MII conversion submodule comprises:

the low 4-bit extraction unit is respectively connected with the TX_CLK signal and the TXD [7:0] signal and is used for intercepting the low 4-bit signal of the TXD [7:0] signal to be output as a TXD [3:0] signal under the drive of the TX_CLK signal;

The high-order 4-bit 0-supplementing units are respectively connected with the RX_CLK signal and the RXD [3:0] signal and are used for outputting the high-order 4-bit 0-supplementing signals of the RXD [3:0] signal as RXD [7:0] signals under the drive of the RX_CLK signal.

Preferably, the MII conversion sub-module further comprises:

and the interruption unit is used for generating interruption if the current working rate of the MAC is 1000MBps and prompting the selection error of the current output interface of the MAC.

Preferably, the RMII interface includes a ref_clk signal, a tx_en signal, a TXD [1:0] signal, an rx_er signal, a RXD [1:0] signal, a crs_dv signal, an MDIO signal, an MDC signal, which are combined by an rx_dv signal and a CRS signal, which are representative of a reference clock generated by the clock generation module; wherein, the RMII multiplexes the same signal as the MII interface; changing the TX_CLK signal and RX_CLK signal in the MII conversion sub-module to be generated by the clock generation module;

correspondingly, the RMII conversion submodule includes:

a TX CNT counter coupled to the REF_CLK signal for triggering a read instruction every 1 clock cycle of the REF_CLK signal when the current operating rate of the MAC is 100 MBps; when the current working rate of the MAC is 10MBps, triggering a reading instruction every 10 clock cycles of the REF_CLK signal;

The TX_FIFO unit is respectively connected with the TX_CLK signal, the TXD [3:0] signal, the TX_EN signal and the read-write asynchronization of the TX_CNT counter and is used for writing the TXD [3:0] signal into the TX_FIFO unit under the enabling of the TX_EN signal and the driving of the TX_CLK signal; after receiving the reading instruction, firstly reading the low-order 2-bit signal of the TXD [3:0] signal as the TXD [1:0] signal, and then reading the high-order 2-bit signal of the TXD [3:0] signal as the TXD [1:0] signal;

an RX_CNT counter coupled to the REF_CLK signal for triggering a write command every 1 clock cycle of the REF_CLK signal when the current operating rate of the MAC is 100 MBps; when the current working rate of the MAC is 10MBps, triggering a write command every 10 clock cycles of the REF_CLK signal;

the RX_FIFO unit is respectively connected with an RX_CLK signal, an RXD [1:0] signal, a CSR_DV signal and a read-write asynchronism RX_FIFO unit of the RX_CNT counter, and is used for writing the RXD [1:0] signal into the RX_FIFO unit under the condition that the CSR_DV signal is valid and after receiving the write command, so as to sequentially form 4-bit valid data; the 4 bits of valid data are sequentially read out as RXD [3:0] signals under the drive of the RX_CLK signal.

Preferably, the clock generation module includes:

A first frequency divider connected to the local_clk signal representing the LOCAL clock for generating a corresponding clock frequency for the GMII/RGMII conversion submodule based on the current operating rate of the MAC;

a second frequency divider connected to the EXT_CLK signal representing the external input clock for generating corresponding TX_CLK, RX_CLK and REF_CLK signals for the RMII conversion submodule according to the current operating rate of the MAC;

and the clock gating unit is respectively connected with the first frequency divider and the second frequency divider and is used for gating and supplying clock signals matched with the interface type matched with the PHY connected at present to the corresponding conversion submodule.

Preferably, the MAC is directly connected to the PHY; and the MAC and the PHY transmit MDIO signals and MDC signals through a direct connection line between the MAC and the PHY.

In order to solve the technical problem, the invention also provides a MAC system which comprises the MAC and any multiplexing interface device.

The invention provides a multiplexing interface device which comprises a first interface controller, an interface conversion module, an output interface selector and a clock generation module. The first interface controller is arranged on the MAC and used for outputting a first interface; the interface conversion module is used for converting the first interface into different types of interface output; the output interface selector is used for selecting a target interface matched with the PHY connected at present from different types of interfaces connected with the output interface selector to be connected with the PHY; the clock generation module is used for generating clock signals meeting the current communication requirements of the MAC and the interface type adapted to the PHY connected with the MAC according to the current working rate of the MAC and the interface type adapted to the PHY connected with the MAC, and providing the clock signals to clock signal lines of the target interfaces correspondingly. Therefore, the multiplexing interface device can simultaneously provide different types of PHY interfaces, and select corresponding interface output according to the interface type adapted to the currently connected PHY, so that the flexibility of MAC is improved and the burden of a user is reduced; meanwhile, the clock generating module can complete clock conversion of different interfaces, so that the burden of a user and the complexity of actual use are further reduced.

The invention also provides a MAC system which has the same beneficial effects as the multiplexing interface device.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a prior art data interaction architecture between a MAC and PHY;

fig. 2 is a schematic structural diagram of a multiplexing interface device according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a specific structure of a multiplexing interface device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a GMII_RGMII_CTRL submodule according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a GMII_MII_CTRL sub-module according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a MII_RMII_CTRL sub-module according to an embodiment of the present invention;

fig. 7 is a schematic design diagram of a clock_gen submodule according to an embodiment of the present invention.

Detailed Description

The core of the invention is to provide a multiplexing interface device and an MAC system, wherein the multiplexing interface device can simultaneously provide different types of PHY interfaces, and select corresponding interface output according to the interface type adapted to the PHY connected currently, thereby improving the flexibility of the MAC and reducing the burden of a user; meanwhile, the clock generating module can complete clock conversion of different interfaces, so that the burden of a user and the complexity of actual use are further reduced.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a multiplexing interface device according to an embodiment of the invention.

The multiplexing interface device includes:

a first interface controller 1 provided on the MAC for outputting a first interface;

The interface conversion module 2 is connected with the first interface controller 1 and is used for converting the first interface into different types of interface output;

an output interface selector 3 respectively connected with the first interface controller 1, the interface conversion module 2 and the PHY, and used for selecting a target interface adapted to the currently connected PHY from different types of interfaces connected with the output interface selector;

the clock generation module 4 is respectively connected with the MAC, the first interface controller 1 and the interface conversion module 2, and is used for generating clock signals meeting the current communication requirements of the MAC and the current working rate of the MAC and the interface type matched with the PHY connected currently, and providing the clock signals to the clock signal line of the target interface correspondingly.

Specifically, the multiplexing interface device of the present application includes a first interface controller 1, an interface conversion module 2, an output interface selector 3 and a clock generation module 4, and its working principle is:

the first interface controller 1 is disposed on the MAC, and the first interface controller 1 may output the first interface. The interface conversion module 2 is connected with the first interface controller 1, and can convert the first interface output by the first interface controller 1 into different types of interface output. One end of the output interface selector 3 is connected to the first interface controller 1 and the interface conversion module 2, respectively, and the other end is connected to the PHY, so as to select a target interface adapted to the PHY currently connected from the first interface output by the first interface controller 1 and other different types of interfaces output by the interface conversion module 2, and connect the target interface to the PHY (physically, the multiplexing interface device is an external interface), so as to implement interface adaptation between the MAC and the PHY.

Furthermore, the present application is further provided with a clock generation module 4, which can generate clock signals meeting the current communication requirements of the current working rate of the MAC and the interface type adapted to the PHY currently connected, and provide the clock signals to the clock signal line of the target interface adapted to the PHY currently connected, so as to realize communication between the MAC and the PHY.

Based on the above embodiments:

referring to fig. 3, fig. 3 is a schematic diagram of a specific structure of a multiplexing interface device according to an embodiment of the invention.

As an alternative embodiment, the first interface controller 1 is a GMII controller for outputting a GMII interface;

and the interface conversion module 2 includes:

the RGMII conversion submodule is respectively connected with the GMII controller and the output interface selector 3 and is used for converting the GMII interface into RGMII interface output;

the MII conversion submodule is respectively connected with the GMII controller and the output interface selector 3 and is used for converting the GMII interface into MII interface output;

and the RMII conversion sub-module is respectively connected with the MII conversion sub-module and the output interface selector 3 and is used for converting the MII interface into the RMII interface for output.

Specifically, four interfaces between MAC and PHY are first introduced:

1) The MII interface contains 16 signals and 2 management interface signals. The MII interface bi-directionally transfers data in 4-bit bytes. When the clock rate corresponding to the MII interface is 25MHz, the working rate of the MAC can reach 100Mb/s; when the corresponding clock rate of the MII interface is 2.5MHz, the working rate of the MAC can reach 10Mb/s.

TABLE 1

Signal name	Description of the invention	Direction
			TX_CLK	Transmitting clock	PHY→MAC
TX_ER	Transmitting data errors	MAC→PHY
			TX_EN	Transmitting enable	MAC→PHY
TXD[3:0]	Transmitting data	MAC→PHY
			RX_CLK	Receiving clock	PHY→MAC
RX_DV	Receiving data valid	PHY→MAC
			RX_ER	Received data errors	PHY→MAC
RXD[3:0]	Receiving data	PHY→MAC
			CRS	Carrier sensing	PHY→MAC
COL	Collision monitoring	PHY→MAC
			MDIO	Managing data	Two-way
MDC	Managing data clocks	MAC→PHY

RXD [3:0]: the data receives signals, and the total number of the data is 4. TX_ER: transmitting a data error prompt signal, which is synchronous with TX_CLK and valid at a high level, and indicates that data transmitted in the TX_ER validity period is invalid; for 10Mbps rate, TX_ER is not active. RX_ER: receiving a data error prompt signal, synchronizing with RX_CLK, and enabling high level to indicate that data transmitted in the RX_ER validity period is not valid; for 10Mbps rate, RX_ER is not active. TX_EN: the transmit enable signal is asserted only for data transmitted during the tx_en validity period. RX_DV: the receive data valid signal acts like a tx_en of the transmit channel. TX_CLK: transmitting a data reference clock, wherein the clock frequency is 25MHz at the speed of 100 Mbps; at a rate of 10Mbps, the clock frequency is 2.5MHz. Note that the direction of the tx_clk clock is directed from the PHY side to the MAC side, and thus the clock is provided by the PHY. RX_CLK: receiving a data reference clock, wherein the clock frequency is 25MHz at the speed of 100 Mbps; at a rate of 10Mbps, the clock frequency is 2.5MHz. RX_CLK is also provided by the PHY side. CRS: the carrier sense signal does not need to be synchronized to the reference clock, so long as there is data transmission, the CRS is active, and in addition, only the PHY of the CRS is active in half duplex mode. COL: the collision detection signal does not need to be synchronized to the reference clock, only the PHY is active in half duplex mode.

2) The RMII interface saves half of the data lines compared to the MII interface. The RMII interface transmits and receives 2-bit data, and the transmitting and receiving clocks all adopt 50MHz clock sources. At 100Mbps Ethernet rate, the MAC layer samples data on RXD [1:0] once per clock. At 10Mbps Ethernet rate, the MAC layer samples data on RXD [1:0] every 10 clocks, where each data received by the physical layer would be reserved for 10 clocks on RXD [1:0 ].

TABLE 2

Signal name	Description of the invention	Direction
			REF_CLK	Reference clock	External clock provision
TX_EN	Transmitting enable	MAC→PHY
			TXD[1:0]	Transmitting data	MAC→PHY
RX_ER	Received data errors	PHY→MAC
			RXD[1:0]	Receiving data	PHY→MAC
CRS_DV	Carrier and received data activity	PHY→MAC
			MDIO	Managing data	Two-way
MDC	Managing data clocks	MAC→PHY

Crs_dv is a combination of two signals of rx_dv and CRS in the MII interface, and when the physical layer receives the carrier signal, crs_dv becomes valid, and data is sent to RXD. It should be noted that the RMII interface differs from the MII interface not only in halving the data lines, but also in greater differences: the TX_CLK and RX_CLK of the MII interface are PHY transferred to the MAC, while only one clock (REF_CLK of 50M) on the RMII interface is externally provided, both to the MAC and PHY.

3) The GMII interface adopts 8-bit interface data, and the working clock is 125MHz, so that the transmission rate can reach 1000Mbps. The GMII interface is compatible with the 10/100Mbps mode of operation specified by the MII interface, and when used as MII mode, uses 4 of the tx_clk and 8 data lines. When the rate is 100Mbps, the working clock is 25MHz, and the data adopts 4bits lower; at 10Mbps rate, the working clock is 2.5MHz, and the data is 4bits lower.

TABLE 3 Table 3

It should be noted that: the transmit reference clock gtx_clk is different from the tx_clk in the MII interface, which is provided by the PHY chip to the MAC chip, and the gtx_clk in the GMII interface, which is provided by the MAC chip to the PHY chip.

4) Compared with the GMII interface, the RGMII interface has the following characteristics: the transmission/reception data line is changed from 8 to 4, and the clock frequency is 125MHz (double-edge sampling) at the 1Gbit/s rate; at a rate of 100Mbit/s, the clock frequency is 25MHz (single-edge sampling); at a rate of 10Mbit/s, the clock frequency is 2.5MHz (single edge sampling).

TABLE 4 Table 4

Signal name	Description of the invention	Direction
			GTX_CLK	Transmitting clock	MAC→PHY
TX_CTL	Transmission control	MAC→PHY
			TXD[3:0]	Transmitting data	MAC→PHY
RX_CLK	Receiving clock	PHY→MAC
			RX_CTL	Reception control	PHY→MAC
RXD[3:0]	Receiving data	PHY→MAC
			CRS	Carrier sensing	PHY→MAC
COL	Collision monitoring	PHY→MAC
			MDIO	Managing data	Two-way
MDC	Managing data clocks	MAC→PHY

The RGMII clock frequency is still 125mhz, the tx/RX data width is changed from 8 to 4 bits, and the RGMII interface samples data on both the rising and falling edges of the clock in order to keep the transmission rate of 1000Mbps unchanged. TXD [3:0]/RXD [3:0] in the GMII interface is sent on the rising edge of the reference clock, and TXD [7:4]/RXD [7:4] in the GMII interface is sent on the falling edge of the reference clock. RGMI is compatible with two rates of 100Mbps and 10Mbps at the same time, and the reference clock rates are 25MHz and 2.5MHz respectively. The TX_CTL signal line is used for transmitting two kinds of information, namely TX_EN and TX_ER, and transmitting TX_EN on the rising edge of TX_CLK and transmitting TX_ER on the falling edge; similarly, the rx_ctl signal line also carries both rx_dv and rx_er information, with rx_dv being sent on the rising edge of rx_clk and rx_er being sent on the falling edge.

Based on the description of the four interfaces between the MAC and PHY, it can be known from the interface signal definition (including clock) of MII/RMII/GMII/RGMII that these protocols are different, but the internal structure/functions are many overlapped, so this application makes full use of the logic function of the GMII controller, and the MII/RGMII performs partial modification (including clock) based on the GMII controller, so as to implement RGMII/MII controllers (corresponding to gmii_rgmii_ctrl/gmii_mii_ctrl in fig. 3 respectively) respectively, output corresponding RGMII/MII interfaces, and the RMII interfaces are multiplexed gmii_mii_ctrl, corresponding to mii_rmii_ctrl in fig. 3, and output RMII interfaces. The phy_intf_mux is an output interface selector 3, and selects a corresponding interface for output according to a specific interface of the PHY in the current application scenario. The clock_gen is a CLOCK generation module 4, which only generates a CLOCK for the interface controller corresponding to the current PHY interface type, and closes the interface controller CLOCK which is not used, so that the power consumption is greatly reduced.

That is, gmii_ctrl is a stand-alone GMII controller that outputs a GMII interface for use with the PHY of the GMII interface. Gmii_rgmii_ctrl is an RGMII controller (i.e., RGMII conversion submodule) based on a GMII controller, outputs an RGMII interface, and is used in cooperation with a PHY of the RGMII interface. Gmii_mii_ctrl is an MII controller (i.e., an MII conversion sub-module) based on a GMII controller, outputs an MII interface, and is used with the PHY of the MII interface. Mii_rmi_ctrl is a RMII controller (i.e., RMII conversion sub-module) based on gmii_mii_ctrl, outputs a RMII interface, and is used with the PHY of the RMII interface. The principle of reducing power consumption is that CLOCKs are only generated for an interface controller corresponding to the current PHY interface type, for example, when a PHY chip is of a GMII interface type, a clock_GEN only outputs a CLOCK of a GMII channel, and CLOCKs of GMII_RGMII_CTRL, GMII_MII_CTR and MII_RMII_CTRL sub-modules are closed; when the PHY chip type is RGMII interface type, because the RGMII controller multiplexes GMII_CTRL, the clock_GEN only outputs the CLOCKs of the GMII_CTRL and GMII_RGMII_CTRL sub-modules, and the CLOCKs of the GMII_MII_CTRL and MII_RMII_CTRL sub-modules are closed; when the PHY chip type is the MII interface type, because the MII controller multiplexes the GMII_CTRL, the CLOCK_GEN only outputs the CLOCKs of the GMII_CTRL and GMII_MII_CTRL sub-modules, and the CLOCKs of the GMII_RGMII_CTRL and MII_RMII_CTRL sub-modules are closed; when the PHY chip type is RMII interface type, because RMII controller multiplexes MII controller, and MII controller multiplexes GMII controller again, clock_gen outputs only the CLOCKs of gmii_ctrl, gmii_mii_ctrl, mii_rmii_ctrl sub-modules, and turns off the CLOCKs of gmii_rgmii_ctrl sub-modules.

As an alternative embodiment, the GMII interface includes a gtx_clk signal indicating a transmit clock generated by the clock generation module 4, a tx_er signal indicating a transmit data error, a tx_en signal indicating a transmit enable, a TXD [7:0] signal indicating transmit data, an rx_clk signal indicating a receive clock generated by the PHY, an rx_dv signal indicating that receive data is valid, an rx_er signal indicating a receive data error, an RXD [7:0] signal indicating receive data, a CRS signal indicating carrier sense, a COL signal indicating collision sense, an MDIO signal indicating management data, an MDC signal indicating management data clock.

Specifically, the description of the present embodiment is already mentioned in the foregoing embodiments, and the present application is not repeated herein.

Referring to fig. 4, fig. 4 is a schematic design diagram of a gmii_rgmii_ctrl sub-module according to an embodiment of the present invention.

As an alternative embodiment, the RGMII interface includes a gtx_clk signal, a tx_ctl signal for transmitting both tx_en signal and tx_er signal, a TXD [3:0] signal representing transmission data, an rx_clk signal, an rx_ctl signal for transmitting both rx_dv signal and rx_er signal, an RXD [3:0] signal representing reception data, a CRS signal, a COL signal, an MDIO signal, an MDC signal; the RGMII interface multiplexes the same signal as the GMII interface;

Correspondingly, the RGMII conversion submodule includes:

the input end is connected with the rising edge sampling unit of the sending clock and the falling edge sampling unit of the sending clock respectively, and the output end is used as a MUX selector of TXD 3:0 signals and used for controlling the alternate output of the low 4-bit sending signals and the high 4-bit sending signals according to the current working rate of the MAC;

the input end is respectively connected with the rising edge sampling unit of the receiving clock and the falling edge sampling unit of the receiving clock, and the output end is used as a COM combination module of TXD [7:0] signals and used for combining and outputting the low 4-bit receiving signals and the high 4-bit receiving signals according to the current working rate of the MAC.

Specifically, as shown in fig. 4, gmii_rgmii_ctrl submodule function parses:

TX side: converting the transmission time sequence of the GMII into the transmission time sequence of the RGMII, firstly dividing Tx_gmii_data [7:0] input by the GMII into two paths, wherein one path is 4bits lower, namely Tx_gmi_data [3:0]; one way is 4bits high, namely Tx_gmii_data [7:4]. Where Tx_gmii_data [3:0] is sampled with the rising edge of TX_CLK and Tx_gmii_data [7:4] is sampled with the falling edge of TX_CLK. The two sampling results are then input to a MUX selector, which selects based on the MAC's current operating rate mac_speed signal (1000 MBps/100MBps/10MBps, in practice, which is auto-negotiated by the native MAC and the peer MAC). When the mac_speed signal is only the current MAC in 1000MBps mode, the MUX selector outputs tx_gmii_data [3:0] to tx_rgmii_data [3:0] on the rising edge of tx_clk, and the MUX selector outputs tx_gmi_data [7:4] to tx_rgmii_data [3:0] on the falling edge of tx_clk. When the mac_speed signal indicates that the current MAC is in 100MBps/10MBps mode, the MUX selector outputs Tx_gmii_data [3:0] to Tx_rgmii_data [3:0] only on the rising edge of TX_CLK. On the falling edge of TX_CLK, the data remains unchanged. The TX_EN signal is sent to TX_CTL on the rising edge of TX_CLK and the TX_ER signal is sent to TX_CTL on the falling edge of TX_CLK.

RX side: converting RGMII transmission time sequence into GMII transmission time sequence, firstly, respectively sampling Tx_rgmii_data [3:0] at the rising edge and the falling edge of RX_CLK to obtain Tx_rgmii_high_data [3:0] and Tx_rgmii_low_data [3:0], and then sending the Tx_rgmii_data [3:0] to a COM combination module. The COM combining module combines according to the mac_speed signal. When the mac_speed signal indicates that the current MAC is in 1000MBps mode, the COM combination module combines Rx_rgmii_high_data [3:0] and Rx_rgmii_data [3:0] into Rx_gmi_data [7:0] at the rising edge of Rx_CLK

(RX_gmii_data[7:4]＝Rx_rgmii_high_data[3:0]，

RX_gmii_data [3:0] = Rx_rgmii_high_data [3:0 ]). When the mac_speed signal indicates that the current MAC is in 100MBps/100MBps mode, the COM combining module combines rx_rgmii_data [3:0] and 0 into rx_gmi_data [7:0] at the rising edge of rx_clk,

(rx_gmii_data [7:4] =4' h0, rx_gmii_data [3:0] =rx_rgmii_data [3:0 ]). RX_CTL is sampled on the rising edge of RX_CLK, output to RX_DV signal, RX_CLK is sampled on the falling edge of RX_CLK, output to RX_ER signal.

Other: COS signals and COL signals are directly transmitted without processing in the GMII_RGMII_CTRL submodule.

Referring to fig. 5, fig. 5 is a schematic design diagram of a gmii_mii_ctrl sub-module according to an embodiment of the present invention.

As an alternative embodiment, the MII interface includes tx_clk signal, tx_er signal, tx_en signal, TXD [3:0] signal, rx_clk signal, rx_dv signal, rx_er signal, RXD [3:0] signal, CRS signal, COL signal, MDIO signal, MDC signal, which represent the transmit clock generated by the PHY; the MII interface multiplexes the same signal as the GMII interface;

correspondingly, the MII conversion submodule includes:

Specifically, as shown in fig. 5, the gmii_mii_ctrl submodule function parses:

TX side: under the driving of the CLOCK tx_clk input by PHY (note that in GMII mode, tx_clk is generated by clock_gen), the transmission data tx_gmii_data [7:0] of GMII is truncated, and only the lower 4bits are truncated as the output data tx_ mii _data [3:0].

RX side: after the upper bit of RX_ mii _data [3:0] is complemented by 4'H0 under the drive of the clock RX_CLK input by PHY, RX_gmii_data [7:0] = {4' H0, RX_mii_data [3:0] }, input to GMII controller.

Meanwhile, the controller inputs a mac_speed signal, because the MII controller only supports 100/10MBps mode, if the speed mode indicated by mac_speed is 1000MBps, an interrupt is generated on the module, and the current MAC output interface selection error is carried out, so that a prompt of reselection is needed.

Other: the TX_EN, TX_ER, RX_DV and RX_ ER, CRS, COL signals are directly transmitted without processing.

As an alternative embodiment, the MII conversion sub-module further comprises:

Referring to fig. 6, fig. 6 is a schematic design diagram of an mii_rmii_ctrl sub-module according to an embodiment of the present invention.

As an alternative embodiment, the RMII interface includes a ref_clk signal, a tx_en signal, a TXD [1:0] signal, an rx_er signal, a RXD [1:0] signal, a crs_dv signal, an MDIO signal, an MDC signal, which are combined by an rx_dv signal and a CRS signal, which are representative of a reference clock generated by the clock generation module 4; wherein, the RMII interface multiplexes the same signal as the MII interface; changing the TX_CLK signal and RX_CLK signal in the MII conversion sub-module to be generated by the clock generation module 4;

Correspondingly, the RMII conversion submodule includes:

a TX CNT counter coupled to the REF_CLK signal for triggering a read command every 1 clock cycle of the REF_CLK signal when the current operating rate of the MAC is 100 MBps; when the current working rate of the MAC is 10MBps, triggering a reading instruction every 10 clock cycles of the REF_CLK signal;

the TX_FIFO unit is respectively connected with the TX_CLK signal, the TXD [3:0] signal, the TX_EN signal and the TX_CNT counter and is asynchronous in reading and writing, and is used for writing the TXD [3:0] signal into the TX_FIFO unit under the enabling of the TX_EN signal and the driving of the TX_CLK signal; after receiving a reading instruction, firstly reading the low-order 2-bit signal of the TXD [3:0] signal as the TXD [1:0] signal, and then reading the high-order 2-bit signal of the TXD [3:0] signal as the TXD [1:0] signal;

the RX_FIFO unit is respectively connected with the RX_CLK signal, the RXD [1:0] signal, the CSR_DV signal and the RX_CNT counter and is used for writing the RXD [1:0] signal into the RX_FIFO unit under the condition that the CSR_DV signal is valid and after receiving a writing instruction so as to sequentially form 4-bit effective data; the 4 bits of valid data are sequentially read out as RXD [3:0] signals under the driving of the RX_CLK signal.

Specifically, as shown in fig. 6, the mii_rmi_ctrl submodule function parses:

TX side: under the drive of TX_CLK, the Tx_ mii _data is written into TX_FIFO_ASYNC, wherein the TX_FIFO_ASYNC realizes the function of a TX_FIFO controller with asynchronous reading and writing, the writing end data is 4bits, the reading end data is 2bits, and the writing end data is 4bits of low 2bits and then the reading end data is 2bits higher.

Meanwhile, the clock of the write-in end of the TX_FIFO_ASYNC is TX_CLK (25 MHz in 100MBps mode and 2.5MHz in 10MBps mode), and the enable signal of the write-in end is TX_EN.

The clock at the sense end is REF_CLK (50 MHz for each of the clocks in 100/10MBps mode) and the read enable signal is associated with a TX_CNT counter, which is read every REF_CLK clock cycle when mac_speed indicates that the current mode of operation is 100MBps mode. And when mac_speed indicates that the current operation mode is 10MBps mode, the tx_fifo_async is read once only when the count period is 10 (i.e., the value of tx_cnt=9). Wherein, counter TX_CNT is driven by REF_CLK, and is reset to 0 after counting to 9. That is, in 10MBps mode, tx_fifo_async is read once every 10 ref_clk cycles.

Note that: the RMII protocol does not require a tx_er signal and therefore the tx_er signal of the MII does not require access to this module.

RX side: the opposite procedure is the TX side.

Under the drive of RX_CLK, RX_rmii_data [1:0] is written into RX_FIFO_ASYNC. Wherein RX_FIFO_ASYNC is an RX_FIFO controller with asynchronous reading and writing, the clock of the writing end is RX_CLK, the data enabling of the writing end is CSR_DV, and the writing enabling is controlled by RX_CNT. When the mac_speed signal indicates that the current mode of operation is 100MBps mode and csr_dv is high, rx_rmii_data [1:0] is written to rx_fifo_async. And the mac_speed signal indicates that when the current operation mode is 10MBps mode, rx_rmii_data [1:0] is written into rx_fifo_async when csr_dv is high and the count period of rx_cnt is 10 (the value of rx_cnt is 9). Wherein, counter RX_CNT is driven by REF_CLK, and is reset to 0 after counting to 9. That is, in 10MBps mode, rx_fifo_async is written once every 10 ref_clk periods.

It should be noted that, when storing the write data, the RX_FIFO_ASYNC stores the first valid RX_rmii_data [1:0], then stores the second valid RX_rmii_data [1:0], and then stores the second valid RX_rmii_data [1:0], thus forming 4bits of valid data.

And a reading end: under the drive of RX_CLK, 4bits of valid data RX_ mii _data [3:0] are read out.

Crs_col_gen: the submodule generates CRS and COL signals in the MII protocol. According to the content of the signals, the processing is as follows:

CRS＝TX_EN|CSR_DV；

COL＝TX_EN&CSR_DV；

RX_DV is generated by RX_FIFO_ASYNC read logic, and is set to 1 when there is a valid RX_ mii _data [3:0] read.

Referring to fig. 7, fig. 7 is a schematic design diagram of a clock_gen submodule according to an embodiment of the present invention.

As an alternative embodiment, the clock generation module 4 includes:

a first divider coupled to the local_clk signal representing the LOCAL clock for generating a corresponding clock frequency for the GMII/RGMII conversion submodule based on a current operating rate of the MAC;

a second frequency divider coupled to the EXT_CLK signal representing the external input clock for generating corresponding TX_CLK, RX_CLK and REF_CLK signals for the RMII conversion sub-module according to the current operating rate of the MAC;

and the clock gating unit is respectively connected with the first frequency divider and the second frequency divider and is used for gating and supplying a clock signal matched with the interface type matched with the currently connected PHY to the corresponding conversion submodule.

Specifically, as shown in fig. 7, the clock_gen submodule functionally parses:

The main function of the CLOCK GEN sub-module is to generate a CLOCK signal corresponding to the current PHY interface type based on phy_inf (indicating the PHY interface type in the current application scenario) and mac_speed (indicating the MAC current mode).

Local_clk is a LOCAL clock used to generate GMII/RGMII clocks, typically 125MHz. EXT_CLK is an external input clock for the RMII clock, typically 50MHz. DIVIDE0 is the first frequency divider that generates the corresponding clock frequency for the GMII/RGMII controller based on the mode of operation indicated by mac_speed (1000 MBps-125 MHz,100 MBps-25 MHz,10 MPbs-2.5 MHz). DIVIDE1 is a second frequency divider that generates TX_CLK and RX_CLK for the RMII controller based on the mode of operation indicated by mac_speed (100 MBps-25 MHz,10 MPbs-2.5 MHz). REF_CLK outputs 50MHz.

The clock_port_sel is a CLOCK gating unit, and is configured to gate an output CLOCK of the clock_gen according to a result of phy_inf: when the PHY is a GMII interface, the CLOCK_PORT_SEL gates the TX_GMII_CLK, i.e. PORT 1; when the PHY is an MII interface, the CLOCK_PORT_SEL gates the TX_GMII_CLK, i.e. PORT 1; when PHY is RGMII interface, CLOCK_PORT_SEL gates TX_GMII_CLK and TX_RGMII_CLK, i.e. 1 and 2 gates; when PHY is RMII interface, CLOCK_PORT_SEL gates TX_GMII_CLK and TX_RMII_CLK, i.e., PORT 1 and PORT 3 gates.

As an alternative embodiment, the MAC is directly connected to the PHY; and the MAC and the PHY transmit MDIO signals and MDC signals through a direct connection line between the MAC and the PHY.

Specifically, the MDIO interface is used for management control of the MAC and the PHY, and is used for reading and writing a control register and a status register of the PHY, and other protocols have the interface, so as shown in fig. 3, the MAC is directly connected with the PHY, so that the MAC and the PHY transmit the MDIO signal and the MDC signal through a direct connection line between the MAC and the PHY, thereby simplifying line connection.

In conclusion, the core control logic is multiplexed to the greatest extent, so that the code logic is reduced, hardware resources are reduced, and the area of a corresponding chip is reduced; meanwhile, a flexible clock generation module is designed, so that clocks are not output to unnecessary submodules, and the power consumption is greatly reduced.

The application also provides a MAC system, which comprises a MAC and any multiplexing interface device.

The description of the MAC system provided in the present application refers to the embodiment of the multiplexing interface device, and is not repeated herein.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multiplexing interface device, comprising:

the clock generation module is respectively connected with the MAC, the first interface controller and the interface conversion module, and is used for generating clock signals meeting the current communication requirements of the MAC, the first interface controller and the interface conversion module according to the current working rate of the MAC and the interface type matched with the PHY connected currently, and correspondingly providing the clock signals to the clock signal line of the target interface;

The first interface controller is a GMII controller for outputting a GMII interface;

and the interface conversion module comprises:

the RMII conversion sub-module is respectively connected with the MII conversion sub-module and the output interface selector and is used for converting the MII interface into an RMII interface for output;

the clock generation module generates a clock for an interface controller corresponding to the current PHY interface type, and closes the interface controller clock which is not needed to be used;

when the PHY chip is of a GMII interface type, the CLOCK generation module CLOCK_GEN only outputs the CLOCK of the GMII channel, and the CLOCKs of the GMII_RGMII_CTRL, GMII_MII_CTRL and MII_RMII_CTRL sub-modules are closed; when the PHY chip type is RGMII interface type, multiplexing the CLOCKs of the GMII_CTRL and the CLOCK_GEN by the RGMII controller, and closing the CLOCKs of the GMII_MII_CTRL and the MII_RMII_CTRL sub-modules; when the PHY chip type is an MII interface type, multiplexing the GMII_CTRL and the CLOCK_GEN by the MII controller, outputting CLOCKs of the GMII_CTRL and the GMII_MII_CTRL sub-modules only, and closing the CLOCKs of the GMII_RGMII_CTRL and the MII_RMII_CTRL sub-modules; when the PHY chip type is the RMII interface type, multiplexing an MII controller by the RMII controller, multiplexing a GMII controller by the MII controller, outputting CLOCKs of the GMII_CTRL, GMII_MII_CTRL and MII_RMII_CTRL sub-modules by the CLOCK_GEN, and closing the CLOCKs of the GMII_RGMII_CTRL sub-modules;

Wherein, GMII_RGMII_CTRL is an RGMII controller based on the GMII controller; gmii_mii_ctrl is a GMII controller-based MII controller; mii_rmi_ctrl is a RMII controller based on gmii_mii_ctrl; gmii_ctrl is an independent GMII controller; gmii_mii_ctrl is a MII controller based on a GMII controller.

2. The multiplexing interface device of claim 1, wherein the GMII interface includes a gtx_clk signal representing a transmit clock generated by the clock generation module, a tx_er signal representing a transmit data error, a tx_en signal representing a transmit enable, a TXD [7:0] signal representing transmit data, an rx_clk signal representing a receive clock generated by the PHY, an rx_dv signal representing receive data valid, an rx_er signal representing receive data error, an RXD [7:0] signal representing receive data, a CRS signal representing carrier sense, a COL signal representing collision sense, an MDIO signal representing management data, and an MDC signal representing management data clock.

3. The multiplexing interface device of claim 2, wherein the RGMII interface comprises a gtx_clk signal, a tx_ctl signal for transmitting both tx_en signal and tx_er signal, a TXD [3:0] signal representing transmit data, an rx_clk signal, an rx_ctl signal for transmitting both rx_dv signal and rx_er signal, an RXD [3:0] signal representing receive data, a CRS signal, a COL signal, an MDIO signal, an MDC signal; wherein the RGMII interface multiplexes the same signal as the GMII interface;

Correspondingly, the RGMII conversion submodule comprises:

4. The multiplexing interface device of claim 3, wherein the MII interface includes a tx_clk signal, a tx_er signal, a tx_en signal, a TXD [3:0] signal, an rx_clk signal, an rx_dv signal, an rx_er signal, an RXD [3:0] signal, a CRS signal, a COL signal, an MDIO signal, an MDC signal, which represent a transmit clock generated by the PHY; wherein the MII interface multiplexes the same signals as the GMII interface;

correspondingly, the MII conversion submodule comprises:

5. The multiplexing interface device of claim 4, wherein the MII conversion sub-module further comprises:

6. The multiplexing interface device of claim 4, wherein the RMII interface comprises a ref_clk signal, a tx_en signal, a TXD [1:0] signal, an rx_er signal, a RXD [1:0] signal, a crs_dv signal, an MDIO signal, an MDC signal, which are combined by an rx_dv signal and a CRS signal, representing a reference clock generated by the clock generation module; wherein, the RMII multiplexes the same signal as the MII interface; changing the TX_CLK signal and RX_CLK signal in the MII conversion sub-module to be generated by the clock generation module;

correspondingly, the RMII conversion submodule includes:

7. The multiplexing interface device of claim 6, wherein the clock generation module comprises:

8. The multiplexing interface device of claim 7, wherein the MAC is directly connected to the PHY; and the MAC and the PHY transmit MDIO signals and MDC signals through a direct connection line between the MAC and the PHY.

9. A MAC system comprising a MAC and a multiplexing interface device as claimed in any one of claims 1 to 8.