CN112490293A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112490293A CN112490293A CN202011445350.0A CN202011445350A CN112490293A CN 112490293 A CN112490293 A CN 112490293A CN 202011445350 A CN202011445350 A CN 202011445350A CN 112490293 A CN112490293 A CN 112490293A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 210000000746 body region Anatomy 0.000 claims description 31
- 230000015556 catabolic process Effects 0.000 abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 238000002955 isolation Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a semiconductor device and a method of manufacturing the same, the semiconductor device including: the device comprises a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate; the LOCOS and the at least one groove positioned on one side of the LOCOS are formed in the substrate of the active region, the top surface of the LOCOS is higher than the top surface of the substrate, and the bottom wall of the groove is higher than the bottom surface of the groove filling structure; the gate dielectric layer is formed on the inner wall of the groove and the substrate on the periphery of the groove; and the grid electrode layer is formed on the grid dielectric layer and the LOCOS close to the groove. The technical scheme of the invention can reduce the on-resistance without reducing the breakdown voltage.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
Lateral double-diffused metal oxide semiconductors (LDMOS) are now widely used in power ICs, the most important parameters of LDMOS are on-resistance (Ron) and Breakdown Voltage (BV), the smaller the on-resistance the better, the larger the breakdown voltage the better, and the contradictory the two. After the on-resistance and the breakdown voltage are optimized by adjusting the ion implantation conditions, the size of the field plate region, the device size and the like, if the on-resistance is further reduced, the breakdown voltage is reduced, and if the breakdown voltage is further increased, the on-resistance is increased.
For example, as shown in fig. 1a and 1b, an LDMOS with a Local Oxidation isolation structure (LOCOS) containing Silicon is defined, according to the layout, an active region a1 is defined, the LDMOS includes a substrate 10, a body region 11 and a drift region 12 in the substrate 10 of the active region, a body contact region 15 and a source region 16 in the body region 11, and a drain region 17 in the drift region 12, the LDMOS further includes a gate dielectric layer 13 and a gate layer 14 in sequence on the substrate 10, and a field oxide layer 18 between the gate layer 14 and the drain region 17, the field oxide layer 18 is located on one side of the gate dielectric layer 13, a portion of the gate layer 14 is located above the channel, and another portion laterally extends to above the field oxide layer 18, the portion of the gate layer 14 located above the channel constitutes a gate region of the LDMOS, and the portion extending to the field oxide layer 18 constitutes a field plate. The gate dielectric layer 13 and the gate layer 14 extend from the body region 11 onto the drift region 12, the drift region 12 surrounding the field oxide layer 18, the body contact region 15 and the source region 16 being located in the body region 11 on the side of the gate layer 14 remote from the field oxide layer 18. Although the LDMOS of the silicon-containing local oxidation isolation structure shown in fig. 1a and 1b has a longer field oxide layer 18 and a portion of the field oxide layer 18 is located below the gate layer 14, the breakdown voltage is increased, but the current path is also increased, which results in an increase in on-resistance.
Therefore, how to further reduce the on-resistance while maintaining the breakdown voltage unchanged is a problem that needs to be solved at present.
Disclosure of Invention
The invention provides a semiconductor device and a method for manufacturing the same, which can reduce the on-resistance without reducing the breakdown voltage.
To achieve the above object, the present invention provides a semiconductor device comprising:
the device comprises a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate;
the LOCOS and the at least one groove positioned on one side of the LOCOS are formed in the substrate of the active region, the top surface of the LOCOS is higher than the top surface of the substrate, and the bottom wall of the groove is higher than the bottom surface of the groove filling structure;
the gate dielectric layer is formed on the inner wall of the groove and the substrate on the periphery of the groove; and the number of the first and second groups,
and the grid electrode layer is formed on the grid dielectric layer and the LOCOS close to the groove.
Optionally, one side of the trench close to the LOCOS exposes the LOCOS.
Optionally, a length of all the trenches in an edge direction perpendicular to the one side of the LOCOS is greater than a length in an edge direction parallel to the one side of the LOCOS.
Optionally, the semiconductor device includes at least two trenches, and all of the trenches are sequentially arranged along an edge direction parallel to the one side of the LOCOS.
Optionally, two ends of the LOCOS are in contact with the top of the sidewall of the trench filling structure; and two ends of the grid layer extend to the groove filling structure from the part of the LOCOS on the grid dielectric layer and close to the groove.
Optionally, the semiconductor device further includes a body region and a drift region formed in the substrate of the active region, an interface between the body region and the drift region is located below the gate layer, the drift region surrounds the LOCOS, and the trench extends from the drift region to the body region.
Optionally, the semiconductor device further includes a source region and a drain region, the source region is located in the body region of the gate layer far from the LOCOS, and the drain region is located in the drift region of the LOCOS on the side facing away from the source region.
Optionally, an end of the trench facing away from the LOCOS exceeds an end of the gate layer facing away from the LOCOS, and the end of the trench facing away from the LOCOS extends onto the source region.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate;
forming a LOCOS in the substrate of the active region, wherein the top surface of the LOCOS is higher than the top surface of the substrate;
forming at least one groove in the substrate on one side of LOCOS, wherein the bottom wall of the groove is higher than the bottom surface of the groove filling structure;
forming a gate dielectric layer on the inner wall of the groove and the substrate on the periphery of the groove; and the number of the first and second groups,
and forming a gate layer on the gate dielectric layer and a part of the LOCOS close to the groove.
Optionally, one side of the trench close to the LOCOS exposes the LOCOS.
Optionally, a length of all the trenches in an edge direction perpendicular to the one side of the LOCOS is greater than a length in an edge direction parallel to the one side of the LOCOS.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the semiconductor device comprises a LOCOS and at least one groove positioned on one side of the LOCOS, wherein the top surface of the LOCOS is higher than the top surface of a substrate, and the bottom wall of the groove is higher than the bottom surface of a groove filling structure; the gate dielectric layer is formed on the inner wall of the groove and the substrate on the periphery of the groove; and the grid layer is formed on the grid dielectric layer and the LOCOS on the part close to the groove, so that the breakdown voltage is not reduced, and meanwhile, the on-resistance is reduced.
2. The manufacturing method of the semiconductor device of the invention, through forming LOCOS in the substrate of the active area, the top surface of said LOCOS is higher than the top surface of said substrate; forming at least one groove in the substrate on one side of LOCOS, wherein the bottom wall of the groove is higher than the bottom surface of the groove filling structure; forming a gate dielectric layer on the inner wall of the groove and the substrate on the periphery of the groove; and forming a gate layer on the gate dielectric layer and a part of the LOCOS close to the groove. The manufacturing method of the semiconductor device can reduce the on-resistance without reducing the breakdown voltage.
Drawings
FIG. 1a is a layout of a conventional LDMOS structure having a silicon-containing local oxidation isolation structure;
FIG. 1b is a cross-sectional view of the LDMOS of the silicon-containing local oxidation isolation structure shown in FIG. 1a along direction AA';
FIG. 2a is a layout of a semiconductor device according to an embodiment of the present invention;
FIG. 2b is a schematic cross-sectional view of the semiconductor device shown in FIG. 2a along the direction BB';
fig. 2c is a schematic cross-sectional view of the semiconductor device shown in fig. 2a along the direction CC';
fig. 2d is a schematic cross-sectional view of the semiconductor device shown in fig. 2a, taken along direction DD';
FIG. 2e is a schematic cross-sectional view of the semiconductor device shown in FIG. 2a taken along the direction EE';
FIG. 2f is a layout of a semiconductor device according to another embodiment of the present invention;
FIG. 2g is a schematic cross-sectional view of the semiconductor device shown in FIG. 2f, taken along the direction FF';
fig. 3 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4a to 4m are device diagrams in the method of manufacturing the semiconductor device shown in fig. 3.
Wherein the reference numerals of figures 1a to 4m are as follows:
10-a substrate; 11-a body region; 12-a drift region; 13-a gate dielectric layer; 14-a gate layer; 15-a body contact region; 16-a source region; 17-a drain region; 18-field oxide layer; 20-a substrate; 201-pad oxide layer; 202-a silicon nitride layer; 21-a trench filling structure; 211 — a first trench; 22-LOCOS; 221-opening; 23-second trench, trench; 24-a gate dielectric layer; 25-a gate layer; 26-a body region; 261-a source region; 262-a body contact region; 27-a drift region; 271-a drain region; 28-conductive contact plug.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, a semiconductor device and a method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a semiconductor device, referring to fig. 2a to fig. 2g, the semiconductor device includes a substrate 20, a LOCOS22, at least one trench 23, a gate dielectric layer 24, and a gate layer 25, an active region a2 surrounded by a trench filling structure 21 is formed in the substrate 20; the LOCOS22 and at least one trench 23 located at one side of the LOCOS22 are formed in the substrate 20 of the active area a2, the top surface of the LOCOS22 is higher than the top surface of the substrate 20, the bottom wall of the trench 23 is higher than the bottom surface of the trench fill structure 21; the gate dielectric layer 24 is formed on the inner wall of the trench 23 and the substrate 20 at the periphery of the trench 23; the gate layer 25 is formed on the gate dielectric layer 24 and on a portion of the LOCOS22 near the trench 23.
The semiconductor device provided in this embodiment will be described in detail with reference to fig. 2a to 2 g.
An active region a2 surrounded by trench fill structures 21 is formed in the substrate 20. The trench filling structure 21 functions as an isolation.
The substrate 20 may be made of any suitable material known to those skilled in the art.
The LOCOS22 and at least one trench 23 located at one side of the LOCOS22 are formed in the substrate 20 of the active area a2, the top surface of the LOCOS22 is higher than the top surface of the substrate 20, and the bottom wall of the trench 23 is higher than the bottom surface of the trench fill structure 21. LOCOS is a Local Oxidation of Silicon isolation structure (LOCOS).
The top surface of the trench filling structure 21 may be flush with the top surface of the substrate 20, or the top surface of the trench filling structure 21 may be higher than the top surface of the substrate 20.
The depth of the groove 23 may be
The depth of the portion of the trench filling structure 21 in the substrate 20 may be
Two ends of the LOCOS22 are in contact with the top of the sidewall of the trench filling structure 21, and the bottom surface of the LOCOS22 is higher than the bottom surface of the trench filling structure 21.
A side of the trench 23 proximate the LOCOS22 exposes the LOCOS 22. The bottom wall of the trench 23 may be flush with the bottom surface of the LOCOS22, or the bottom wall of the trench 23 is lower than the bottom surface of the LOCOS22 (as shown in fig. 2 e).
The semiconductor device includes at least two trenches 23, all of the trenches 23 being sequentially arranged along an edge direction parallel to the one side of the LOCOS 22.
The gate dielectric layer 24 is formed on the inner wall of the trench 23 and the substrate 20 at the periphery of the trench 23. One side of the gate dielectric layer 24 close to the LOCOS22 is in contact with the LOCOS22, and both ends of the gate dielectric layer 24 in an edge direction parallel to the one side of the LOCOS22 are in contact with the trench filling structure 21.
The gate layer 25 is formed on the gate dielectric layer 24 and on a portion of the LOCOS22 near the trench 23. Both ends of the gate layer 25 (i.e., both ends in the edge direction parallel to the one side of the LOCOS 22) extend from on the gate dielectric layer 24 and on a portion of the LOCOS22 near the trench 23 onto the trench fill structure 21. The LOCOS22 is a field oxide layer of a semiconductor device, a portion of the gate layer 25 above the layout-defined channel region constitutes a gate region of the semiconductor device, and a portion extending to the LOCOS22 constitutes a field plate.
Wherein the gate layer 25 may cover all the trenches 23, that is, the end of the trench 23 facing away from the LOCOS22 does not exceed the end of the gate layer 25 facing away from the LOCOS22, as shown in fig. 2 a; alternatively, the gate layer 25 may cover only a part of the trench 23, i.e. the end of the trench 23 facing away from the LOCOS22 may extend beyond the end of the gate layer 25 facing away from the LOCOS22, as shown in fig. 2 f.
The semiconductor device further comprises a body region 26 and a drift region 27 formed in the substrate 20 of the active region a2, an interface of the body region 26 and the drift region 27 being located below the gate layer 25, the drift region 27 surrounding the LOCOS22, the trench 23 extending from the drift region 27 to the body region 26.
The semiconductor device further comprises a source region 261 and a drain region 271, the source region 261 being located in a body region 26 of the gate layer 25 remote from the LOCOS22, the drain region 271 being located in a drift region 27 of the LOCOS22 on a side facing away from the source region 261. Simultaneously with the formation of the source region 261 and the drain region 271, a body contact region 262 may also be formed in the body region 26, the body contact region 262 being located in the body region 26 of the source region 261 on a side facing away from the gate layer 25, and a trench filling structure 21 being further spaced between the body contact region 262 and the source region 261.
As shown in fig. 2a and 2f, the semiconductor device further includes a conductive contact plug 28 formed on the source region 261, the drain region 271, the body contact region 262 and the gate layer 25, and the conductive contact plug 28 on the gate layer 25 is located above the trench filling structure 21; and as shown in fig. 2f and 2g, an end of the trench 23 facing away from the LOCOS22 may extend onto the source region 261, with the bottom of the conductive contact plug 28 contacting the source region 261 below the trench 23.
In addition, the length of all the trenches 23 in the edge direction perpendicular to the one side of the LOCOS22 is greater than the length in the edge direction parallel to the one side of the LOCOS22, so that the width of the layout-defined channel region increases by a greater extent than the length of the channel region. Since the portion between the source region 261 and the drain region 271, which is located below the gate dielectric layer 24, is a channel region, and the direction between the source region 261 and the drain region 271 is the length direction of the channel region, the length direction of the channel region is the direction perpendicular to the edge of the LOCOS22 on the one side, and the width direction of the channel region is the direction parallel to the edge of the LOCOS22 on the one side, then the length of all the trenches 23 in the length direction of the channel region is greater than the length in the width direction of the channel region.
Specifically, referring to fig. 2a, 2b and 2e, the transverse cross-sectional pattern of the trench 23 is a rectangle, the cross-sectional patterns of the trench 23 along the BB 'and EE' directions are both inverted trapezoids, the short side of the rectangle is connected to the one side of the LOCOS22, and the long side of the rectangle is perpendicular to the one side of the LOCOS 22; defining a length of a bottom wall of the trench 23 in a length direction of the channel region to be L1, a length of a side wall of the trench 23 in the length direction of the channel region to be L3, a length of a bottom wall of the trench 23 in a width direction of the channel region to be L2, a length of a side wall of the trench 23 in the width direction of the channel region to be L4, when one trench 23 is formed, the length of the channel region is increased more than one length L3 and less than two lengths L3 (since a portion of the side wall of the trench 23 near a side of the LOCOS22 is exposed to the LOCOS22 so that the length of the channel region increased by the side wall of the trench 23 near the side of the LOCOS22 is less than a length L3), the width of the channel region is increased by two lengths L4, and since L3 is L4, the length of the channel region is increased by an amount less than the width of the channel region, and L1> L2, the percentage of increase in the width of the channel region (the ratio of the lengths of the two L4 based on the increase in the length of L2) is therefore greater than the percentage of increase in the length of the channel region (less than the ratio of the lengths of the two L3 based on the increase in the length of L1), i.e. the magnitude of the increase in the width of the channel region is greater than the magnitude of the increase in the length of the channel region; the larger the number of the trenches 23, the larger the amount of increase in the width of the channel region, and the larger the magnitude of increase in the width of the channel region, so that the on-resistance is greatly reduced without lowering the breakdown voltage.
Especially for the embodiments shown in fig. 2f and 2g, the end of the trench 23 facing away from the LOCOS22 extends onto the source region 261 and exposes the sidewall of the trench filling structure 21, so that the end of the trench 23 facing away from the LOCOS22 cannot increase the length of the channel region, further increasing the width of the channel region more than the length of the channel region.
As can be seen from the above, at least one trench 23 is formed on one side of LOCOS22, and the at least one trench 23 extends from the drift region 27 to the body region 26, so that the width of the channel region is increased without changing the layout width, for example, the portion of the body region 26 located below the gate layer 25 is an effective channel region, the width of the effective channel region is increased by 50% to 100%, the number of carriers in channel inversion is increased by 50% to 100%, and further, the on-resistance is greatly reduced without reducing the breakdown voltage.
In summary, the semiconductor device provided by the present invention includes: the device comprises a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate; the LOCOS and the at least one groove positioned on one side of the LOCOS are formed in the substrate of the active region, the top surface of the LOCOS is higher than the top surface of the substrate, and the bottom wall of the groove is higher than the bottom surface of the groove filling structure; the gate dielectric layer is formed on the inner wall of the groove and the substrate on the periphery of the groove; and the grid electrode layer is formed on the grid dielectric layer and the LOCOS close to the groove. The semiconductor device of the invention can reduce the on-resistance without reducing the breakdown voltage.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
step S1, providing a substrate, wherein an active area surrounded by a trench filling structure is formed in the substrate;
step S2, forming a LOCOS in the substrate of the active region, wherein the top surface of the LOCOS is higher than the top surface of the substrate;
step S3, forming at least one groove in the substrate at one side of the LOCOS, wherein the bottom wall of the groove is higher than the bottom surface of the groove filling structure;
step S4, forming a gate dielectric layer on the inner wall of the groove and the substrate on the periphery of the groove;
and step S5, forming a gate layer on the gate dielectric layer and the LOCOS close to the groove.
Fig. 4a, 4b, 4d, 4f, 4h, 4j and 4l are schematic cross-sectional views along BB 'direction for manufacturing the semiconductor device shown in fig. 2a, fig. 4c, 4e, 4g, 4i, 4k and 4m are schematic cross-sectional views along DD' direction for manufacturing the semiconductor device shown in fig. 2a, and fig. 4c, 4e, 4g, 4i, 4k and 4m correspond to fig. 4b, 4d, 4f, 4h, 4j and 4l in sequence.
According to step S1, a substrate 20 is provided, and an active region (i.e., the active region a2 shown in fig. 2a and 2 f) surrounded by the trench filling structure 21 is formed in the substrate 20. The substrate 20 may be made of any suitable material known to those skilled in the art. The trench filling structure 21 functions as an isolation.
The trench filling structure 21 may be formed by: firstly, a pad oxide layer 201 and a silicon nitride layer 202 may be covered on the substrate 20; then, as shown in fig. 4a, etching the silicon nitride layer 202, the pad oxide layer 201 and the substrate 20 with a partial thickness in sequence to form a first trench 211 in the substrate 20, where the first trench 211 encloses an active region a 2; then, an insulating dielectric layer (not shown) is formed and filled in the first trench 211, the insulating dielectric layer buries the silicon nitride layer 202 therein, and the insulating dielectric layer is planarized by using a chemical mechanical polishing process until the top surface of the silicon nitride layer 202 is exposed, as shown in fig. 4b, the remaining insulating dielectric layer is the trench filling structure 21, and the top surface of the trench filling structure 21 is higher than the top surface of the substrate 20. The depth of the portion of the trench filling structure 21 in the substrate 20 may be
In step S2, LOCOS22 is formed in the substrate 20 of the active region a2, and the top surface of the LOCOS22 is higher than the top surface of the substrate 20.
The step of forming the LOCOS22 in the substrate 20 of the active region a2 may include: firstly, etching the silicon nitride layer 202 and the pad oxide layer 201 in sequence to form an opening 221 in the silicon nitride layer 202 and the pad oxide layer 201, as shown in fig. 4c, the opening 221 exposes the top surface of the substrate 20 in the region where the LOCOS22 is to be formed, and both ends of the opening 221 also expose the top of the sidewall of the trench filling structure 21; then, referring to fig. 4d and 4e, a local oxidation process is performed on the top of the substrate 20 exposed by the opening 221 to form a LOCOS22 on the top of the substrate 20 in the opening 221, the LOCOS22 further extends into the substrate 20 under the pad oxide 201 on both sides of the opening 221, and both ends of the LOCOS22 are in contact with the top of the sidewall of the trench filling structure 21, the top surface of the LOCOS22 may be higher than the top surface of the pad oxide 201, and the bottom surface of the LOCOS22 is higher than the bottom surface of the trench filling structure 21.
At least one trench 23 is formed in the substrate 20 on the LOCOS22 side, in accordance with step S3, wherein the bottom wall of the trench 23 is higher than the bottom surface of the trench filling structure 21. The depth of the trench 23 in the substrate 20 may be
To distinguish from the first trench 211, a trench 23 formed in the substrate 20 on the LOCOS22 side is defined as a second trench 23. Then, the step of forming at least one second trench 23 in the substrate 20 on the LOCOS22 side may include: etching the silicon nitride layer 202, the pad oxide layer 201 and the substrate 20 with a partial thickness on one side of the LOCOS22 in sequence to form at least one second trench 23 in the substrate 20, as shown in fig. 4f and 4 g; next, the silicon nitride layer 202 and the pad oxide layer 201 are sequentially removed, as shown in fig. 4h and 4 i. In addition, a partial thickness of the trench filling structure 21 may also be removed, so that the top surface of the trench filling structure 21 may be flush with the top surface of the substrate 20.
Wherein a side of the second trench 23 proximate to the LOCOS22 exposes sidewalls of the LOCOS 22. The bottom wall of the second trench 23 may be flush with the bottom surface of the LOCOS22, or the bottom wall of the second trench 23 is lower than the bottom surface of the LOCOS22 (as shown in fig. 2 e).
The method of manufacturing the semiconductor device may include forming at least two second trenches 23 in the substrate 20 at one side of the LOCOS22, all of the second trenches 23 being sequentially arranged along an edge direction parallel to the one side of the LOCOS 22.
According to step S4, a gate dielectric layer 24 is formed on the inner wall of the trench 23 and the substrate 20 at the periphery of the trench 23, that is, the gate dielectric layer 24 is formed on the inner wall of the second trench 23 and the substrate 20 at the periphery of the second trench 23, as shown in fig. 4j and 4 k.
The gate dielectric layer 24 may be formed using a deposition or thermal oxidation process. One side of the gate dielectric layer 24 close to the LOCOS22 is in contact with the LOCOS22 (as shown in fig. 4k, 2d and 2 e), and both ends of the gate dielectric layer 24 in an edge direction parallel to the one side of the LOCOS22 are in contact with the trench filling structure 21 (as shown in fig. 4 j).
According to step S5, a gate layer 25 is formed on the gate dielectric layer 24 and on a portion of the LOCOS22 near the trench 23 (i.e., the second trench 23), as shown in fig. 4m, 2d and 2 e. Also, as shown in fig. 4l and 2c, both ends of the gate layer 25 (i.e., both ends in the edge direction parallel to the one side of the LOCOS 22) extend from on the gate dielectric layer 24 and on a portion of the LOCOS22 near the second trench 23 onto the trench filling structure 21. Conventional deposition, photolithography and etching processes may be used to form the gate layer 25.
The LOCOS22 is a field oxide layer of a semiconductor device, a portion of the gate layer 25 above the layout-defined channel region constitutes a gate region of the semiconductor device, and a portion extending to the LOCOS22 constitutes a field plate.
Wherein the gate layer 25 may cover all of the second trenches 23, that is, the end of the second trench 23 facing away from the LOCOS22 does not exceed the end of the gate layer 25 facing away from the LOCOS22, as shown in fig. 2 a; alternatively, the gate layer 25 may cover only a part of the second trench 23, i.e. the end of the second trench 23 facing away from the LOCOS22 may extend beyond the end of the gate layer 25 facing away from the LOCOS22, as shown in fig. 2 f.
In addition, after forming the at least one trench 23 (i.e., the second trench 23) in the substrate 20 on the LOCOS22 side and before forming the gate dielectric layer 24 on the inner wall of the trench 23 and the substrate 20 at the periphery of the trench 23, specifically, after removing the silicon nitride layer 202 and before removing the pad oxide layer 201 in step S3, ion implantation may be performed on the substrate 20 to form the body region 26 and the drift region 27 in the substrate 20 of the active region a 2. Alternatively, the body region 26 and the drift region 27 may be formed before the first trench 211 is formed.
As shown in fig. 2d and 2e, the boundary between the body region 26 and the drift region 27 is located below the gate layer 25, the drift region 27 surrounds the LOCOS22, and the second trench 23 extends from the drift region 27 to the body region 26.
In addition, after forming the gate layer 25, the method of manufacturing the semiconductor device further includes forming a source region 261 and a drain region 271, the source region 261 being located in the body region 26 of the gate layer 25 away from the LOCOS22, the drain region 271 being located in the drift region 27 of the LOCOS22 on a side facing away from the source region 261. Simultaneously with the formation of the source region 261 and the drain region 271, a body contact region 262 may also be formed in the body region 26, the body contact region 262 being located in the body region 26 of the source region 261 on a side facing away from the gate layer 25, and a trench filling structure 21 being further spaced between the body contact region 262 and the source region 261.
As shown in fig. 2a and 2f, the method of fabricating the semiconductor device further includes forming a conductive contact plug 28 on the source region 261, the drain region 271, the body contact region 262 and the gate layer 25, wherein the conductive contact plug 28 on the gate layer 25 is located above the trench filling structure 21; and as shown in fig. 2f and 2g, an end of the trench 23 facing away from the LOCOS22 may extend onto the source region 261, with the bottom of the conductive contact plug 28 contacting the source region 261 below the trench 23.
In addition, the length of all the trenches 23 in the edge direction perpendicular to the one side of the LOCOS22 is greater than the length in the edge direction parallel to the one side of the LOCOS22, so that the width of the layout-defined channel region increases by a greater extent than the length of the channel region. Since the portion between the source region 261 and the drain region 271, which is located below the gate dielectric layer 24, is a channel region, and the direction between the source region 261 and the drain region 271 is the length direction of the channel region, the length direction of the channel region is the direction perpendicular to the edge of the LOCOS22 on the one side, and the width direction of the channel region is the direction parallel to the edge of the LOCOS22 on the one side, then the length of all the trenches 23 in the length direction of the channel region is greater than the length in the width direction of the channel region. For specific reference, the description of the semiconductor device is omitted here.
As can be seen from the above steps, at least one trench 23 (i.e., the second trench 23) is formed on one side of the LOCOS22, and the at least one trench 23 extends from the drift region 27 to the body region 26, so that the width of the effective channel region is increased without changing the layout width, for example, the portion of the body region 26 located below the gate layer 25 is the effective channel region, the width of the effective channel region is increased by 50% to 100%, the number of carriers in channel inversion is increased by 50% to 100%, and further, the on-resistance is greatly reduced without reducing the breakdown voltage.
In addition, the steps in the method for manufacturing a semiconductor device are not limited to the above formation order, and the order of the steps can be adaptively adjusted.
In summary, the method for manufacturing a semiconductor device provided by the present invention includes: providing a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate; forming a LOCOS in the substrate of the active region, wherein the top surface of the LOCOS is higher than the top surface of the substrate; forming at least one groove in the substrate on one side of LOCOS, wherein the bottom wall of the groove is higher than the bottom surface of the groove filling structure; forming a gate dielectric layer on the inner wall of the groove and the substrate on the periphery of the groove; and forming a gate layer on the gate dielectric layer and a part of the LOCOS close to the groove. The manufacturing method of the semiconductor device can reduce the on-resistance without reducing the breakdown voltage.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. A semiconductor device, comprising:
the device comprises a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate;
the LOCOS and the at least one groove positioned on one side of the LOCOS are formed in the substrate of the active region, the top surface of the LOCOS is higher than the top surface of the substrate, and the bottom wall of the groove is higher than the bottom surface of the groove filling structure;
the gate dielectric layer is formed on the inner wall of the groove and the substrate on the periphery of the groove; and the number of the first and second groups,
and the grid electrode layer is formed on the grid dielectric layer and the LOCOS close to the groove.
2. The semiconductor device according to claim 1, wherein a side of the trench close to the LOCOS exposes the LOCOS.
3. The semiconductor device according to claim 1, wherein lengths of all the trenches in an edge direction perpendicular to the one side of the LOCOS are larger than lengths in an edge direction parallel to the one side of the LOCOS.
4. The semiconductor device according to claim 1, wherein the semiconductor device includes at least two trenches, all of which are sequentially arranged along an edge direction parallel to the one side of the LOCOS.
5. The semiconductor device according to claim 1, wherein both ends of the LOCOS are in contact with top portions of sidewalls of the trench filling structures; and two ends of the grid layer extend to the groove filling structure from the part of the LOCOS on the grid dielectric layer and close to the groove.
6. The semiconductor device of claim 1, further comprising a body region and a drift region formed in the substrate of the active region, an interface of the body region and the drift region being located below the gate layer, the drift region surrounding the LOCOS, the trench extending from the drift region to the body region.
7. The semiconductor device of claim 6, further comprising a source region and a drain region, the source region being located in a body region of the gate layer away from the LOCOS, the drain region being located in a drift region of the LOCOS on a side of the LOCOS facing away from the source region.
8. The semiconductor device of claim 7, wherein an end of the trench facing away from the LOCOS extends beyond an end of the gate layer facing away from the LOCOS, and the end of the trench facing away from the LOCOS extends onto the source region.
9. A method of manufacturing a semiconductor device, comprising:
providing a substrate, wherein an active region surrounded by a groove filling structure is formed in the substrate;
forming a LOCOS in the substrate of the active region, wherein the top surface of the LOCOS is higher than the top surface of the substrate;
forming at least one groove in the substrate on one side of LOCOS, wherein the bottom wall of the groove is higher than the bottom surface of the groove filling structure;
forming a gate dielectric layer on the inner wall of the groove and the substrate on the periphery of the groove; and the number of the first and second groups,
and forming a gate layer on the gate dielectric layer and a part of the LOCOS close to the groove.
10. The method for manufacturing a semiconductor device according to claim 9, wherein a side of the trench close to the LOCOS exposes the LOCOS.
11. The manufacturing method of a semiconductor device according to claim 9, wherein lengths of all the trenches in an edge direction perpendicular to the one side of the LOCOS are larger than lengths in an edge direction parallel to the one side of the LOCOS.
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| US20050001265A1 (en) * | 2003-06-13 | 2005-01-06 | Satoshi Shiraki | Semiconductor device and method for manufacturing the same |
| EP1580813A2 (en) * | 2004-03-26 | 2005-09-28 | Sharp Kabushiki Kaisha | Semiconductor substrate, semiconductor device, and manufacturing methods for them |
| JP2009170468A (en) * | 2008-01-10 | 2009-07-30 | Sharp Corp | Mos field-effect transistor |
| CN102097473A (en) * | 2009-11-17 | 2011-06-15 | 美格纳半导体有限会社 | Semiconductor device |
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| US20050001265A1 (en) * | 2003-06-13 | 2005-01-06 | Satoshi Shiraki | Semiconductor device and method for manufacturing the same |
| EP1580813A2 (en) * | 2004-03-26 | 2005-09-28 | Sharp Kabushiki Kaisha | Semiconductor substrate, semiconductor device, and manufacturing methods for them |
| JP2009170468A (en) * | 2008-01-10 | 2009-07-30 | Sharp Corp | Mos field-effect transistor |
| CN102097473A (en) * | 2009-11-17 | 2011-06-15 | 美格纳半导体有限会社 | Semiconductor device |
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| WO2023028901A1 (en) * | 2021-08-31 | 2023-03-09 | 长江存储科技有限责任公司 | Method for manufacturing semiconductor device, and semiconductor device and three-dimensional memory |
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