CN112599602B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN112599602B
CN112599602B CN202011445253.1A CN202011445253A CN112599602B CN 112599602 B CN112599602 B CN 112599602B CN 202011445253 A CN202011445253 A CN 202011445253A CN 112599602 B CN112599602 B CN 112599602B
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trench
groove
filling structure
substrate
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CN112599602A (en
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程亚杰
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Wuhan Xinxin Integrated Circuit Co.,Ltd.
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device including: the device comprises a substrate, wherein an active region surrounded by a first groove filling structure is formed in the substrate; the second groove filling structure and at least one third groove positioned on one side of the second groove filling structure are formed in the substrate of the active area, and the bottom wall of the third groove is higher than the bottom surface of the first groove filling structure; the gate dielectric layer is formed on the inner wall of the third groove and the substrate on the periphery of the third groove; and the grid electrode layer is formed on the grid dielectric layer and a part of the second groove filling structure close to the third groove. The technical scheme of the invention can reduce the on-resistance without reducing the breakdown voltage.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a semiconductor device and a method for fabricating the same.
Background
Lateral double-diffused metal oxide semiconductors (LDMOS) are now widely used in power ICs, the most important parameters of LDMOS are on-resistance (Ron) and Breakdown Voltage (BV), the smaller the on-resistance the better, the larger the breakdown voltage the better, and the contradictory the two. After the on-resistance and the breakdown voltage are optimized by adjusting the ion implantation conditions, the size of the field plate region, the device size and the like, if the on-resistance is further reduced, the breakdown voltage is reduced, and if the breakdown voltage is further increased, the on-resistance is increased.
For example, as shown in fig. 1a and 1b, an LDMOS including a Shallow Trench Isolation (STI) is defined by layout as an active region a1, the LDMOS includes a substrate 10, a body region 11 and a drift region 12 located in the substrate 10 of the active region, a body contact region 15 and a source region 16 located in the body region 11, and a drain region 17 located in the drift region 12, and further includes a gate dielectric layer 13 and a gate layer 14 sequentially located on the substrate 10, and a shallow trench isolation structure 18 located in the substrate 10 of the active region a 1. The shallow trench isolation structure 18 is a field oxide layer of the LDMOS, the shallow trench isolation structure 18 is located on one side of the gate dielectric layer 13, one part of the gate layer 14 is located above the channel, the other part of the gate layer extends laterally to above the shallow trench isolation structure 18, the part of the gate layer 14 located above the channel forms a gate region of the LDMOS, and the part extending to the shallow trench isolation structure 18 forms a field plate. The depth of the shallow trench isolation structure 18 is the same as the depth of the shallow trench isolation structure (not shown) at the periphery of the active region a1, the gate dielectric layer 13 and the gate electrode layer 14 extend from the body region 11 to the drift region 12, the drift region 12 surrounds the shallow trench isolation structure 18, the drain region 17 is located in the drift region 12 at the side of the shallow trench isolation structure 18 away from the gate electrode layer 14, and the body contact region 15 and the source region 16 are located in the body region 11 at the side of the gate electrode layer 14 away from the shallow trench isolation structure 18. Although the LDMOS with shallow trench isolation shown in fig. 1a and 1b has a high breakdown voltage due to the shallow trench isolation 18 being partially located under the gate layer 14, the current passing through the bottom of the deep shallow trench isolation 18 results in a high on-resistance.
Therefore, how to further reduce the on-resistance while maintaining the breakdown voltage unchanged is a problem that needs to be solved at present.
Disclosure of Invention
The invention provides a semiconductor device and a method for manufacturing the same, which can reduce the on-resistance without reducing the breakdown voltage.
To achieve the above object, the present invention provides a semiconductor device comprising:
the device comprises a substrate, wherein an active region surrounded by a first groove filling structure is formed in the substrate;
the second groove filling structure and at least one third groove positioned on one side of the second groove filling structure are formed in the substrate of the active area, and the bottom wall of the third groove is higher than the bottom surface of the first groove filling structure;
the gate dielectric layer is formed on the inner wall of the third groove and the substrate on the periphery of the third groove; and the number of the first and second groups,
and the grid electrode layer is formed on the grid dielectric layer and the part of the second groove filling structure close to the third groove.
Optionally, one side of the third trench close to the second trench filling structure is exposed out of the second trench filling structure.
Optionally, the length of all the third trenches in the direction perpendicular to the edge of the one side of the second trench filling structure is greater than the length of all the third trenches in the direction parallel to the edge of the one side of the second trench filling structure.
Optionally, the semiconductor device includes at least two third trenches, and all of the third trenches are sequentially arranged along an edge direction parallel to the one side of the second trench filling structure.
Optionally, a bottom surface of the second trench filling structure is flush with a bottom surface of the first trench filling structure; or the bottom surface of the second trench filling structure is flush with the bottom wall of the third trench.
Optionally, two ends of the second trench filling structure are in contact with the sidewall of the first trench filling structure; and two ends of the grid layer extend to the first groove filling structure from the upper part of the grid dielectric layer and the part of the second groove filling structure close to the third groove.
Optionally, the semiconductor device further includes a body region and a drift region formed in the substrate of the active region, an interface between the body region and the drift region is located below the gate layer, the drift region surrounds the second trench filling structure, and the third trench extends from the drift region to the body region.
Optionally, the semiconductor device further includes a source region and a drain region, the source region is located in the body region of the gate layer far away from the second trench filling structure, and the drain region is located in the drift region of the second trench filling structure on the side facing away from the source region.
Optionally, an end of the third trench facing away from the second trench filling structure exceeds an end of the gate layer facing away from the second trench filling structure, and the end of the third trench facing away from the second trench filling structure extends onto the source region.
The present invention also provides a method for manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first trench, a second trench and at least one third trench in the substrate, wherein the first trench encloses an active region in the substrate, the second trench is formed in the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, and the depth of the third trench is smaller than that of the first trench;
forming a first trench filling structure in the first trench and a second trench filling structure in the second trench;
forming a gate dielectric layer on the inner wall of the third groove and the substrate on the periphery of the third groove; and (c) a second step of,
and forming a gate layer on the gate dielectric layer and a part of the second trench filling structure close to the third trench.
Optionally, one side of the third groove close to the second groove is communicated with the second groove.
Optionally, the length of all the third trenches in an edge direction perpendicular to the one side of the second trench is greater than the length in an edge direction parallel to the one side of the second trench.
Optionally, the step of forming the first trench, the second trench and the at least one third trench in the substrate includes:
forming a first groove in the substrate, and simultaneously forming a second groove and at least one third groove in the substrate, wherein the depth of the second groove is the same as that of the third groove;
or, a first trench and a second trench are simultaneously formed in the substrate, and then at least one third trench is formed in the substrate, wherein the depth of the second trench is the same as that of the first trench.
Optionally, the step of forming the first trench filling structure in the first trench and forming the second trench filling structure in the second trench includes:
forming an insulating medium layer to be filled in the first groove, the second groove and the third groove; and the number of the first and second groups,
and removing the insulating medium layer in the third groove to form a first groove filling structure in the first groove and a second groove filling structure in the second groove.
Optionally, two ends of the second trench are communicated with the side wall of the first trench; and two ends of the grid layer extend to the first groove filling structure from the upper part of the grid dielectric layer and the part of the second groove filling structure close to the third groove.
Optionally, the manufacturing method of the semiconductor device further includes forming a body region and a drift region in the substrate of the active region; the junction of the body region and the drift region is located below the gate layer, the drift region surrounds the second trench, and the third trench extends from the drift region to the body region.
Optionally, the manufacturing method of the semiconductor device further includes forming a source region and a drain region, the source region is located in the body region of the gate layer far away from the second trench filling structure, and the drain region is located in the drift region of the second trench filling structure on the side facing away from the source region.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the semiconductor device comprises at least one third groove positioned on one side of the second groove filling structure, wherein the bottom wall of the third groove is higher than the bottom surface of the first groove filling structure, and the gate layer is formed on the gate dielectric layer and the part, close to the third groove, of the second groove filling structure, so that the breakdown voltage is not reduced, and the on-resistance is reduced.
2. According to the manufacturing method of the semiconductor device, the first groove, the second groove and the at least one third groove are formed in the substrate, the first groove surrounds an active region in the substrate, the second groove is formed in the substrate of the active region, the at least one third groove is formed in the substrate of the active region on one side of the second groove, and the depth of the third groove is smaller than that of the first groove; forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench; forming a gate dielectric layer on the inner wall of the third groove and the substrate on the periphery of the third groove; and forming a gate layer on the gate dielectric layer and a part of the second trench filling structure close to the third trench, so that the breakdown voltage is not reduced and the on-resistance is reduced.
Drawings
FIG. 1a is a layout of a conventional LDMOS device with a shallow trench isolation structure;
FIG. 1b is a schematic cross-sectional view of the LDMOS with the shallow trench isolation structure shown in FIG. 1a along direction AA';
FIG. 2a is a layout of a semiconductor device according to an embodiment of the present invention;
FIG. 2b is a schematic cross-sectional view of the semiconductor device shown in FIG. 2a along the direction BB';
fig. 2c is a schematic cross-sectional view of the semiconductor device shown in fig. 2a along the direction CC';
FIG. 2d is a schematic cross-sectional view of the semiconductor device shown in FIG. 2a taken along the direction DD';
FIG. 2e is a schematic cross-sectional view of the semiconductor device shown in FIG. 2a taken along the direction EE';
FIG. 2f is a layout of a semiconductor device according to another embodiment of the present invention;
FIG. 2g is a schematic cross-sectional view of the semiconductor device shown in FIG. 2f, taken along the direction FF';
fig. 3 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 4a to 4m are device diagrams in the method of manufacturing the semiconductor device shown in fig. 3.
Wherein the reference numerals of figures 1a to 4m are as follows:
10-a substrate; 11-a body region; 12-a drift region; 13-a gate dielectric layer; 14-a gate layer; 15-body contact region; 16-a source region; 17-a drain region; 18-shallow trench isolation structures; 20-a substrate; 201-pad oxide layer; 202-a silicon nitride layer; 203-insulating dielectric layer; 21-a first trench fill structure; 211 — a first trench; 22-a second trench filling structure; 221-a second trench; 23-a third trench; 24-a gate dielectric layer; 25-a gate layer; 26-body region; 261-a source region; 262-a body contact region; 27-a drift region; 271-a drain region; 28-conductive contact plug.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, a semiconductor device and a method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided for the purpose of facilitating and clearly illustrating embodiments of the present invention.
An embodiment of the present invention provides a semiconductor device, referring to fig. 2a to 2g, the semiconductor device includes a substrate 20, a second trench filling structure 22, at least one third trench 23, a gate dielectric layer 24, and a gate layer 25, an active region a2 surrounded by the first trench filling structure 21 is formed in the substrate 20; the second trench filling structure 22 and the at least one third trench 23 located at one side of the second trench filling structure 22 are formed in the substrate 20 of the active area a2, and a bottom wall of the third trench 23 is higher than a bottom surface of the first trench filling structure 21; the gate dielectric layer 24 is formed on the inner wall of the third trench 23 and the substrate 20 at the periphery of the third trench 23; the gate layer 25 is formed on the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23.
The semiconductor device provided by the present embodiment is described in detail below with reference to fig. 2a to 2 g.
An active region a2 surrounded by the first trench filling structure 21 is formed in the substrate 20.
The substrate 20 may be made of any suitable material known to those skilled in the art.
The second trench filling structure 22 and the at least one third trench 23 located at one side of the second trench filling structure 22 are formed in the substrate 20 of the active area a2, and a bottom wall of the third trench 23 is higher than a bottom surface of the first trench filling structure 21.
The top surfaces of the first trench filling structure 21 and the second trench filling structure 22 may be flush with the top surface of the substrate 20, or the top surfaces of the first trench filling structure 21 and the second trench filling structure 22 may be higher than the top surface of the substrate 20. The first trench filling structure 21 and the second trench filling structure 22 both function as an isolation.
A bottom surface of the second trench filling structure 22 may be flush with a bottom surface of the first trench filling structure 21, a depth of the third trench 23 may be less than depths of portions of the first trench filling structure 21 and the second trench filling structure 22 in the substrate 20, and a depth of the third trench 23 may be
Figure BDA0002824143420000071
The depth of the portions of the first trench filling structure 21 and the second trench filling structure 22 in the substrate 20 may be
Figure BDA0002824143420000072
Alternatively, the bottom surface of the second trench filling structure 22 is flush with the bottom wall of the third trench 23, that is, the depth of the portion of the second trench filling structure 22 located in the substrate 20 and the depth of the third trench 23 are both smaller than the depth of the portion of the first trench filling structure 21 located in the substrate 20, and the depth of the portion of the second trench filling structure 22 located in the substrate 20 and the depth of the third trench 23 may be equal to
Figure BDA0002824143420000073
The depth of the portion of the first trench filling structure 21 in the substrate 20 may be
Figure BDA0002824143420000074
If the depth of the third trench 23 is less than the depths of the portions of the first trench filling structure 21 and the second trench filling structure 22 located in the substrate 20, one side of the third trench 23 close to the second trench filling structure 22 exposes the top of the sidewall of the second trench filling structure 22, and the entire sidewalls of the two ends of the second trench filling structure 22 are in contact with the sidewall of the first trench filling structure 21; if the depth of the portion of the second trench filling structure 22 located in the substrate 20 and the depth of the third trench 23 are both smaller than the depth of the portion of the first trench filling structure 21 located in the substrate 20, the entire sidewall of the third trench 23 close to the side of the second trench filling structure 22 contacts the sidewall of the second trench filling structure 22, and two ends of the second trench filling structure 22 contact the top of the sidewall of the first trench filling structure 21.
The semiconductor device may include at least two third trenches 23, all of the third trenches 23 being sequentially arranged along an edge direction parallel to the one side of the second trench filling structure 22.
The gate dielectric layer 24 is formed on the inner wall of the third trench 23 and the substrate 20 at the periphery of the third trench 23. One side of the gate dielectric layer 24 close to the second trench filling structure 22 is in contact with the second trench filling structure 22, and two ends of the gate dielectric layer 24 in the edge direction parallel to the one side of the second trench filling structure 22 are in contact with the first trench filling structure 21.
The gate layer 25 is formed on the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23. Both ends of the gate layer 25 (i.e., both ends in the edge direction parallel to the one side of the second trench filling structure 22) extend from the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23 onto the first trench filling structure 21. The second trench filling structure 22 is a field oxide layer of a semiconductor device, a portion of the gate layer 25 located above the layout-defined channel region forms a gate region of the semiconductor device, and a portion extending to the second trench filling structure 22 forms a field plate.
Wherein the gate layer 25 may cover all of the third trenches 23, that is, the end of the third trench 23 facing away from the second trench filling structure 22 does not exceed the end of the gate layer 25 facing away from the second trench filling structure 22, as shown in fig. 2 a; alternatively, the gate layer 25 may cover only a portion of the third trench 23, i.e., an end of the third trench 23 facing away from the second trench filling structure 22 may extend beyond an end of the gate layer 25 facing away from the second trench filling structure 22, as shown in fig. 2 f.
The semiconductor device further comprises a body region 26 and a drift region 27 formed in the substrate 20 of the active region a2, an interface of the body region 26 and the drift region 27 is located below the gate layer 25, the drift region 27 surrounds the second trench filling structure 22, and the third trench 23 extends from the drift region 27 to the body region 26.
The semiconductor device further comprises a source region 261 and a drain region 271, wherein the source region 261 is located in the body region 26 of the gate layer 25 away from the second trench filling structure 22, and the drain region 271 is located in the drift region 27 of the second trench filling structure 22 on the side facing away from the source region 261. Simultaneously with the formation of the source region 261 and the drain region 271, a body contact region 262 may be formed in the body region 26, the body contact region 262 being located in the body region 26 of the source region 261 on a side facing away from the gate layer 25, and a first trench filling structure 21 being further spaced between the body contact region 262 and the source region 261.
As shown in fig. 2a and 2f, the semiconductor device further comprises a conductive contact plug 28 formed on the source region 261, the drain region 271, the body contact region 262 and the gate layer 25, and the conductive contact plug 28 on the gate layer 25 is located above the first trench filling structure 21; and as shown in fig. 2f and 2g, an end of the third trench 23 facing away from the second trench filling structure 22 may extend onto the source region 261, and a bottom of the conductive contact plug 28 contacts the source region 261 under the third trench 23.
In addition, the length of all the third trenches 23 in the direction perpendicular to the edge of the one side of the second trench filling structure 22 is greater than the length in the direction parallel to the edge of the one side of the second trench filling structure 22, so that the width of the layout-defined channel region is increased by a greater extent than the length of the channel region. Since the portion between the source region 261 and the drain region 271, which is located below the gate dielectric layer 24, is a channel region, and the direction between the source region 261 and the drain region 271 is the length direction of the channel region, the length direction of the channel region is the direction perpendicular to the edge of the one side of the second trench filling structure 22, and the width direction of the channel region is the direction parallel to the edge of the one side of the second trench filling structure 22, then, the length of all the third trenches 23 in the length direction of the channel region is greater than the length in the width direction of the channel region.
Specifically, referring to fig. 2a, 2b and 2e, the transverse cross-sectional profile of the third trench 23 is rectangular, the cross-sectional profiles of the third trench 23 along the BB 'and EE' directions are both inverted trapezoids, the short side of the rectangle is connected to the one side of the second trench filling structure 22, and the long side of the rectangle is perpendicular to the one side of the second trench filling structure 22; defining a length of a bottom wall of the third trench 23 in a length direction of the channel region to be L1, a length of a side wall of the third trench 23 in the length direction of the channel region to be L3, a length of a bottom wall of the third trench 23 in a width direction of the channel region to be L2, and a length of a side wall of the third trench 23 in the width direction of the channel region to be L4, when one third trench 23 is formed, the length of the channel region is increased by one length L3 (since the entire side wall of the third trench 23 on the side close to the second trench filling structure 22 is exposed to the second trench filling structure 22, so that the side wall of the third trench 23 on the side close to the second trench filling structure 22 fails to increase the length of the channel region), the width of the channel region is increased by two lengths L4, and since L3 is L4, then, the length of the channel region is increased by an amount smaller than the width of the channel region, and L1> L2, so that the percentage of increase in the width of the channel region (the ratio of the lengths of two L4 based on the increase in the length of L2) is greater than the percentage of increase in the length of the channel region (the ratio of the length of one L3 based on the increase in the length of L1), i.e., the magnitude of the increase in the width of the channel region is greater than the magnitude of the increase in the length of the channel region; the larger the number of the third trenches 23, the larger the amount of increase in the width of the channel region, and the larger the magnitude of increase in the width of the channel region, so that the on-resistance is greatly reduced without lowering the breakdown voltage.
Especially for the embodiments shown in fig. 2f and fig. 2g, since the end of the third trench 23 facing away from the second trench filling structure 22 extends onto the source region 261 and exposes the sidewall of the first trench filling structure 21, the length of the channel region cannot be increased by the end of the third trench 23 facing away from the second trench filling structure 22, and the width of the channel region is further increased more than the length of the channel region.
As can be seen from the above, since at least one third trench 23 is formed on one side of the second trench filling structure 22, and the at least one third trench 23 extends from the drift region 27 to the body region 26, the width of the channel region is increased without changing the width of the layout, for example, the portion of the body region 26 located below the gate layer 25 is an effective channel region, the width of the effective channel region is increased by 50% to 100%, the number of carriers in channel inversion is increased by 50% to 100%, and further, the on-resistance is greatly reduced while the breakdown voltage is not reduced.
And if the thickness of the portion of the second trench filling structure 22 located in the substrate 20 is the same as the depth of the third trench 23 and both are smaller than the thickness of the portion of the first trench filling structure 21 located in the substrate 20, the thickness of the second trench filling structure 22 located in the substrate 20 is reduced, so that the on-resistance is further reduced.
In summary, the semiconductor device provided by the present invention includes: the device comprises a substrate, wherein an active region surrounded by a first groove filling structure is formed in the substrate; the second groove filling structure and at least one third groove positioned on one side of the second groove filling structure are formed in the substrate of the active area, and the bottom wall of the third groove is higher than the bottom surface of the first groove filling structure; the gate dielectric layer is formed on the inner wall of the third groove and the substrate on the periphery of the third groove; and the grid electrode layer is formed on the grid dielectric layer and a part of the second groove filling structure close to the third groove. The semiconductor device of the invention can reduce the on-resistance without reducing the breakdown voltage.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, and referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, where the method for manufacturing a semiconductor device includes:
step S1, providing a substrate;
step S2, forming a first trench, a second trench and at least one third trench in the substrate, where the first trench encloses an active region in the substrate, the second trench is formed in the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, and the depth of the third trench is smaller than that of the first trench;
step S3, forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench;
step S4, forming a gate dielectric layer on the inner wall of the third trench and the substrate at the periphery of the third trench;
and step S5, forming a gate layer on the gate dielectric layer and on a portion of the second trench filling structure close to the third trench.
Fig. 4a, 4b, 4d, 4f, 4h, 4j and 4l are schematic cross-sectional views along BB 'direction for manufacturing the semiconductor device shown in fig. 2a, fig. 4c, 4e, 4g, 4i, 4k and 4m are schematic cross-sectional views along CC' direction for manufacturing the semiconductor device shown in fig. 2a, and fig. 4c, 4e, 4g, 4i, 4j and 4m correspond to fig. 4b, 4d, 4f, 4h, 4j and 4l in sequence.
According to step S1, a substrate 20 is provided, and the material of the substrate 20 may be any suitable substrate known to those skilled in the art.
In step S2, a first trench 211, a second trench 221 and at least one third trench 23 are formed in the substrate 20, the first trench 211 enclosing an active region (i.e., the active region a2 shown in fig. 2a and 2 f) in the substrate 20, the second trench 221 being formed in the substrate 20 of the active region a2, the at least one third trench 23 being formed in the substrate 20 of the active region a2 on one side of the second trench 221, the depth of the third trench 23 being smaller than the depth of the first trench 211.
The step of forming the first trench 211, the second trench 221 and the at least one third trench 23 in the substrate 20 comprises:
first, a first trench 211 is formed in the substrate 20, and then a second trench 221 and at least one third trench 23 are simultaneously formed in the substrate 20. Specifically, a pad oxide layer 201 and a silicon nitride layer 202 may be covered on the substrate 20; then, as shown in fig. 4a, etching the silicon nitride layer 202, the pad oxide layer 201 and the substrate 20 with a partial thickness in sequence to form a first trench 211 in the substrate 20, where the first trench 211 encloses an active region a 2; then, as shown in fig. 4b and 4c, the substrate 20 of the active area a2 surrounded by the first trench 211, and the silicon nitride layer 202 and the pad oxide layer 201 above the substrate 20 are etched to form a second trench 221 and at least one third trench 23, the depth of the second trench 221 is the same as that of the third trench 23, the depths of the second trench 221 and the third trench 23 are smaller than that of the first trench 211, and the depths of the second trench 221 and the third trench 23 in the substrate 20 may be equal to that of the third trench 23
Figure BDA0002824143420000121
The depth of the first trench 211 in the substrate 20 may be
Figure BDA0002824143420000122
Or, first, a first trench 211 and a second trench 221 are simultaneously formed in the substrate 20, and then at least one third trench 23 is formed in the substrate 20, the first trench 211, the second trench 221 and the third trench 23 are also formed by photolithography and etching, the depth of the second trench 221 is the same as the depth of the first trench 211, the depth of the third trench 23 is smaller than the depths of the first trench 211 and the second trench 221, and the depth of the third trench 23 in the substrate 20 may be the same as the depth of the first trench 211
Figure BDA0002824143420000123
The first trench 211 and the second trench 221 in the substrate 20 may have a depth of
Figure BDA0002824143420000124
If the depth of the second groove 221 is the same as that of the third groove 23 and the depths of the second groove 221 and the third groove 23 are less than that of the first groove 211, the entire sidewall of the third groove 23 close to one side of the second groove 221 is communicated with the second groove 221 (as shown in fig. 4 c), and two ends of the second groove 221 are communicated with the top of the sidewall of the first groove 211; if the depth of the second groove 221 is the same as the depth of the first groove 211 and the depth of the third groove 23 is smaller than the depths of the first groove 211 and the second groove 221, one side of the third groove 23 close to the second groove 221 is communicated with the top of the sidewall of the second groove 221, and the entire sidewall of both ends of the second groove 221 is communicated with the first groove 211.
The method of manufacturing the semiconductor device may include forming at least two of the third trenches 23 in the substrate 20 of the active region a2, all of the third trenches 23 being sequentially arranged along an edge direction parallel to the one side of the second trench 221.
In step S3, a first trench filling structure 21 is formed in the first trench 211 and a second trench filling structure 22 is formed in the second trench 221. The first trench filling structure 21 and the second trench filling structure 22 both function as an isolation. The method comprises the following steps:
firstly, forming an insulating medium layer 203 to be filled in the first trench 211, the second trench 221 and the third trench 23, wherein the insulating medium layer 203 buries the silicon nitride layer 202 inside; then, planarizing the insulating dielectric layer 203 by using a chemical mechanical polishing process until the top surface of the silicon nitride layer 202 is exposed, as shown in fig. 4d and 4e, the insulating dielectric layer 203 in the first trench 211 is connected to the insulating dielectric layer 203 in the second trench 221; then, removing the silicon nitride layer 202 and the pad oxide layer 201, as shown in fig. 4f and 4g, the top surface of the remaining insulating medium layer 203 is higher than the top surface of the substrate 20; next, removing the insulating dielectric layer 203 in the third trench 23 by dry etching or wet etching to form a first trench filling structure 21 in the first trench 211 and a second trench filling structure 22 in the second trench 221, as shown in fig. 4h and 4i, for convenience of distinguishing, the first trench filling structure 21 and the second trench filling structure 22 are filled with a filling pattern different from that of the insulating dielectric layer 203.
The top surfaces of the first trench filling structure 21 and the second trench filling structure 22 may be flush with the top surface of the substrate 20, or the top surfaces of the first trench filling structure 21 and the second trench filling structure 22 may be higher than the top surface of the substrate 20 (as shown in fig. 4h and 4 i).
According to step S4, a gate dielectric layer 24 is formed on the inner wall of the third trench 23 and the substrate 20 at the periphery of the third trench 23, as shown in fig. 4j and 4 k. The gate dielectric layer 24 may be formed using a deposition or thermal oxidation process. One side of the gate dielectric layer 24 close to the second trench 221 is in contact with the second trench filling structure 22 (as shown in fig. 2d and 2 e), and both ends of the gate dielectric layer 24 in the edge direction parallel to the one side of the second trench 221 are in contact with the first trench filling structure 21 (as shown in fig. 4 j).
According to step S5, a gate layer 25 is formed on the gate dielectric layer 24 and on a portion of the second trench filling structure 22 close to the third trench 23, as shown in fig. 4l, fig. 2d and fig. 2 e. And, as shown in fig. 4l and 4m, both ends of the gate layer 25 (i.e., both ends in the edge direction parallel to the one side of the second trench 221) extend from the gate dielectric layer 24 and a portion of the second trench filling structure 22 close to the third trench 23 onto the first trench filling structure 21. Conventional deposition, photolithography and etching processes may be used to form the gate layer 25.
The second trench filling structure 22 is a field oxide layer of the semiconductor device, a portion of the gate layer 25 above the layout-defined channel region forms a gate region of the semiconductor device, and a portion extending to the second trench filling structure 22 forms a field plate.
Wherein the gate layer 25 may cover all of the third trenches 23, that is, an end of the third trench 23 facing away from the second trench 221 does not exceed an end of the gate layer 25 facing away from the second trench 221, as shown in fig. 2 a; alternatively, the gate layer 25 may cover only a part of the third trench 23, i.e. the end of the third trench 23 facing away from the second trench 221 may extend beyond the end of the gate layer 25 facing away from the second trench 221, as shown in fig. 2 f.
In addition, after forming the first trench 211, the second trench 221 and the at least one third trench 23 in the substrate 20 and before forming the first trench filling structure 21 in the first trench 211 and forming the second trench filling structure 22 in the second trench 221, the method for manufacturing a semiconductor device further includes forming a body region 26 and a drift region 27 in the substrate 20 of the active region a 2. Alternatively, the body region 26 and the drift region 27 may be formed before the first trench 211 is formed.
As shown in fig. 2d and fig. 2e, the boundary between the body region 26 and the drift region 27 is located below the gate layer 25, the drift region 27 surrounds the second trench 221, and the third trench 23 extends from the drift region 27 to the body region 26.
In addition, after the gate layer 25 is formed, the method for manufacturing the semiconductor device further includes forming a source region 261 and a drain region 271, the source region 261 is located in the body region 26 of the gate layer 25 away from the second trench filling structure 22, and the drain region 271 is located in the drift region 27 of the second trench filling structure 22 on the side facing away from the source region 261. Simultaneously with the formation of the source region 261 and the drain region 271, a body contact region 262 may be formed in the body region 26, the body contact region 262 being located in the body region 26 of the source region 261 on a side facing away from the gate layer 25, and a first trench filling structure 21 being further spaced between the body contact region 262 and the source region 261.
As shown in fig. 2a and 2f, the method of fabricating the semiconductor device further includes forming a conductive contact plug 28 on the source region 261, the drain region 271, the body contact region 262 and the gate layer 25, wherein the conductive contact plug 28 on the gate layer 25 is located above the first trench filling structure 21; and as shown in fig. 2f and 2g, an end of the third trench 23 facing away from the second trench 221 may extend onto the source region 261, and a bottom of the conductive contact plug 28 contacts the source region 261 under the third trench 23.
In addition, the length of all the third trenches 23 in the edge direction perpendicular to the one side of the second trench 221 (i.e., perpendicular to the second trench filling structure 22) is greater than the length in the edge direction parallel to the one side of the second trench 221 (i.e., perpendicular to the second trench filling structure 22), so that the width of the layout-defined channel region increases by a greater extent than the length of the channel region. Since the portion between the source region 261 and the drain region 271, which is located below the gate dielectric layer 24, is a channel region, and the direction between the source region 261 and the drain region 271 is the length direction of the channel region, the length direction of the channel region is the direction perpendicular to the edge of the one side of the second trench filling structure 22, and the width direction of the channel region is the direction parallel to the edge of the one side of the second trench filling structure 22, then, the length of all the third trenches 23 in the length direction of the channel region is greater than the length in the width direction of the channel region. For specific reference, the description of the semiconductor device is omitted here.
As can be seen from the above steps, at least one third trench 23 is formed on one side of the second trench filling structure 22, and the at least one third trench 23 extends from the drift region 27 to the body region 26, so that the width of the effective channel region is increased without changing the width of the layout, for example, the portion of the body region 26 located below the gate layer 25 is the effective channel region, the width of the effective channel region is increased by 50% to 100%, the number of carriers in channel inversion is increased by 50% to 100%, and further, the on-resistance is greatly reduced while the breakdown voltage is not reduced.
And, if the depth of the second trench 221 is the same as the depth of the third trench 23 and both are smaller than the depth of the first trench 211, the thickness of the second trench filling structure 22 in the substrate 20 is reduced, so that the on-resistance is further reduced.
In addition, the steps in the method for manufacturing a semiconductor device are not limited to the above formation order, and the order of the steps can be adaptively adjusted.
In summary, the method for manufacturing a semiconductor device provided by the present invention includes: providing a substrate; forming a first trench, a second trench and at least one third trench in the substrate, wherein the first trench encloses an active region in the substrate, the second trench is formed in the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, and the depth of the third trench is smaller than that of the first trench; forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench; forming a gate dielectric layer on the inner wall of the third groove and the substrate on the periphery of the third groove; and forming a gate layer on the gate dielectric layer and a part of the second trench filling structure close to the third trench. The manufacturing method of the semiconductor device can reduce the on-resistance without reducing the breakdown voltage.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (15)

1. A semiconductor device, comprising:
the device comprises a substrate, wherein an active region surrounded by a first groove filling structure is formed in the substrate;
a second trench filling structure and at least one third trench located at one side of the second trench filling structure, formed in the substrate of the active region, wherein the bottom wall of the third trench is higher than the bottom surface of the first trench filling structure, and the length of all the third trenches in the edge direction perpendicular to the one side of the second trench filling structure is greater than the length in the edge direction parallel to the one side of the second trench filling structure;
the gate dielectric layer is formed on the inner wall of the third groove and the substrate on the periphery of the third groove; and the number of the first and second groups,
the grid layer is formed on the grid dielectric layer and on a part of the second groove filling structure close to the third groove, and one end of the third groove, which is back to the second groove filling structure, exceeds one end of the grid layer, which is back to the second groove filling structure.
2. The semiconductor device of claim 1, wherein a side of the third trench proximate to the second trench fill structure exposes the second trench fill structure.
3. The semiconductor device of claim 1, wherein the semiconductor device includes at least two third trenches, all of the third trenches being sequentially arranged along an edge direction parallel to the one side of the second trench filling structure.
4. The semiconductor device of claim 1, wherein a bottom surface of the second trench fill structure is flush with a bottom surface of the first trench fill structure; or the bottom surface of the second trench filling structure is flush with the bottom wall of the third trench.
5. The semiconductor device of claim 1, wherein both ends of the second trench fill structure are in contact with sidewalls of the first trench fill structure; and two ends of the grid layer extend to the first groove filling structure from the upper part of the grid dielectric layer and the part of the second groove filling structure close to the third groove.
6. The semiconductor device of claim 1, further comprising a body region and a drift region formed in the substrate of the active region, an interface of the body region and the drift region being located below the gate layer, and the drift region surrounding the second trench fill structure, the third trench extending from the drift region to the body region.
7. The semiconductor device of claim 6, further comprising a source region in the body region of the gate layer distal from the second trench fill structure and a drain region in a drift region of the second trench fill structure on a side facing away from the source region.
8. The semiconductor device of claim 7, wherein an end of the third trench facing away from the second trench fill structure extends onto the source region.
9. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first trench, a second trench and at least one third trench in the substrate, wherein the first trench surrounds an active region in the substrate, the second trench is formed in the substrate of the active region, the at least one third trench is formed in the substrate of the active region on one side of the second trench, the depth of the third trench is smaller than that of the first trench, and the length of all the third trenches in the direction perpendicular to the edge of the one side of the second trench is greater than that in the direction parallel to the edge of the one side of the second trench;
forming a first trench filling structure in the first trench and forming a second trench filling structure in the second trench;
forming a gate dielectric layer on the inner wall of the third groove and the substrate on the periphery of the third groove; and the number of the first and second groups,
and forming a gate layer on the gate dielectric layer and on a part of the second trench filling structure close to the third trench, wherein one end of the third trench, which is back to the second trench filling structure, exceeds one end of the gate layer, which is back to the second trench filling structure.
10. The method for manufacturing a semiconductor device according to claim 9, wherein a side of the third trench close to the second trench communicates with the second trench.
11. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the first trench, the second trench, and the at least one third trench in the substrate comprises:
forming a first groove in the substrate, and simultaneously forming a second groove and at least one third groove in the substrate, wherein the depth of the second groove is the same as that of the third groove;
or, a first trench and a second trench are simultaneously formed in the substrate, and then at least one third trench is formed in the substrate, wherein the depth of the second trench is the same as that of the first trench.
12. The method of manufacturing a semiconductor device according to claim 9, wherein the step of forming the first trench fill structure in the first trench and the step of forming the second trench fill structure in the second trench comprises:
forming an insulating medium layer to be filled in the first groove, the second groove and the third groove; and (c) a second step of,
and removing the insulating medium layer in the third groove to form a first groove filling structure in the first groove and a second groove filling structure in the second groove.
13. The method for manufacturing a semiconductor device according to claim 9, wherein both ends of the second trench communicate with sidewalls of the first trench; and two ends of the grid layer extend to the first groove filling structure from the upper part of the grid dielectric layer and the part of the second groove filling structure close to the third groove.
14. The method for manufacturing a semiconductor device according to claim 9, further comprising forming a body region and a drift region in the substrate of the active region; the junction of the body region and the drift region is located below the gate layer, the drift region surrounds the second trench, and the third trench extends from the drift region to the body region.
15. The method of manufacturing the semiconductor device according to claim 14, further comprising forming a source region and a drain region, wherein the source region is located in a body region of the gate layer away from the second trench filling structure, and the drain region is located in a drift region of a side of the second trench filling structure facing away from the source region.
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