CN112490275A - Display panel, manufacturing method thereof and display device - Google Patents
Display panel, manufacturing method thereof and display device Download PDFInfo
- Publication number
- CN112490275A CN112490275A CN202011394874.1A CN202011394874A CN112490275A CN 112490275 A CN112490275 A CN 112490275A CN 202011394874 A CN202011394874 A CN 202011394874A CN 112490275 A CN112490275 A CN 112490275A
- Authority
- CN
- China
- Prior art keywords
- substrate
- layer
- thin film
- film transistor
- display panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application provides a display panel and a manufacturing method thereof, and a display device, the display panel comprises a substrate and an oxide thin film transistor positioned on the substrate, wherein a grid electrode of the oxide thin film transistor is positioned on one side of an oxide channel of the oxide thin film transistor, which is deviated from the substrate, and comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is closer to the substrate relative to the second surface, the second surface is larger than and covers the first surface, and the second surface is used for shielding ion implantation, so that the boundary of the ion implantation diffusion reaches the side edge of the first surface, and the ion diffusion degree is realized, the deviation of the finally obtained process value and the design value of the effective channel length is smaller, the deviation between the actual effective channel length and the design value caused by the process is reduced, and the characteristics and the uniformity of a device are further ensured.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a manufacturing method of the display panel and a display device.
Background
The flexible and foldable display device has a wide market prospect due to the love of consumers as a necessary trend of the development of an Organic Light-Emitting Diode (OLED) device.
At present, Poly-Si (polysilicon) manufactured by LTPS (Low Temperature polysilicon, also referred to as p-Si for short) process is used as a semiconductor for a driving back plate of an OLED. However, the leakage current of Poly-Si is large, which inevitably increases the power consumption of the display device. The thin film transistor (LTPO (Low Temperature Polycrystalline Oxide) technology for short) of the OLED display device is manufactured by using an Oxide such as IGZO (indium gallium zinc Oxide) or ZnO (zinc Oxide) as an active layer instead of part of Poly-Si, and the possibility of electric leakage of the display device during display is reduced by using the advantage of Low leakage current of the Oxide.
However, in the manufacturing process of the thin film transistor using the oxide as the active layer, process variations cause poor device characteristics.
Disclosure of Invention
In view of the above, the present invention provides a display panel, a manufacturing method thereof, and a display device, so as to solve the problem of poor device characteristics caused by process deviation in the manufacturing process of a thin film transistor using an oxide as an active layer in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme:
a display panel, comprising: the transistor comprises a substrate and an oxide thin film transistor arranged on the substrate;
the oxide thin film transistor comprises an oxide channel and a grid electrode positioned on the side, facing away from the substrate, of the oxide channel;
the grid electrode comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is a surface close to the oxide channel, and the second surface is a surface away from the oxide channel;
wherein a projection of the first surface on the substrate is located inside a projection of the second surface on the substrate, and a projected area of the first surface on the substrate is smaller than a projected area of the second surface on the substrate.
The invention also comprises a display device comprising the display panel described above.
In addition, the invention also comprises a manufacturing method of the display panel, which comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an oxide thin film transistor arranged on one side of the substrate, the oxide thin film transistor comprises an oxide channel and a grid electrode positioned on one side, facing away from the substrate, of the oxide channel, and the grid electrode comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is a surface close to the oxide channel, and the second surface is a surface facing away from the oxide channel; the projection of the first surface on the substrate is located inside the projection of the second surface on the substrate, and the area of the projection of the first surface on the substrate is smaller than the area of the projection of the second surface on the substrate;
and conducting treatment is carried out on the oxide channel by taking the grid electrode as a blocking layer.
As can be seen from the foregoing technical solutions, the display panel provided by the present invention includes a substrate and an oxide thin film transistor located on the substrate, wherein a gate of the oxide thin film transistor is located on a side of an oxide channel of the oxide thin film transistor, which is away from the substrate, and the gate includes two surfaces that are oppositely disposed, wherein an area of a surface of the gate, which is away from the substrate, is larger than an area of a surface of the gate, which is towards the substrate, and an orthographic projection of the surface of the gate, which is away from the substrate, on the substrate includes an orthographic projection of the surface of the gate, which is towards the substrate, on the substrate, that is, in a top view, the surface of the gate, which is towards the substrate, is completely located in the surface of the gate, which is away from the substrate, and the surface of the gate, which is away, the surface of the grid electrode, which is far away from the substrate, can play a role in shielding, so that the channel region of the conductive oxide thin film transistor is avoided, the length of the channel region is ensured, the actual manufacturing parameters of the device are equivalent to the design parameters, the deviation between the channel length and the design value caused by the process is reduced, and the characteristics and the uniformity of the device are further ensured.
The invention also provides a manufacturing method of the display panel, and a device with small deviation from a design value can be obtained by the manufacturing method, so that the device characteristic and uniformity are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a display panel according to the related art;
FIG. 2 is an enlarged view of a portion I of FIG. 1;
fig. 3 is a schematic view of ion implantation provided in the prior art;
fig. 4 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic view of a gate structure formed by a simple material according to the present embodiment;
fig. 7 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;
fig. 8 is a schematic cross-sectional view of a display panel according to an embodiment of the invention;
fig. 9 is a schematic view of a partial ion implantation corresponding to part II in fig. 8;
FIG. 10 is a schematic cross-sectional view of another display panel according to an embodiment of the present invention;
fig. 11 is a schematic top view of a display panel according to an embodiment of the present invention;
fig. 12 is a schematic diagram of gate structures of a first oxide thin film transistor and a second oxide thin film transistor, which both include a first portion and a second portion, according to an embodiment of the present invention;
fig. 13 is a schematic diagram of gate structures of a first oxide thin film transistor and a second oxide thin film transistor having smooth sidewalls according to an embodiment of the present invention;
fig. 14 is a flowchart of a method for manufacturing a display panel according to an embodiment of the invention;
fig. 15-17 are schematic views illustrating a gate fabrication process according to the present invention;
FIGS. 18-21 are schematic views of another gate fabrication process provided by the present invention;
fig. 22 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
As described in the background section, in the related art, in the manufacturing process of the thin film transistor using an oxide as an active layer, the device characteristics are poor due to process variations.
The inventor finds that the root cause of the above phenomenon is that the display panel structure in the related art is schematically shown in fig. 1. The display panel includes an oxide thin film transistor 01, and a gate 011 of the oxide thin film transistor 01 is located over a channel region. After the gate structure is manufactured in the related art, the interlayer dielectric layer 012 needs to be used for covering, in order to make the interlayer dielectric layer 012 cover the gate well, the gate in the related art is configured to have a structure with a taper angle, where the upper surface is smaller than the lower surface, as shown in fig. 2, which is a partial enlarged view of a portion I in fig. 1, and in order to ensure a covering effect of the interlayer dielectric layer 012 on the gate, the taper angle α is usually smaller than 45 °; however, in the process of performing ion implantation on both sides of the channel region to form the conductive source/drain regions, the ion implantation causes lateral diffusion, so that both sides of the channel region are also made conductive, and further the channel length is shortened, as shown in fig. 3.
Moreover, since the gate thickness and taper angle cannot be strictly controlled in the process design parameters, the diffusion degree cannot be predicted, and in the manner of the related art, even if the bottom surface of the gate is enlarged to block the ion implantation, it cannot be determined how large the area of the gate is enlarged to enable the channel length to be exactly the same as the designed value or have a small deviation after the ion implantation diffusion.
Accordingly, the present invention provides a display panel comprising: the transistor comprises a substrate and an oxide thin film transistor arranged on the substrate;
the oxide thin film transistor comprises an oxide channel and a grid electrode positioned on the side, facing away from the substrate, of the oxide channel;
the grid electrode comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is a surface close to the oxide channel, and the second surface is a surface away from the oxide channel;
wherein a projection of the first surface on the substrate is located inside a projection of the second surface on the substrate, and a projected area of the first surface on the substrate is smaller than a projected area of the second surface on the substrate.
According to the invention, the shape of the grid electrode is improved to be that the second surface is larger than the first surface, the first surface is set as a design value of the effective channel length, the second surface is used for shielding ion implantation, so that the boundary of the ion implantation diffusion reaches the side edge of the first surface, the ion diffusion degree is realized, the deviation of the process value and the design value of the finally obtained effective channel length is smaller, the deviation between the actual effective channel length and the design value caused by the process is reduced, and the characteristics and the uniformity of the device are further ensured.
Furthermore, the interlayer dielectric layer positioned above the grid is formed by adopting an atomic layer deposition method, so that the interlayer dielectric layer can better cover the grid.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 4, fig. 4 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention, where the display panel includes a substrate 10 and an oxide thin film transistor 20 disposed on the substrate 10; the oxide thin film transistor 20 includes an oxide channel 201 and a gate 202 on a side of the oxide channel 201 facing away from the substrate; the gate 202 includes a first surface 200A and a second surface 202B disposed opposite to each other, wherein the first surface 202A is a surface close to the oxide channel 201, and the second surface 202B is a surface away from the oxide channel 201; wherein the projection of the first surface 202A on the substrate is located inside the projection of the second surface 202B on the substrate, and the projection area of the first surface 202A on the substrate is smaller than the projection area of the second surface 202B on the substrate.
In this embodiment, in a manufacturing process of the oxide thin film transistor, the gate is located on a side of the oxide channel away from the substrate, and the gate is used as a mask plate to perform ion doping on the oxide active layer by using an ion implantation process (IMP, implantation) to form a source region and a drain region.
The grid electrode is made of a metal layer MD, and an interlayer dielectric layer 30 is formed on the grid electrode; optionally, the gate 202 is electrically led out through any one metal layer Mx located on the interlayer dielectric layer 30; the source region S and the drain region D are connected to the metal layer M2 through metal vias, respectively. It should be noted that, in the embodiments of the present invention, the gates that are not specifically described are all gates of an oxide thin film transistor, and other gates are mentioned later and will be described separately.
In the embodiment of the present invention, the shape of the gate 202 is larger than the area of the second surface 202B far away from the substrate than the area of the first surface 202A facing the substrate, and the projection of the first surface 202A on the substrate 10 is located inside the projection of the second surface 202B on the substrate 10, that is, as shown in fig. 4, the shape of the gate 202 is a shape with a larger top and a smaller bottom, and it should be noted that, when the gate 202 is used as a mask plate in an ion implantation process, in the sectional view shown in fig. 4, since the middle portion 202C of the gate 202 has a larger thickness and has a shielding effect on ions during the ion implantation process, and the edge 202D has a smaller thickness, when the ions are implanted, there is ion diffusion at the edge portion of the gate, but due to the shielding effect of the middle portion, the ion diffusion also diffuses to the edge of the lower surface of the gate, i.e. where the edge of the first surface is the boundary. So that the edges of the source and drain regions formed by ion diffusion are flush with the edge of the first surface, so that the effective channel length is the same as the size of the first surface.
By adopting the grid provided by the embodiment of the invention, the effective channel length of the oxide thin film transistor can be accurately controlled, and the problem that the device characteristics of the finally obtained oxide thin film transistor are poorer due to the fact that the effective channel length obtained by an actual process is shortened relative to a design value because the side of the channel is subjected to conduction caused by ion diffusion is avoided.
It should be noted that the first surface 202A is smaller than the second surface 202B, and the second surface 202B covers the first surface 202A to achieve the above-mentioned purpose, so the shape of the first surface 202A and the shape of the second surface 202B are not limited in this embodiment, and the distance between the edges of the two is not limited. In order to make the process control simpler and to make the effective channel length of the formed oxide thin film transistor easy to control, optionally, the shape of the first surface 202A and the shape of the second surface 202B may be the same, further, the orthographic projection of the first surface 202A on the substrate is a first projection, the orthographic projection of the second surface 202B on the substrate is a second projection, and the geometric center of the first projection coincides with the geometric center of the second projection. In this embodiment, the first surface and the second surface have the same shape, and the geometric centers of the first projection and the second projection are coincident, so that distances from the edge of the first projection to the edge of the second projection in a plurality of positions of the gate projection are the same, that is, distances from the effective channel region to the source region and the drain region are the same, and in the ion implantation process, the ion implantation concentration from the effective channel region to the source region or the drain region is gradually changed, and the shape of the first projection edge is used as a ring to perform gradual change by taking the geometric center as a center.
The distance from the edge of the first projection to the edge of the second projection is D1, wherein D1 is 0.25 μm or less and 0.5 μm or less. Under the condition that the thickness of the grid electrode is not changed, if D1 is too small, the shielding capability of the second surface of the grid electrode on ion implantation is more limited, and the influence on ion diffusion is smaller, so that the ion implantation occurs in a channel region, and the length of an effective channel region is reduced; when D1 is too large, the second surface of the gate protrudes more than the first surface, which makes the climbing of the subsequent interlayer dielectric layer difficult and increases the difficulty of the manufacturing process.
In the embodiment of the present invention, the specific shape and material of the gate are not limited, and optionally, as shown in fig. 4, the gate has a smooth sidewall 202E, and an included angle is formed between the sidewall 202E and the first surface 202A, that is, when the first surface and the second surface are circular, the three-dimensional shape of the gate is a truncated cone shape with a large upper surface and a small lower surface; when the first surface and the second surface are rectangular, the three-dimensional shape of the gate is a square platform with a large upper surface and a small lower surface, and the side wall is a smooth surface inclined relative to the first surface.
Fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention. The dotted line portion is the oxide thin film transistor structure provided in the embodiments of the present invention. The substrate 10 of the display panel sequentially comprises a first flexible substrate (PI1)101, a first Barrier Layer (Barrier1)102, a second flexible substrate (PI2)103, a second Barrier Layer (Barrier2) or a Buffer Layer (Buffer)104, a first insulating Layer (GI1, Gate insulator)105, (IMD) a first interlayer Dielectric Layer (ILD1, Inter Layer Dielectric) a second insulating Layer (GI2) and a third insulating Layer (GI3)109 from bottom to top; the display panel further includes a low temperature polysilicon tft in the substrate 10, as shown in fig. 5, which has a structure formed by the first metal layer M1 and the polysilicon layer Poly, and has source and drain regions similar to those of the oxide tft, and is electrically connected to an external circuit through the second metal layer M2, and the gate is formed by the first metal layer M1 and is electrically connected to the external circuit through other metal vias and metal layers, which are not shown in the figure. Also included in substrate 10 are other metal layers, such as MC, which form a capacitor with first metal layer M1 and may serve as a storage capacitor.
The gate of the oxide thin film transistor is further covered with a second interlayer dielectric layer ILD2, a first planarizing layer PLN1, a second planarizing layer PLN2, a third metal layer M3 on the first planarizing layer PLN1, and other structures. The display panel may be an OLED display panel and, therefore, further includes a pixel defining layer PDL, and spacer posts PS on the pixel defining layer, and anodes RE between the pixel defining layers. In the embodiment of the present invention, the display panel may further include other structures, which are not described in detail in this embodiment.
In addition to the shape of the gate electrode, the gate electrode may be made of a single material or may have a multilayer structure made of a plurality of materials. When the gate material is a single material, it is optional, and the gate material is Al, as shown in fig. 6, which is a schematic diagram of a gate structure formed by a single material provided in this embodiment; when the gate material is a multi-layer structure formed by multiple materials, as shown in fig. 7, fig. 7 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention; the gate electrode in this embodiment includes a first layer 2021, a second layer 2022, and a third layer 2023 which are stacked; wherein the first layer 2021 and the third layer 2023 are both made of Ti; the second layer is made of Al.
It should be noted that, in the process of manufacturing a gate with a smooth sidewall, a photoresist may be formed first, the photoresist is etched to form a through hole, the shape of the through hole is the same as that of the gate to be formed, then the through hole is filled by a metal deposition process, and when the gate is made of Al, metal aluminum is directly deposited in the through hole; when the gate includes the first layer, the second layer, and the third layer, a Ti layer, an Al layer, and a Ti layer may be sequentially formed in the via hole, and finally, a gate structure of a three-layer structure may be formed.
In addition, in other embodiments of the present invention, the gate may have other shapes, as shown in fig. 8 and fig. 9, where fig. 8 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention; fig. 9 is a schematic view of a partial ion implantation corresponding to part II in fig. 8; the gate includes a first portion 2024 and a second portion 2025 which are arranged in a stacked manner in a direction away from the substrate; wherein the shape of the first portion 2024 is the same as the shape of the projection of the first surface on the substrate in a plane parallel to the substrate surface; the shape of the second portion 2025 is the same as the shape of the projection of the second surface on the substrate, and it should be noted that the shape of the first surface and the shape of the second surface may be the same or different in this embodiment. For example, if the first surface and the second surface are both circular, the first portion is cylindrical and the second portion is also cylindrical; the first surface is circular, and when the second surface is rectangular, the first portion is cylindrical and the second portion is cubic. This is not limited in this embodiment.
In addition, in this embodiment, the materials of the first portion and the second portion may be the same or different. When the first part and the second part are made of the same material, the grid electrode with the different shapes of the first part and the second part can be manufactured and formed in a mode of forming a groove by adopting photoresist. When the first part and the second part are made of different materials, the first part is made of Al, the second part is made of Ti, and the etching rate of Al is greater than that of Ti in the wet etching process of Al and Ti, so that an Al layer can be manufactured firstly, and then a Ti layer is manufactured on the Al layer when the grid electrode in the shape is manufactured; and etching the Al layer and the Ti layer by a wet etching process, wherein the etching rate of Ti is smaller than that of the Al layer, so that a grid electrode with the area of the second part positioned above being larger than that of the first part positioned below is finally formed.
It should be noted that, in order to isolate the gate from other conductive layers formed thereon, an interlayer dielectric layer is further included above the gate, referring to fig. 5 and 8, the interlayer dielectric layer ILD2 is located on a side of the gate 202 away from the substrate 10, the interlayer dielectric layer ILD2 covers the gate 202, the interlayer dielectric layer ILD2 is a metal oxide, and the interlayer dielectric layer ILD2 covers the sidewall 202E of the gate 202. In the embodiment, the interlayer dielectric layer is formed by adopting an atomic deposition (ALD) method, so that the surface and the side wall of the gate, which are away from the substrate, can be completely covered, and the thicknesses of the interlayer dielectric layer covered on the second surface and the side wall of the gate are the same, thereby ensuring the insulation effect.
Atomic Layer Deposition (ALD) is a thin film deposition technique based on surface vapor phase chemical reactions. Also known as Atomic Layer Epitaxy (ALE) techniques. The top technique of ALD film deposition, as a surface-controlled, self-limiting chemical vapor treatment process, ALD can ensure 100% uniformity, conformality, defect-free, pinhole-free film growth.
Because the ALD process has the characteristics of good compactness, good climbing performance, good water and oxygen blocking performance and good flexibility, the thickness range of the interlayer dielectric layer in the embodiment can be selected from 10nm to 100nm, including end points, so that the thickness of the interlayer dielectric layer can be reduced relative to the interlayer dielectric layers formed by other processes, and further the whole thickness of the display panel can be further reduced.
Fig. 10 is a schematic cross-sectional view of another display panel according to an embodiment of the invention. Referring to fig. 10, in the embodiment of the present invention, the display panel further includes a low temperature polysilicon thin film transistor (a structure formed by a first metal layer M1 and polysilicon Poly) and a metal pad layer 40, and a source drain of the oxide thin film transistor and a source drain of the low temperature polysilicon thin film transistor are disposed on the same layer and are both formed by a second metal layer M2; the metal cushion layer 40 is positioned on one side of the oxide thin film transistor, which is far away from the substrate; the display panel further comprises a capacitor metal layer 50, wherein the capacitor metal layer 50 and the grid electrode are formed by a metal layer MD at the same layer, and an interlayer dielectric layer ILD2 is positioned between the capacitor metal layer 50 and the metal cushion layer 40; in the direction perpendicular to the substrate, the capacitor metal layer 50 at least partially overlaps the metal pad layer 40.
By forming the overlap with the metal pad layer and forming the capacitor metal layer with the same layer and thickness as the gate layer while forming the gate, the capacitor formed between the capacitor metal layer 50 and the metal pad layer 40 can be used as a storage capacitor, thereby increasing the capacity of the storage capacitor. In addition, in this embodiment, an interlayer dielectric layer is further disposed between the metal capacitor layer and the metal pad layer, and since the interlayer dielectric layer is formed by using an ALD process and has a relatively large dielectric constant, the interlayer dielectric layer serves as a dielectric layer of a capacitor formed by the metal capacitor layer 50 and the metal pad layer 40, and the capacitance of the capacitor formed by the metal capacitor layer and the metal pad layer is further increased.
In this embodiment, the shape of the capacitor metal layer is not limited, and in order to simplify the manufacturing process, the optional capacitor metal layer and the gate in this embodiment are formed in the same step, and correspondingly, the shape of the capacitor metal layer 50 is the same as that of the gate 202, and since the surface of the capacitor metal layer 50 facing the metal pad layer 40 is a surface with a larger area, when the capacitor metal layer is aligned with the metal pad layer 40, the aligned area of the capacitor metal layer 50 and the metal pad layer 40 is increased, and furthermore, the thickness of the interlayer dielectric layer ILD2 in the embodiment of the present invention is thinner than that in the prior art, so that the distance between the capacitor metal layer 50 and the metal pad layer 40 is smaller, and according to the plate capacitance formula, C ∈ S0 ∈ S; in the formula: c is a capacitor; ε is the relative dielectric constant; ε 0 is the vacuum dielectric constant; s is the area of the two polar plates opposite to each other; d is the distance between the two polar plates; it can be seen that, by forming the capacitor metal layer 50 and the gate 202 in a manner of being large at the top and small at the bottom simultaneously and forming the interlayer dielectric layer ILD2 by using the ALD process, the facing area S of the plate capacitor can be increased, the inter-plate distance d can be reduced, and the capacitance of the capacitor formed by the capacitor metal layer 50 and the metal pad layer 40 can be increased.
It should be noted that, unlike the prior art, since the ILD2 is thinner in the present embodiment and the position of the second metal layer M2 is lower than the second surface of the gate 202, the gate in the present embodiment is not electrically connected to an external circuit through the second metal layer M2 as in the prior art. The gate 202 in this embodiment may be electrically connected to an external circuit through any one layer of metal (e.g., the metal layer Mx in fig. 4) located above the gate 202 as a terminal, which is not shown in the drawing, but actually, a metal layer may be added to make the terminal, or the terminal and any one layer of metal layer located above the gate 202 may be formed in the same step, for example, by using the third metal layer M3 for the terminal, which is not limited in this embodiment.
It should be noted that, as shown in fig. 11, which is a schematic view of a top view structure of a display panel provided in the embodiment of the present invention, the display panel further includes a binding region 60, the binding region 60 is located at one side of the display panel, and the binding region 60 is used for binding a driver chip; the lengths of the pixel power lines which are different from the binding area 60 are different on the display panel, so that the voltage drop on the power lines is different, and the compensation of the voltage drop on the power lines can be realized by adjusting the blocking capability of the grid electrode of the oxide thin film transistor in the ion implantation process in the embodiment, so that the display brightness of different areas of the display panel is uniform.
The oxide thin film transistor on the display panel includes a first oxide thin film transistor 21 and a second oxide thin film transistor 22, a minimum distance from the first oxide thin film transistor 21 to the strapping region is d1, a minimum distance from the second oxide transistor 22 to the strapping region is d2, and d2 > d 1; the resistance of the active layer of the first oxide thin film transistor is greater than the resistance of the active layer of the second oxide thin film transistor.
The minimum distance from the first oxide thin film transistor (second oxide thin film transistor) to the bonding region in this embodiment refers to a line length of the power line trace PVDD connecting the first oxide thin film transistor (second oxide thin film transistor) and the bonding region, not a spatial distance. Since d2 > d1, the length of the power line between the second oxide thin film transistor 22 and the strapping region 60 is larger than the length of the power line between the first oxide thin film transistor 21 and the strapping region 60. Under the condition of adopting the same cross-sectional area and the same material, the longer the power line length is, the larger the line resistance is, and the larger the voltage drop generated on the power line is; therefore, the voltage drop of the power line corresponding to the second oxide thin film transistor 22 is relatively large, and in order to compensate for the voltage drop, in this embodiment, it is optional to make the resistance of the active layer of the first oxide thin film transistor greater than the resistance of the active layer of the second oxide thin film transistor, that is, the on-resistance of the first oxide thin film transistor is greater than the on-resistance of the second oxide thin film transistor.
Due to the fact that the on-resistance of the first oxide thin film transistor is large, the voltage drop generated on the power line is small, the voltage drop corresponding to the first oxide thin film transistor is small, and the voltage drop generated on the first oxide thin film transistor compensates the voltage drop generated on the power line connected with the first oxide thin film transistor, so that the total voltage drops on the first oxide thin film transistor and the second oxide thin film transistor are equivalent, the total voltage drops generated at positions, different from the binding area, on the display panel are basically consistent, and the brightness of the display panel is uniform.
In this embodiment, the first oxide thin film transistor and the second oxide thin film transistor are not particularly limited to one oxide thin film transistor. Any two oxide thin film transistors having different minimum distances from the binding region may correspond to the first oxide thin film transistor and the second oxide thin film transistor described in this embodiment. That is, in the present embodiment, the resistance value of the active layer of the oxide thin film transistor is inversely related to the minimum distance of the oxide thin film transistor to the binding region.
In addition, the means for implementing different resistances of the active layers of different oxide thin film transistors is not limited in this embodiment, and alternatively, in an embodiment of the present invention, the means can be implemented by changing a distance between an edge of the second surface of the gate and an edge of the first surface. For example, in the case where the gate thicknesses of all the oxide thin film transistors are the same, the embodiment is described by taking a circular gate shape as an example, and as shown in fig. 12, the embodiment is a schematic diagram of a gate structure in which each of the first oxide thin film transistor and the second oxide thin film transistor includes a first portion and a second portion, where a distance from a forward projection of the second surface 21-202B of the gate of the first oxide thin film transistor to a forward projection of the first surface 21-202A of the first oxide thin film transistor on the substrate is D2; the distance D3 from the orthographic projection of the second surface 22-202B of the second oxide thin film transistor to the orthographic projection of the first surface 22-202A of the second oxide thin film transistor on the substrate; wherein D2 < D3. The second surface of the second oxide thin film transistor is large, so that the blocking of ion injection is obvious, the obtained effective channel length is large, the carrier mobility of the second oxide thin film transistor is large, the driving current is large, and the reduction of the driving current caused by the voltage drop of the power line can be compensated.
When the side wall of the gate is a smooth side wall, optionally, the on-resistance of different oxide thin film transistors is adjusted by changing an included angle (taper angle) between the side wall and the substrate. Similarly, in the case of the same gate thickness, the effective channel length of the second oxide thin film transistor is made longer, and therefore, as shown in fig. 13, the structure of the gate with smooth sidewalls of the first oxide thin film transistor and the second oxide thin film transistor is schematically illustrated, wherein the included angle between the sidewalls of the gates 21-202 of the first oxide thin film transistor and the substrate is a1, and the included angle between the sidewalls of the gates 22-202 of the second oxide thin film transistor and the substrate is a2, where a2 < a 1.
Because the included angle between the side wall of the grid electrode of the second oxide thin film transistor and the substrate is smaller, under the condition of the same grid electrode thickness, the grid electrode shielding capacity is relatively stronger, the obtained effective channel length is longer, and the carrier mobility and the driving current of the second oxide thin film transistor are larger and larger by the kiren, so that the reduction of the driving current caused by the voltage drop of a power line can be compensated.
According to the display panel provided by the embodiment of the invention, the shape of the grid can play a role of shielding in the ion implantation process, and the deviation between the finally obtained device structure parameter and the design value is smaller by setting the size of the first surface of the grid to be the same as the design length of the channel, so that the consistency of the performance, the process and the design of the device is ensured.
Based on the same inventive concept, please refer to fig. 14, fig. 14 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention, where the method for manufacturing a display panel includes:
s101: providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an oxide thin film transistor arranged on one side of the substrate, the oxide thin film transistor comprises an oxide channel and a grid electrode positioned on one side, away from the substrate, of the oxide channel, and the grid electrode comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is a surface close to the oxide channel, and the second surface is a surface away from the oxide channel; the projection of the first surface on the substrate is positioned inside the projection of the second surface on the substrate, and the area of the projection of the first surface on the substrate is smaller than that of the projection of the second surface on the substrate;
it should be noted that, in this embodiment, a specific structure of a semiconductor substrate is not limited, the semiconductor substrate is a structure including a substrate and a completed oxide thin film transistor already fabricated on the substrate, in other embodiments of the present invention, other devices, such as a low temperature polysilicon thin film transistor and a capacitor, may also be fabricated on the semiconductor substrate according to actual requirements, and this is not limited in this embodiment.
S102: conducting treatment is carried out on the oxide channel by taking the grid electrode as a blocking layer;
and conducting treatment on the oxide channel by using the grid electrode with the first surface area smaller than the second surface area as a mask plate or a blocking layer, so that a source electrode region and a drain electrode region are formed on the oxide channel or the part, which is not shielded, on the active layer, so as to form a source electrode and a drain electrode in the following process and electrically connect the source electrode and the drain electrode to the outside.
It should be noted that, in order to ensure insulation between the gate and the metal layer or the conductive structure formed subsequently, the present embodiment further includes a step of forming an interlayer dielectric layer on the gate, and since the shape of the gate is special, in order to ensure that the interlayer dielectric layer can completely cover the sidewall and the second surface of the gate, the interlayer dielectric layer is formed by using an atomic layer deposition method in the present embodiment, so that the interlayer dielectric layer can uniformly cover the sidewall and the second surface of the gate, and the thicknesses covered on the sidewall and the second surface of the gate are the same.
The interlayer dielectric layer is formed by adopting an atomic layer deposition method, and has better compactness and good insulation, so that the thickness of the interlayer dielectric layer can be made into a layer structure thinner than that of the prior art, and ions in an ion implantation process can penetrate through the thinner interlayer dielectric layer, so that the step of conducting treatment in the embodiment can be performed before the interlayer dielectric layer is manufactured or after the interlayer dielectric layer is manufactured and formed, and the embodiment is not limited.
In addition, it should be noted that, in this embodiment, the shape of the gate is improved over the prior art, the area of the first surface is smaller than that of the second surface, the shape of the gate may have a smooth sidewall, or may be a structure divided into an upper portion and a lower portion, and different processes may be adopted for forming different shapes.
For example, when the gate electrode includes a first portion and a second portion arranged in a stack in a direction away from the substrate; the shape of the first portion is the same as the shape of the projection of the first surface on the substrate in a plane parallel to the surface of the substrate; the shape of the second portion is the same as the shape of the projection of the second surface on the substrate. Referring to fig. 15-17, a schematic diagram of a gate manufacturing process according to the present invention is illustrated, in this embodiment, by taking as an example that other structures of an oxide thin film transistor have been completed on a semiconductor substrate, a method for manufacturing a gate includes:
forming a first partial layer structure, referring to fig. 15, a first partial layer structure 2024A is formed on the semiconductor substrate 110;
forming a second partial layer structure on the first partial layer structure, as shown in fig. 16, forming a whole second partial layer structure 2025A on the first partial layer structure 2024A;
and etching the first part layer structure and the second part layer structure by adopting an etching process, wherein the etching rate of the first part layer structure is greater than that of the second part layer structure to form a first part and a second part, as shown in fig. 17, because the etching rates of the first part layer and the second part layer are different, the two parts are etched by the etching process to obtain different areas, and finally two structures with different areas, namely a first part 2024 and a second part 2025 are formed. In this embodiment, the material of the first partial layer may be Al, and the material of the second partial layer may be Ti.
When the grid electrode has a smooth side wall and an included angle is formed between the side wall and the first surface; referring to fig. 18-21, another schematic diagram of a gate manufacturing process provided by the present invention is illustrated, in this embodiment, by taking as an example that other structures of an oxide thin film transistor have been completed on a semiconductor substrate, a method for manufacturing a gate includes:
forming an organic layer, referring to fig. 18, an organic layer 70 is formed on the semiconductor substrate 110;
forming a through hole on the organic layer, wherein the area of the opening of the through hole, which is away from the substrate, is larger than the area of the opening of the through hole, which is toward the substrate, please refer to fig. 19, forming an inverted trapezoidal through hole 80 on the organic layer 70 at a position where a gate is to be formed by an etching process, wherein the through hole 80 penetrates through the organic layer 70;
the gate with smooth sidewalls is formed by filling the via with metal, see fig. 20, and the gate 202 is formed by filling the via 80 with metal.
Finally, the excess organic layer is removed, and the metal in the through hole is retained to form a gate, as shown in fig. 21. That is, in this embodiment, the shape of the gate to be fabricated is formed by the organic layer, and then the gate is formed by metal filling.
According to the display panel manufactured by the method, the length of the channel can be better controlled due to the shape of the grid electrode, so that the effective channel length of the device manufactured by the process is equivalent to a design value, the deviation is small, and the performance of the device is guaranteed.
In addition, the interlayer dielectric layer is formed by the atomic layer deposition method, the grid electrode can be well covered, water and oxygen can be blocked, the metal layer arranged on the same layer with the grid electrode can be added, and the capacitance can be formed between the interlayer dielectric layer and other metal layers and used as a storage capacitor to increase the capacity of the storage capacitor.
Fig. 22 is a schematic structural diagram of a display device according to an embodiment of the present invention, and the display device 100 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
Due to the adoption of the manufacturing of the display panel in the embodiment, the deviation of the final process production value and the design value of the oxide thin film transistor is small, the device performance is good, and the display uniformity can be correspondingly improved.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (23)
1. A display panel, comprising: the transistor comprises a substrate and an oxide thin film transistor arranged on the substrate;
the oxide thin film transistor comprises an oxide channel and a grid electrode positioned on the side, facing away from the substrate, of the oxide channel;
the grid electrode comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is a surface close to the oxide channel, and the second surface is a surface away from the oxide channel;
wherein a projection of the first surface on the substrate is located inside a projection of the second surface on the substrate, and a projected area of the first surface on the substrate is smaller than a projected area of the second surface on the substrate.
2. The display panel according to claim 1, wherein the first surface and the second surface have the same shape.
3. The display panel of claim 2, wherein the orthographic projection of the first surface on the substrate is a first projection, the orthographic projection of the second surface on the substrate is a second projection, and a geometric center of the first projection coincides with a geometric center of the second projection.
4. The display panel of claim 3, wherein the distance from the edge of the first projection to the edge of the second projection is D1, wherein 0.25 μm D1 μm 0.5 μm.
5. The display panel according to claim 1, wherein the gate electrode includes a first portion and a second portion which are stacked in a direction away from the substrate;
wherein, in a plane parallel to the substrate surface, the shape of the first portion is the same as the shape of the projection of the first surface on the substrate;
the shape of the second portion is the same as the shape of the projection of the second surface on the substrate.
6. The display panel according to claim 5, wherein the first portion and the second portion are made of different materials.
7. The display panel according to claim 6, wherein the material of the first portion is Al; the second part is made of Ti.
8. The display panel of claim 7, wherein the gate has smooth sidewalls, and the sidewalls have an angle with the first surface.
9. The display panel according to claim 8, wherein the gate electrode comprises a first layer, a second layer, and a third layer which are stacked;
wherein the first layer and the third layer are both made of Ti; the second layer is made of Al.
10. The display panel according to claim 8, wherein the gate electrode is made of Al.
11. The display panel according to any one of claims 1 to 10, wherein the display panel further comprises an interlayer dielectric layer, the interlayer dielectric layer is located on a side of the gate away from the substrate, the interlayer dielectric layer covers the gate, the interlayer dielectric layer is a metal oxide, and the interlayer dielectric layer covers a sidewall of the gate.
12. The display panel according to claim 11, wherein the interlayer dielectric layer has a thickness of 10nm to 100nm, inclusive.
13. The display panel according to claim 11, wherein the display panel further comprises a low temperature polysilicon thin film transistor and a metal pad layer, and a source drain of the oxide thin film transistor and a source drain of the low temperature polysilicon thin film transistor are arranged in the same layer;
the metal cushion layer is positioned on one side of the oxide thin film transistor, which is far away from the substrate;
the display panel also comprises a capacitor metal layer, the capacitor metal layer and the grid are on the same layer, and the interlayer dielectric layer is positioned between the capacitor metal layer and the metal cushion layer;
the capacitor metal layer and the metal pad layer at least partially overlap in a direction perpendicular to the substrate.
14. The display panel according to claim 1,
the display panel comprises a binding area, the binding area is positioned on one side of the display panel, and the binding area is used for binding a drive chip;
the oxide thin film transistor comprises a first oxide thin film transistor and a second oxide thin film transistor, the minimum distance from the first oxide thin film transistor to the binding region is d1, the minimum distance from the second oxide thin film transistor to the binding region is d2, and d2 > d 1;
the resistance of the active layer of the first oxide thin film transistor is greater than the resistance of the active layer of the second oxide thin film transistor.
15. The display panel according to claim 14,
the resistance value of the active layer of the oxide thin film transistor is inversely related to the minimum distance of the oxide thin film transistor to the binding region.
16. The display panel according to claim 14,
the distance from the orthographic projection of the second surface of the first oxide thin film transistor to the orthographic projection of the first surface of the first oxide thin film transistor on the substrate is D2;
the distance from the orthographic projection of the second surface of the second oxide thin film transistor to the orthographic projection of the first surface of the second oxide thin film transistor on the substrate is D3;
wherein D2 < D3.
17. The display panel according to claim 16,
the included angle between the side wall of the grid electrode of the first oxide thin film transistor and the substrate is a1, the included angle between the side wall of the grid electrode of the second oxide thin film transistor and the substrate is a2, and a2 is less than a 1.
18. A display device comprising the display panel according to any one of claims 1 to 17.
19. A method for manufacturing a display panel is characterized by comprising the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a substrate and an oxide thin film transistor arranged on one side of the substrate, the oxide thin film transistor comprises an oxide channel and a grid electrode positioned on one side, facing away from the substrate, of the oxide channel, and the grid electrode comprises a first surface and a second surface which are oppositely arranged, wherein the first surface is a surface close to the oxide channel, and the second surface is a surface facing away from the oxide channel; the projection of the first surface on the substrate is located inside the projection of the second surface on the substrate, and the area of the projection of the first surface on the substrate is smaller than the area of the projection of the second surface on the substrate;
and conducting treatment is carried out on the oxide channel by taking the grid electrode as a blocking layer.
20. The method for manufacturing a display panel according to claim 19,
forming an interlayer dielectric layer on the grid;
and conducting treatment on the oxide channel by using the grid electrode as a blocking layer is positioned before or after the step of forming the interlayer dielectric layer on the semiconductor substrate.
21. The method for manufacturing a display panel according to claim 20, wherein the forming an interlayer dielectric layer on the gate electrode specifically includes:
and manufacturing and forming the interlayer dielectric layer by adopting an atomic layer deposition method.
22. The display panel manufacturing method according to claim 19, wherein when the gate electrode includes a first portion and a second portion which are stacked in a direction away from the substrate;
the manufacturing method of the grid electrode comprises the following steps:
forming a first partial layer structure;
forming a second partial layer structure on the first partial layer structure;
and etching the first part of layer structure and the second part of layer structure by adopting an etching process, wherein the etching rate of the first part of layer structure is greater than that of the second part of layer structure, and the first part and the second part are formed.
23. The method of claim 19, wherein when the gate has a smooth sidewall and the sidewall forms an angle with the first surface; the manufacturing method of the grid electrode comprises the following steps:
forming an organic layer;
forming a through hole on the organic layer, wherein the opening area of the through hole, which is far away from the substrate, is larger than the opening area of the through hole, which is far towards the substrate;
and filling the through hole with metal to form a grid electrode with smooth side walls.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011394874.1A CN112490275B (en) | 2020-12-03 | 2020-12-03 | Display panel, manufacturing method thereof and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011394874.1A CN112490275B (en) | 2020-12-03 | 2020-12-03 | Display panel, manufacturing method thereof and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112490275A true CN112490275A (en) | 2021-03-12 |
| CN112490275B CN112490275B (en) | 2023-04-21 |
Family
ID=74939039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011394874.1A Active CN112490275B (en) | 2020-12-03 | 2020-12-03 | Display panel, manufacturing method thereof and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112490275B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115633521A (en) * | 2022-11-17 | 2023-01-20 | 北京京东方技术开发有限公司 | Display substrate and display device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100032679A1 (en) * | 2008-08-05 | 2010-02-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and display device |
| CN106783626A (en) * | 2017-01-04 | 2017-05-31 | 京东方科技集团股份有限公司 | The manufacture method of thin film transistor (TFT), array base palte and display device |
| WO2017166431A1 (en) * | 2016-04-01 | 2017-10-05 | 京东方科技集团股份有限公司 | Tft array substrate and manufacturing method therefor, and display device |
| US20180061868A1 (en) * | 2016-08-31 | 2018-03-01 | Lg Display Co., Ltd. | Organic light-emitting display device comprising multiple types of thin-film transistors and method of fabricating the same |
| CN108231904A (en) * | 2016-12-13 | 2018-06-29 | 天马日本株式会社 | Thin film transistor (TFT) and its driving method, display device and transistor circuit |
| WO2018184279A1 (en) * | 2017-04-05 | 2018-10-11 | 武汉华星光电技术有限公司 | Tft substrate and manufacturing method thereof |
| CN110444553A (en) * | 2019-08-14 | 2019-11-12 | 京东方科技集团股份有限公司 | Photosensitive device and its manufacturing method, detection substrate and array substrate |
| CN111739916A (en) * | 2020-06-30 | 2020-10-02 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
-
2020
- 2020-12-03 CN CN202011394874.1A patent/CN112490275B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100032679A1 (en) * | 2008-08-05 | 2010-02-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and display device |
| WO2017166431A1 (en) * | 2016-04-01 | 2017-10-05 | 京东方科技集团股份有限公司 | Tft array substrate and manufacturing method therefor, and display device |
| US20180061868A1 (en) * | 2016-08-31 | 2018-03-01 | Lg Display Co., Ltd. | Organic light-emitting display device comprising multiple types of thin-film transistors and method of fabricating the same |
| CN108231904A (en) * | 2016-12-13 | 2018-06-29 | 天马日本株式会社 | Thin film transistor (TFT) and its driving method, display device and transistor circuit |
| CN106783626A (en) * | 2017-01-04 | 2017-05-31 | 京东方科技集团股份有限公司 | The manufacture method of thin film transistor (TFT), array base palte and display device |
| WO2018184279A1 (en) * | 2017-04-05 | 2018-10-11 | 武汉华星光电技术有限公司 | Tft substrate and manufacturing method thereof |
| CN110444553A (en) * | 2019-08-14 | 2019-11-12 | 京东方科技集团股份有限公司 | Photosensitive device and its manufacturing method, detection substrate and array substrate |
| CN111739916A (en) * | 2020-06-30 | 2020-10-02 | 上海天马有机发光显示技术有限公司 | Display panel and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115633521A (en) * | 2022-11-17 | 2023-01-20 | 北京京东方技术开发有限公司 | Display substrate and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112490275B (en) | 2023-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11923382B2 (en) | Method of fabricating array substrate, array substrate and display device | |
| CN109920818B (en) | Display panel, manufacturing method thereof and display device | |
| US11696448B2 (en) | Memory device and method of forming the same | |
| CN112331679B (en) | Display device | |
| US11004980B2 (en) | Thin film transistor having vertical channel and manufacturing method therefor, array substrate, display panel and display device | |
| JP2023518622A (en) | DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY MOTHERBOARD AND DISPLAY DEVICE | |
| US20170148889A1 (en) | Metal oxide semiconductor field effect transistor power device with multi gates connection | |
| CN110299322B (en) | Display substrate, manufacturing method thereof and display device | |
| WO2015010404A1 (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| US20080048191A1 (en) | Organic light emitting display device and method of fabricating the same | |
| CN112490275B (en) | Display panel, manufacturing method thereof and display device | |
| CN107112365A (en) | Semiconductor device | |
| CN113036057A (en) | Array substrate, preparation method thereof, display panel and display device | |
| US9379233B2 (en) | Semiconductor device | |
| CN114156285B (en) | Array substrate, preparation method thereof and display panel | |
| US20170250076A1 (en) | Thin Film Transistor and Manufacturing Method Thereof, Array Substrate and Manufacturing Method Thereof, Display Apparatus | |
| CN113745249B (en) | Display panel, preparation method thereof and mobile terminal | |
| WO2024036766A1 (en) | Array substrate and display panel | |
| CN114975613A (en) | Array substrate, manufacturing method thereof and display panel | |
| CN112103245B (en) | Manufacturing method of array substrate, array substrate and display panel | |
| TWI726692B (en) | Semiconductor device and method for fabricating the same | |
| CN109411531B (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN111540787A (en) | Oxide thin film transistor and preparation method thereof | |
| CN111430383A (en) | Array substrate, manufacturing method thereof and display device | |
| CN116207131B (en) | Thin film transistor and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |