CN112466852A - Manufacturing method of bypass capacitor and bypass capacitor - Google Patents
Manufacturing method of bypass capacitor and bypass capacitor Download PDFInfo
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- CN112466852A CN112466852A CN202110114950.7A CN202110114950A CN112466852A CN 112466852 A CN112466852 A CN 112466852A CN 202110114950 A CN202110114950 A CN 202110114950A CN 112466852 A CN112466852 A CN 112466852A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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Abstract
The invention relates to the technical field of semiconductors, and discloses a manufacturing method of a bypass capacitor and the bypass capacitor, wherein the method comprises the following steps: depositing a first metal layer on any surface of the substrate; etching a through hole on the substrate, wherein the through hole and the first metal layer enclose a groove; depositing a second metal layer and an insulating medium layer on the inner surface of the groove in sequence; and electroplating a third metal layer on the inner surface of the deposited first groove and one surface of the substrate, which is far away from the first metal layer, and forming a bypass capacitor by the first metal layer, the second metal layer, the insulating medium layer and the third metal layer which are distributed in sequence. The manufacturing method of the bypass capacitor and the bypass capacitor can reduce the area of a chip occupied by the capacitor device, so that the chip layout is more convenient and the chip cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a bypass capacitor and the bypass capacitor.
Background
The bypass capacitor is widely applied to a microwave monolithic integrated circuit and is used for filtering and impedance matching of direct current power supply. At present, most of the existing bypass capacitors are large, and occupy most of the area of a chip, so that the layout of the chip is limited, and the cost of the chip is increased.
Therefore, how to provide an effective solution to reduce the occupied area of the bypass capacitor on the chip has become an urgent problem in the prior art.
Disclosure of Invention
In order to solve the problem of large occupied area of the bypass capacitor on a chip in the prior art, the invention aims to provide a manufacturing method of the bypass capacitor and the bypass capacitor so as to reduce the occupied area of the bypass capacitor on the chip.
In a first aspect, the present invention provides a method of manufacturing a bypass capacitor, the method comprising:
depositing a first metal layer on any surface of the substrate;
etching a through hole on the substrate, wherein the through hole and the first metal layer enclose a groove;
depositing a second metal layer and an insulating medium layer on the inner surface of the groove in sequence;
and electroplating a third metal layer on the inner surface of the deposited first groove and one surface of the substrate, which is far away from the first metal layer, and forming a bypass capacitor by the first metal layer, the second metal layer, the insulating dielectric layer and the third metal layer which are distributed in sequence.
Through the design, the first metal layer is deposited on the substrate and etched on the substrate to form the through hole, then the second metal layer and the insulating medium layer are sequentially deposited on the inner surface of the groove surrounded by the through hole and the first metal layer, finally the third metal layer is electroplated on the inner surface of the deposited first groove and the surface of the substrate, which is far away from the first metal layer, and the first metal layer, the second metal layer, the insulating medium layer and the third metal layer which are sequentially distributed can form the bypass capacitor, so that the area of the chip occupied by the capacitor device can be reduced, the chip layout is more convenient and fast, and the chip cost is greatly reduced.
In one possible design, etching a via hole in the substrate includes:
and etching the substrate to form the through hole by physical etching or chemical etching.
In one possible design, etching a via hole in the substrate includes:
and etching the substrate to form the through hole in a positive photoetching mode.
In one possible design, the first metal layer, the second metal layer, and the third metal layer are all made of the same material.
In one possible design, the first metal layer, the second metal layer, and the third metal layer are all titanium tungsten alloy layers.
In one possible design, the insulating dielectric layer is a silicon oxide layer or a silicon nitride layer.
In one possible design, the substrate is a gallium arsenide substrate or a silicon substrate.
In a second aspect, the present invention provides a bypass capacitor comprising:
the device comprises a substrate, a first substrate and a second substrate, wherein through holes are etched in the substrate;
the first metal layer is deposited on any surface of the substrate, and the first metal layer and the through hole enclose a groove;
a second metal layer;
the second metal layer and the insulating medium layer are deposited on the inner surface of the groove in sequence;
and the third metal layer is electroplated on the inner surface of the deposited first groove and one surface of the substrate, which is deviated from the first metal layer.
In one possible design, the first groove after the third metal layer is electroplated is filled with an insulating filling layer.
In one possible design, the insulating fill layer is deposited in the first recess after electroplating the third metal layer.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a bypass capacitor according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a bypass capacitor according to an embodiment of the present invention.
Icon: 110-a substrate; 120-a first metal layer; 130-a second metal layer; 140-insulating dielectric layer; 150-third metal layer.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.
It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time; for the term "/and" as may appear herein, which describes another associative object relationship, it means that two relationships may exist, e.g., a/and B, may mean: a exists independently, and A and B exist independently; in addition, for the character "/" that may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.
It will be understood that when an element is referred to herein as being "connected," "connected," or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, if a unit is referred to herein as being "directly connected" or "directly coupled" to another unit, it is intended that no intervening units are present. In addition, other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between … …" versus "directly between … …", "adjacent" versus "directly adjacent", etc.).
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.
It should also be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
It should be understood that specific details are provided in the following description to facilitate a thorough understanding of example embodiments. However, it will be understood by those of ordinary skill in the art that the example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams in order not to obscure the examples in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.
Examples
In order to solve the problem that the occupied area of a bypass capacitor on a chip is large in the prior art, the embodiment of the application provides a manufacturing method of the bypass capacitor and the bypass capacitor.
Referring to fig. 1, a flow chart of a method for manufacturing a bypass capacitor according to one or more embodiments of the present disclosure is shown. As shown in fig. 1, the method for manufacturing the bypass capacitor may include the steps of:
step S101, depositing a first metal layer on any surface of a substrate.
The substrate may be, but is not limited to, a gallium arsenide substrate, a silicon substrate, or the like. The first metal layer may be, but is not limited to, a titanium metal layer, a tungsten metal layer, a titanium tungsten alloy layer, or the like.
Step S102, etching and forming a through hole on the substrate.
When the substrate is etched, etching can be carried out from one surface of the substrate, which is far away from the first metal layer, and a through hole penetrating through the substrate is formed on the substrate in an etching mode, and the through hole and the first metal layer enclose a groove.
In the embodiment of the application, the pattern to be etched can be formed on the substrate by adopting a positive photoetching or negative photoetching mode.
During etching, the through hole can be formed on the substrate through physical etching or chemical etching. Specific processes are not specifically described in the embodiments of the present application.
And step S103, depositing a second metal layer and an insulating medium layer on the inner surface of the groove in sequence.
The second metal layer may be, but is not limited to, a titanium metal layer, a tungsten metal layer, a titanium-tungsten alloy layer, or the like. The insulating dielectric layer may be, but is not limited to, a silicon oxide layer, a silicon nitride layer, or the like.
In the embodiment of the application, when the second metal layer and the insulating dielectric layer are deposited in the groove, the second metal layer is deposited in the groove, and then the insulating dielectric layer is deposited on the second metal layer after the second metal layer is deposited.
And step S104, electroplating a third metal on the inner surface of the deposited first groove and one surface of the substrate, which is far away from the first metal layer.
The third metal layer may be, but is not limited to, a titanium metal layer, a tungsten metal layer, a titanium-tungsten alloy layer, or the like. The deposited first groove is the first groove with the inner surface sequentially deposited with the second metal layer and the insulating medium layer.
It should be noted that, when the insulating dielectric layer is deposited in step S103, the deposited insulating dielectric layer needs to completely cover the surface of the second metal layer, and thus the deposited insulating dielectric layer can completely separate the second metal layer from the third metal layer, so that the capacitor structure can be formed.
The first metal layer is deposited on one surface of the substrate, the through hole formed by etching on the substrate and the first metal layer enclose a groove, the second metal layer and the insulating medium layer are sequentially deposited on the inner surface of the groove, then the third metal layer is electroplated on the inner surface of the deposited first groove and the surface of the substrate, which is far away from the first metal layer, the second metal layer and the third metal layer can be electrically isolated by the insulating medium layer deposited on the inner surface of the groove, and the deposited second metal layer encloses the part, located in the groove, of the third metal layer, so that the first metal layer, the second metal layer, the insulating medium layer and the third metal layer which are sequentially distributed can form a bypass capacitor.
In the embodiment of the present application, the first metal layer, the second metal layer, and the third metal layer are made of the same material, and are all titanium-tungsten alloy layers. The titanium-tungsten alloy has good conductivity and corrosion resistance, so that the performance and the service life of the bypass capacitor can be guaranteed.
In summary, in the manufacturing method of the bypass capacitor provided by the embodiment of the present application, the first metal layer is deposited on one surface of the substrate, the through hole is formed on the substrate by etching, the through hole and the first metal layer enclose a groove, the second metal layer and the insulating medium layer are sequentially deposited on the inner surface of the groove, and then the third metal layer is electroplated on the inner surface of the deposited first groove and the surface of the substrate away from the first metal layer. The insulating dielectric layer deposited on the inner surface of the groove can electrically isolate the second metal layer from the third metal layer, and the deposited second metal layer surrounds the part of the third metal layer, which is positioned in the groove, so that the bypass capacitor can be formed. Therefore, the capacitor used in the integrated circuit can be manufactured very conveniently, and the bypass capacitor is formed in an etching mode, so that the area of the chip occupied by the capacitor device can be effectively reduced, the chip layout is more convenient and faster, and meanwhile, the manufacturing cost of the chip is greatly reduced.
Referring to fig. 2, a schematic structural diagram of a bypass capacitor provided in the present embodiment is shown, where the bypass capacitor can be manufactured by the method for manufacturing a bypass capacitor provided in the present embodiment, and the bypass capacitor includes:
a substrate 110, wherein a through hole is etched on the substrate 110;
the first metal layer 120 is deposited on any surface of the substrate 110, and a groove is defined by the first metal layer 120 and the through hole;
a second metal layer 130;
the insulating medium layer 140, the second metal layer 130 and the insulating medium layer 140 are deposited on the inner surface of the groove in sequence;
and a third metal layer 150, wherein the third metal layer 150 is electroplated on the inner surface of the deposited first groove and the surface of the substrate 110 facing away from the first metal layer 120.
Because the substrate 110 is etched with a through hole, the first metal layer 120 is deposited on one side of the substrate 110 and forms a groove with the through hole, the second metal layer 130 and the insulating medium layer 140 are sequentially deposited on the inner surface of the groove, and the third metal layer 150 is electroplated on the inner surface of the deposited first groove and the side of the substrate 110 away from the first metal layer 120. The insulating dielectric layer 140 deposited on the inner surface of the groove can electrically isolate the second metal layer 130 from the third metal layer 150, and the deposited second metal layer 130 surrounds the portion of the third metal layer 150 located in the groove, so that the first metal layer 120, the second metal layer 130, the insulating dielectric layer 140 and the third metal layer 150 distributed in sequence can form a bypass capacitor. Therefore, the volume of the bypass capacitor can be effectively reduced, the area of the chip occupied by the capacitor device is reduced, the chip layout is more convenient and fast, and meanwhile, the manufacturing cost of the chip is greatly reduced.
Further, in the bypass capacitor provided in the embodiment of the present application, the insulating filling layer is filled in the first groove after the third metal layer 150 is electroplated. The insulating filling layer may be, but is not limited to, a silicon oxide layer, a silicon nitride layer, or the like.
In the embodiment of the present application, the insulating filling layer is deposited in the first groove after the third metal layer is electroplated.
The invention is not limited to the above alternative embodiments, and any other various forms of products can be obtained by anyone in the light of the present invention, but any changes in shape or structure thereof, which fall within the scope of the present invention as defined in the claims, fall within the scope of the present invention.
Claims (10)
1. A method of manufacturing a bypass capacitor, the method comprising:
depositing a first metal layer on any surface of the substrate;
etching a through hole on the substrate, wherein the through hole and the first metal layer enclose a groove;
depositing a second metal layer and an insulating medium layer on the inner surface of the groove in sequence;
and electroplating a third metal layer on the inner surface of the deposited first groove and one surface of the substrate, which is far away from the first metal layer, and forming a bypass capacitor by the first metal layer, the second metal layer, the insulating dielectric layer and the third metal layer which are distributed in sequence.
2. The method of claim 1, wherein etching vias in the substrate comprises:
and etching the substrate to form the through hole by physical etching or chemical etching.
3. The method of claim 1, wherein etching vias in the substrate comprises:
and etching the substrate to form the through hole in a positive photoetching mode.
4. The method of claim 1, wherein the first metal layer, the second metal layer, and the third metal layer are all of the same material.
5. The method of claim 4, wherein the first metal layer, the second metal layer, and the third metal layer are all titanium tungsten alloy layers.
6. The method of claim 1, wherein the insulating dielectric layer is a silicon oxide layer or a silicon nitride layer.
7. The method of claim 1, wherein the substrate is a gallium arsenide substrate or a silicon substrate.
8. A bypass capacitor, comprising:
the device comprises a substrate, a first substrate and a second substrate, wherein through holes are etched in the substrate;
the first metal layer is deposited on any surface of the substrate, and the first metal layer and the through hole enclose a groove;
a second metal layer;
the second metal layer and the insulating medium layer are deposited on the inner surface of the groove in sequence;
and the third metal layer is electroplated on the inner surface of the deposited first groove and one surface of the substrate, which is deviated from the first metal layer.
9. The bypass capacitor according to claim 8, wherein the first recess after electroplating the third metal layer is filled with an insulating filling layer.
10. The bypass capacitor according to claim 9, wherein said insulating fill layer is deposited in said first recess after electroplating said third metal layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110114950.7A CN112466852A (en) | 2021-01-28 | 2021-01-28 | Manufacturing method of bypass capacitor and bypass capacitor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110114950.7A CN112466852A (en) | 2021-01-28 | 2021-01-28 | Manufacturing method of bypass capacitor and bypass capacitor |
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| CN112466852A true CN112466852A (en) | 2021-03-09 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236698A (en) * | 1995-02-27 | 1996-09-13 | Nec Eng Ltd | Semiconductor device |
| US20040119140A1 (en) * | 2000-08-15 | 2004-06-24 | Masaaki Nishijima | RF passive circuit and RF amplifier with via-holes |
| CN102386240A (en) * | 2010-09-01 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Cylindrical embedded capacitors |
| CN104347345A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Capacitance structure formation method |
| CN107275315A (en) * | 2017-05-27 | 2017-10-20 | 厦门市三安集成电路有限公司 | A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof |
| CN109920757A (en) * | 2019-01-31 | 2019-06-21 | 厦门市三安集成电路有限公司 | A kind of dorsal segment technique improving compound semiconductor device unfailing performance |
| CN110752207A (en) * | 2019-09-10 | 2020-02-04 | 福建省福联集成电路有限公司 | Back capacitor structure and manufacturing method |
-
2021
- 2021-01-28 CN CN202110114950.7A patent/CN112466852A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08236698A (en) * | 1995-02-27 | 1996-09-13 | Nec Eng Ltd | Semiconductor device |
| US20040119140A1 (en) * | 2000-08-15 | 2004-06-24 | Masaaki Nishijima | RF passive circuit and RF amplifier with via-holes |
| CN102386240A (en) * | 2010-09-01 | 2012-03-21 | 台湾积体电路制造股份有限公司 | Cylindrical embedded capacitors |
| CN104347345A (en) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | Capacitance structure formation method |
| CN107275315A (en) * | 2017-05-27 | 2017-10-20 | 厦门市三安集成电路有限公司 | A kind of structure of compound semiconductor back of the body gold capacitor and preparation method thereof |
| CN109920757A (en) * | 2019-01-31 | 2019-06-21 | 厦门市三安集成电路有限公司 | A kind of dorsal segment technique improving compound semiconductor device unfailing performance |
| CN110752207A (en) * | 2019-09-10 | 2020-02-04 | 福建省福联集成电路有限公司 | Back capacitor structure and manufacturing method |
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Application publication date: 20210309 |