CN112466820A - 半导体装置封装及其制造方法 - Google Patents

半导体装置封装及其制造方法 Download PDF

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Publication number
CN112466820A
CN112466820A CN202010419630.8A CN202010419630A CN112466820A CN 112466820 A CN112466820 A CN 112466820A CN 202010419630 A CN202010419630 A CN 202010419630A CN 112466820 A CN112466820 A CN 112466820A
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conductive layer
conductive
layer
semiconductor device
device package
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CN202010419630.8A
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Inventor
陈瑭原
施孟铠
李德章
唐心陆
洪志斌
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN112466820A publication Critical patent/CN112466820A/zh
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Abstract

本发明涉及一种半导体装置封装，其包含第一导电层、第二导电层和第三导电层。所述第一导电层具有第一间距。所述第二导电层具有第二间距并且布置在所述第一导电层的两个不同的侧面处。所述第三导电层具有第三间距并且安置在所述第一导电层和所述第二导电层上方。所述第三导电层电连接到所述第一导电层。所述第一间距小于所述第三间距，并且所述第三间距小于所述第二间距。

Description

半导体装置封装及其制造方法
技术领域
除了别的之外，本发明涉及半导体装置封装及其制造方法。
背景技术
半导体装置封装可包含堆叠到彼此的一些半导体装置。然而，晶片弯曲或高厚度可能不利地影响半导体装置封装的性能和效率。
发明内容
根据本公开的一些实例实施例，半导体装置封装包含第一导电层、第二导电层和第三导电层。第一导电层具有第一间距。第二导电层具有第二间距并且布置在第一导电层的两个不同侧面处。第三导电层具有第三间距并且安置在第一导电层和第二导电层上方。第三导电层电连接到第一导电层。第一间距小于第三间距，并且第三间距小于第二间距。
根据本公开的一些实例实施例，半导体装置封装包含第一导电层、第一介电层、第二导电层、第二介电层和第三导电层。第一介电层覆盖第一导电层。第二导电层安置在第一介电层的两个不同侧面处。第三导电层安置在第一导电层和第二导电层上方。第二介电层覆盖第一导电层、第一介电层、第二导电层和第三导电层的至少一部分。第一介电层的硬度大于第二介电层的硬度。
根据本公开的一些实例实施例，制造半导体装置封装的方法包含：提供载体；在载体上安置第一导电层；在载体上在第一导电层的不同侧面处安置两个第二导电层；在第一导电层和第二导电层上方安置第三导电层；以及将两个裸片连接到第三导电层。
附图说明
当结合附图阅读时，从以下详细描述容易理解本发明的方面。应注意，各种特征可能并不按比例绘制。实际上，为了论述的清楚起见，可任意增大或减小各个特征的尺寸。
图1是根据本发明的一些实施例的半导体装置封装的截面图。
图2是根据本发明的一些实施例的另一半导体装置封装的截面图。
图3是根据本发明的一些实施例的另一半导体装置封装的截面图。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I、图4J和图4K说明了根据本申请的一些实施例用于制造半导体装置封装的方法的各个阶段。
图5A、图5B、图5C、图5D、图5E、图5F和图5G说明根据本申请的一些实施例用于制造另一半导体装置封装的方法的各个阶段。
贯穿图式和详细描述使用共同参考标号来指示相同或类似元件。根据以下结合附图作出的详细描述，本发明将更显而易见。
具体实施方式
以下公开内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的特定实例。当然，这些仅是实例且并不意图是限制性的。在本发明中，在以下描述中对第一特征在第二特征之上或上的形成的参考可包含第一特征与第二特征直接接触形成的实施例，并且还可包含额外特征可形成于第一特征与第二特征之间从而使得第一特征与第二特征可不直接接触的实施例。另外，本发明可能在各种实例中重复参考数字和/或字母。此重复是出于简单和清晰的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
下文详细论述本发明的实施例。然而，应了解，本发明提供了可在多种多样的特定情境中实施的许多适用的概念。所论述的特定实施例仅仅是说明性的且并不限制本发明的范围。
图1是根据本发明的一些实施例的半导体装置封装1的截面图。半导体装置封装1包含电子组件11a、11b和11c、互连层14，以及导电连接件14m，其可以沉积在衬底上。取决于特定应用，衬底可以是柔性衬底或刚性衬底。
电子组件11a、11b和11c中的每一个包含多个半导体装置,例如但不限于晶体管、电容器和电阻器，其由裸片互连结构一起互连成功能电路以由此形成集成电路。在一些实施例中，电子组件11c经配置以在电子组件11a和11b之间执行计算或信号发射。电子组件11c布置在电子组件11a和11b下方。因此，半导体装置封装1具有相对较大的厚度，这可能妨碍半导体装置封装1的小型化。
在一些实施例中，电子组件11a、11b由封装主体12a覆盖或囊封。在一些实施例中，封装主体12a包含在其中含有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。
互连层14包含电子组件11a、11b所电连接到的电触点(例如，微型衬垫)。在一些实施例中，互连层14是介电层或非硅中介层(例如，有机中介层)并且包含嵌入其中的多个导电连接件14m。
在一些实施例中，电子组件11a安置在导电连接件14m上。电子组件11b安置为邻近于电子组件11a并且在导电连接件14m上。电子组件11a通过导电连接件14m和电子组件11c电连接到电子组件11b。
封装主体12b覆盖或囊封电子组件11c以及导电连接件14m的一部分。互连层14安置在封装主体12b上。封装主体12b包含在其中含有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。
电子组件11c和封装主体12b具有不同的热膨胀系数(CTE)。因为电子组件11c被封装主体12b囊封，所以在制造过程(例如，RDL、钝化或其它过程)期间可能出现晶片弯曲，这是由于电子组件11c与封装主体12b之间的CTE的不匹配。这可能不利地影响半导体装置封装1的性能。
图2是根据本发明的一些实施例的半导体装置封装2的截面图。半导体装置封装2包含电子组件21a和21b、互连层24a和24b，以及导电连接件24m1、24m2和24m3。
电子组件21a、21b中的每一个包含多个半导体装置,例如但不限于晶体管、电容器和电阻器，其由裸片互连结构一起互连成功能电路以由此形成集成电路。如所属领域的技术人员将理解，半导体裸片的装置侧包含有源部分，所述有源部分包含集成电路和互连件。根据若干不同实施例，电子组件21a、21b可以是任何合适的集成电路装置，包含但不限于微处理器(例如，单核或多核)、存储器装置、芯片组、图形装置、高带宽存储器(HBM)，或专用集成电路(ASIC)。在一些实施例中，电子组件21a被称作第一裸片，并且电子组件21b被称作第二裸片。
在一些实施例中，多个电触点25a安置在电子组件21a和21b的有源表面上以在电子组件21a、21b与其它电子组件之间提供电连接。
在一些实施例中，电子组件21a、21b由封装主体22a覆盖或囊封。封装主体22a包含在其中含有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。封装主体22a包含嵌入其中的导电连接件24m3的一部分。封装主体22a覆盖或囊封互连层24b(例如，互连层24b的顶部表面)。举例来说，封装主体22a安置在互连层24b上并且邻近于互连层24b。
互连层24b包含电子组件21a、21b所电连接到的电触点(例如，微型衬垫)。在一些实施例中，互连层24b是介电层或非硅中介层(例如，有机中介层)并且包含嵌入其中的多个导电连接件24m3。
在一些实施例中，互连层24b覆盖或囊封互连层24a。举例来说，互连层24b安置在互连层24a上并且围绕互连层24a。举例来说，互连层24b接触互连层24a的顶部表面和横向表面。在一些实施例中，互连层24a的材料不同于互连层24b的材料。更确切地说，互连层24a的硬度大于互连层24b的硬度。
互连层24a在其中包含多个导电连接件(或再分布层(RDL))24m1。互连层24a的导电连接件24m1的一部分电连接到互连层24b的导电连接件24m3。举例来说，电连接到电子组件21a、21b的导电连接件24m1电连接到互连层24b的导电连接件24m3。
互连层24a在电子组件21a和21b之间提供互连。导电连接件24m1是嵌入在互连层24a内的精细迹线。在一些实施例中，导电连接件24m1的线/空间(L/S)小于导电连接件24m2或24m3的线/空间(L/S)。互连层24a可以充当电子组件21a和21b之间的桥接件以按其间的相对高的速率发射数据。与使用电子组件11c作为互连桥接件(或链路)的图1的实施例相比，半导体装置封装2的电子组件21a和21b之间的互连桥接件可通过导电连接件24m1来实现，这将减小半导体装置封装2的厚度。
在一些实施例中，电子组件21a安置在导电连接件24m3上。电子组件21b安置为邻近于电子组件21a并且在导电连接件24m3上。电子组件21a通过导电连接件24m1和24m3电连接到电子组件21b。
如图2中所示，电子组件21a安置在导电连接件24m1的部分24m1a和邻近于导电连接件24m1的部分24m1a的导电连接件24m2的部分24m2a之上。换句话说，导电连接件24m2的部分24m2a布置在电子组件21a下方。导电连接件24m1的部分24m1a邻近于导电连接件24m2的部分24m2a但是不直接接触导电连接件24m2的部分24m2a。电子组件21b安置在导电连接件24m1的部分24m1b和邻近于导电连接件24m1的部分24m1b的导电连接件24m2的部分24m2b之上。换句话说，导电连接件24m2的部分24m2b布置在电子组件21b下方。导电连接件24m1的部分24m1b邻近于导电连接件24m2的部分24m2b但是不直接接触导电连接件24m2的部分24m2b。
在一些实施例中，导电连接件24m1被称作第一导电层，导电连接件24m2被称作第二导电层，导电连接件24m3被称作第三导电层，互连层24a被称作第一介电层，并且互连层24b被称作第二介电层。
在一些实施例中，导电连接件24m1具有第一间距(例如，L/S)。导电连接件24m2具有第二间距。导电连接件24m3具有第三间距并且安置在导电连接件24m1和导电连接件24m2上方。导电连接件24m3电连接到导电连接件24m1。第一间距小于第三间距，并且第三间距小于第二间距。
举例来说，互连层24a的导电连接件24m1是精细间距互连件或精细线。互连层24b的导电连接件24m3是中间间距互连件或中间线。互连层24b的导电连接件24m2是粗略间距互连件或粗略线。换句话说，导电连接件24m1的密度大于导电连接件24m3的密度。导电连接件24m3的密度大于导电连接件24m2的密度。
在一些实施例中，导电连接件24m1的顶部表面与导电连接件24m2的顶部表面基本上共面。在其它实施例中，导电连接件24m1的顶部表面略微高于导电连接件24m2的顶部表面以便电连接导电连接件24m3。在一些实施例中，导电连接件24m1的直径小于导电连接件24m2或导电连接件24m3的直径。
导电连接件24m1、24m2、24m3在电子组件21a和21b之间提供互连。互连层24a可以充当电子组件21a和21b之间的桥接件或链路。在图1的实施例中，电子组件11c由封装主体12b囊封，这可引起在制造过程(例如，RDL、钝化或其它过程)期间的晶片弯曲，这是由于电子组件11c与封装主体12b之间的CTE的不匹配。这可能不利地影响半导体装置封装1的性能。与图1的实施例相比，半导体装置封装2的电子组件21a和21b之间的互连桥接件可通过导电连接件24m1来实现而无需布置另一电子组件及其相关联的封装主体，这将防止半导体装置封装2发生晶片弯曲。
图3是根据本发明的一些实施例的另一半导体装置封装3的截面图。半导体装置封装3类似于半导体装置封装2，不同之处在于在图3中，载体30安置在电子组件31a和31b上以覆盖或保护半导体装置封装3。在一些实施例中，载体30可以是玻璃载体或任何其它类型的合适的载体。
图4A、图4B、图4C、图4D、图4E、图4F、图4G、图4H、图4I、图4J和图4K说明了根据本申请的一些实施例用于制造半导体装置封装4的方法的各个阶段。为了更好的理解本发明的各方面，已经简化各图。
参考图4A，提供载体40，并且粘合剂层(或离型膜)40a形成或沉积在载体40上。在一些实施例中，载体40可以是玻璃载体或任何其它类型的合适的载体。
参考图4B，互连层44a通过载体40上的粘合剂层40a附接到载体40。在一些实施例中，互连层44a并不完全覆盖载体40。举例来说，互连层44a覆盖载体40的一部分并且暴露载体40的另一部分。另外，互连层44a覆盖或囊封导电连接件44m1。
参考图4C，导电连接件44m2形成或沉积在载体40和粘合剂层40a上。导电连接件44m2形成在互连层44a的两个不同侧面上以围绕导电连接件44m1和互连层44a。导电连接件44m2还可嵌入在介电层内。
在一些实施例中，导电连接件44m1和44m2通过电镀或通过其它合适的技术形成。导电连接件44m1和44m2具有不同的间距。在一些实施例中，导电连接件44m2是粗略间距互连件或粗略线，并且导电连接件44m1是精细间距互连件或精细线。
参考图4D，导电连接件44m3形成或沉积在互连层44b上。导电连接件44m3和互连层44b形成或沉积在互连层44a和导电连接件44m1、44m2上以便在导电连接件44m1、44m2和44m3之间提供电连接。互连层44b的硬度小于互连层44a的硬度。
参考图4E，执行导电连接件44m3和互连层44b的蚀刻、研磨或其它合适的过程。举例来说，针对导电连接件44m3和互连层44b执行激光钻孔以产生多个开口或沟槽。
参考图4F，对应于所产生的开口或沟槽执行通孔镀覆或金属镀覆。导电连接件44m3的一部分直接地接触导电连接件44m1。导电连接件44m1的间距小于导电连接件44m3的间距，并且导电连接件44m3的间距小于导电连接件44m2的间距。
参考图4G，电子组件41a和41b形成或安置在互连层44b上并且电连接到导电连接件44m3。电子组件41a和41b中的每一个包含多个电触点45a以在电子组件41a和41b与导电连接件44m3之间提供电连接。
随后形成或安置封装主体42a以覆盖或囊封电子组件41a和41b。在一些实施例中，封装主体42a包含含有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。
参考图4H，移除封装主体42a的一部分，因此每个电子组件41a和41b的后侧从封装主体42a暴露。在一些实施例中，可通过研磨、蚀刻或其它合适的过程移除封装体42a。
参考图4I和图4J，随后从互连层44a和44b移除载体40和粘合剂层40a以暴露导电连接件44m1和44m2。参考图4K，在下方形成多个焊料球45b以电连接导电连接件44m1和44m2。
导电连接件44m1嵌入在互连层44a内以在电子组件41a和41b之间以提供电连接。互连层44a可以充当电子组件41a和41b之间的桥接件。因此，可减小厚度而无需在电子组件41a和41b之下布置额外的电子组件。由于CTE不匹配的晶片弯曲也可得到改进或消除。
图5A、图5B、图5C、图5D、图5E、图5F和图5G说明根据本申请的一些实施例用于制造另一半导体装置封装5的方法的各个阶段。为了更好的理解本发明的各方面，已经简化各图。
参考图5A，提供载体50，并且粘合剂层(或离型膜)50a形成或沉积在载体50上。在一些实施例中，载体40可以是玻璃载体或任何其它类型的合适的载体。参考图5B，粘合剂层(或离型膜)50b形成或沉积在粘合剂层50a上。
参考图5C，电子组件51a和51b形成或安置在粘合剂层50b上。电子组件51a和51b中的每一个包含多个电触点55a以在电子组件51a和51b之间提供电连接。
参考图5D，随后形成或安置封装主体52a以覆盖或囊封电子组件51a和51b。在一些实施例中，封装主体52a包含含有填充物的环氧树脂、模制化合物(例如，环氧模制化合物或其它模制化合物)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅酮的材料，或其组合。
参考图5E，移除封装主体52a的一部分，因此多个电触点55a从封装主体52a暴露。在一些实施例中，可通过研磨、蚀刻或其它合适的过程移除封装体52a。
参考图5F，互连层54a形成或沉积在封装主体52a和电触点55a上。互连层54a覆盖或囊封导电连接件54m1。导电连接件54m2形成在互连层54a的两个不同侧面上以围绕导电连接件54m1和互连层54a。导电连接件54m3形成或沉积在互连层54b和导电连接件54m1上以便在导电连接件54m1、54m2和54m3之间提供电连接。
在一些实施例中，导电连接件54m1、54m2和54m3通过电镀或通过其它合适的技术形成。在一些实施例中，导电连接件54m2是粗略间距互连件或粗略线，导电连接件54m3是中间间距互连件或中间线，并且导电连接件54m1是精细间距互连件或精细线。
导电连接件54m1嵌入在互连层54a内以在电子组件51a和51b之间以提供电连接。互连层54a可以充当电子组件51a和51b之间的桥接件。因此，厚度可减小而无需在电子组件51a和51b之下布置额外的电子组件。由于CTE不匹配的晶片弯曲也可得到改进或消除。参考图5G，多个焊料球55b形成在导电连接件54m3上方以电连接其它半导体装置封装。
如本文中所使用，例如“在……下方”、“低于”、“下部”、“高于”、“上部”、“下部”、“左侧”、“右侧”及类似者的空间相对术语可以在本文中为易于描述而使用以描述如图中所说明的一个元件或特征与另一元件或特征的关系。除了图中所描绘的定向之外，空间相对术语意图涵盖在使用或操作中的装置的不同定向。所述设备可以其它方式定向(旋转90度或处于其它定向)，且本文中所使用的与空间相关的描述词可类似地相应地进行解释。应理解，当一元件被称作“连接到”或“耦合到”另一元件时，其可直接连接或耦合到另一元件，或可存在中间元件。
如本文中所使用，术语“近似地”、“基本上”、“基本”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确地发生的例子以及事件或情况极近似地发生的例子。如本文中相对于给定值或范围所使用，术语“约”通常意味着在给定值或范围的±10％、±5％、±1％或±0.5％内。范围可在本文中表示为从一个端点到另一端点或在两个端点之间。除非另外规定，否则本文中所公开的所有范围包括端点。术语“基本上共面”可指沿同一平面定位的在数微米(μm)内的两个表面，例如，沿着同一平面定位的在10μm内、5μm内、1μm内或0.5μm内。当参考“基本上”相同的数值或特性时，术语可指处于所述值的平均值的±10％、±5％、±1％或±0.5％内的值。
前文概述本发明的若干实施例及细节方面的特征。本发明中描述的实施例可容易地用作用于设计或修改其它过程的基础以及用于执行相同或相似目的和/或获得引入本文中的实施例的相同或相似优点的结构。此类等效构造并不脱离本发明的精神和范围，并且可在不脱离本发明的精神和范围的情况下作出各种改变、替代和变化。

Claims (20)

1.一种半导体装置封装，其包括：
第一导电层，其具有第一间距，
第二导电层，其具有第二间距并且布置在所述第一导电层的两个不同侧面处；以及
第三导电层，其具有第三间距并且安置在所述第一导电层和所述第二导电层上方，所述第三导电层电连接到所述第一导电层，其中所述第一间距小于所述第三间距，并且所述第三间距小于所述第二间距。
2.根据权利要求1所述的半导体装置封装，其进一步包括：
第一裸片，其安置在所述第三导电层上；以及
第二裸片安置为邻近于所述第一裸片并且在所述第三导电层上，其中所述第一裸片通过所述第一导电层电连接到所述第二裸片。
3.根据权利要求2所述的半导体装置封装，其中
所述第一裸片安置在所述第一导电层的第一部分之上并且所述第二导电层的第一部分邻近于所述第一导电层的所述第一部分；以及
所述第二裸片安置在所述第一导电层的第二部分之上并且所述第二导电层的第二部分邻近于所述第一导电层的所述第二部分。
4.根据权利要求2所述的半导体装置封装，其进一步包括：
载体，其布置在所述第一裸片和所述第二裸片上。
5.根据权利要求1所述的半导体装置封装，其中所述第二导电层围绕所述第一导电层。
6.根据权利要求1所述的半导体装置封装，其进一步包括：
第一介电层，其围绕所述第一导电层；以及
第二介电层，其围绕所述第一介电层、所述第二导电层和所述第三导电层的一部分。
7.根据权利要求6所述的半导体装置封装，其中所述第一介电层的材料不同于所述第二介电层的材料。
8.根据权利要求7所述的半导体装置封装，其中所述第一介电层的硬度大于所述第二介电层的硬度。
9.一种半导体装置封装，其包括：
第一导电层；
第一介电层，其覆盖所述第一导电层；
第二导电层，其安置在所述第一介电层的两个不同侧面处；
第三导电层，其安置在所述第一导电层和所述第二导电层之上；以及
第二介电层，其覆盖所述第一导电层、所述第一介电层、所述第二导电层和所述第三导电层的至少一部分，
其中所述第一介电层的硬度大于所述第二介电层的硬度。
10.根据权利要求9所述的半导体装置封装，其中所述第一导电层、所述第二导电层和所述第三导电层具有不同间距。
11.根据权利要求9所述的半导体装置封装，其进一步包括：
第一裸片，其安置在所述第三导电层上；以及
第二裸片，其安置为邻近于所述第一裸片并且在所述第三导电层上。
12.根据权利要求11所述的半导体装置封装，其中所述第一裸片通过所述第一导电层电连接到所述第二裸片。
13.根据权利要求12所述的半导体装置封装，其中：
所述第一裸片安置在所述第一导电层的第一部分之上并且所述第二导电层的第一部分邻近于所述第一导电层的所述第一部分；以及
所述第二裸片安置在所述第一导电层的第二部分之上并且所述第二导电层的第二部分邻近于所述第一导电层的所述第二部分。
14.根据权利要求13所述的半导体装置封装，其中所述第一导电层由所述第二导电层围绕。
15.根据权利要求9所述的半导体装置封装，其中所述第一导电层的密度大于所述第三导电层的密度，并且所述第三导电层的密度大于所述第二导电层的密度。
16.一种制造半导体装置封装的方法，其包括：
提供载体；
在所述载体上安置第一导电层；
在所述载体上在所述第一导电层的不同侧面处安置两个第二导电层；
在所述第一导电层和所述第二导电层上方安置第三导电层；以及
将两个裸片连接到所述第三导电层。
17.根据权利要求16所述的方法，其进一步包括：
形成第一介电层以围绕所述第一导电层。
18.根据权利要求17所述的方法，其进一步包括：
形成第二介电层以围绕所述第二导电层、所述第一介电层和所述第三导电层的一部分。
19.根据权利要求18所述的方法，其中所述第一介电层和所述第二介电层具有不同硬度。
20.根据权利要求16所述的方法，其中所述第一导电层、所述第二导电层和所述第三导电层具有不同间距。
CN202010419630.8A 2019-09-06 2020-05-18 半导体装置封装及其制造方法 Pending CN112466820A (zh)

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