CN112466254B - Display panel, display control method, capacity determination method and display device - Google Patents

Display panel, display control method, capacity determination method and display device Download PDF

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CN112466254B
CN112466254B CN202011497826.5A CN202011497826A CN112466254B CN 112466254 B CN112466254 B CN 112466254B CN 202011497826 A CN202011497826 A CN 202011497826A CN 112466254 B CN112466254 B CN 112466254B
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target
storage capacitor
pixel
capacity
target storage
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CN112466254A (en
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张蒙蒙
周星耀
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Wuhan Tianma Microelectronics Co Ltd
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Wuhan Tianma Microelectronics Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Abstract

The application discloses a display panel, a display control method, a capacity determination method and a display device. The display panel comprises a pixel unit, wherein the pixel unit comprises a target sub-pixel and a non-target sub-pixel, the target sub-pixel comprises a target pixel circuit and a target light-emitting element, the target pixel circuit comprises a target storage capacitor, the non-target sub-pixel comprises a non-target pixel circuit and a non-target light-emitting element, and the non-target pixel circuit comprises a non-target storage capacitor; wherein the capacity of the target storage capacitor is greater than the capacity of the non-target storage capacitor. According to the embodiment of the application, the problem that the brightness of the target sub-pixel cannot reach the required brightness can be solved.

Description

Display panel, display control method, capacity determination method and display device
Technical Field
The present application relates to the field of display technologies, and in particular, to a display panel, a display control method for a display panel, a method for determining a capacitance capacity, and a display device.
Background
Organic Light Emitting Diodes (OLEDs) are one of the hot spots in the research field of displays, and compared with Liquid Crystal Displays (LCDs), OLED Display panels have the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like.
With the development of display technology, OLED display panels are increasingly sought to have lower power consumption. However, in the prior art, although the power consumption of the OLED display panel can be further reduced, the luminance of the organic light emitting diode cannot reach the required luminance.
Disclosure of Invention
The application provides a display panel, a display control method of the display panel, a determination method of capacitance capacity and a display device, which can solve the problem that the brightness of a target sub-pixel cannot reach the required brightness.
In a first aspect, an embodiment of the present application provides a display panel, which includes a pixel unit, where the pixel unit includes a target sub-pixel and a non-target sub-pixel, the target sub-pixel includes a target pixel circuit and a target light emitting element, the target pixel circuit includes a target storage capacitor, the non-target sub-pixel includes a non-target pixel circuit and a non-target light emitting element, and the non-target pixel circuit includes a non-target storage capacitor; wherein the capacity of the target storage capacitor is greater than the capacity of the non-target storage capacitor.
In a second aspect, an embodiment of the present application provides a display control method for a display panel, for controlling the display panel according to the embodiment of the first aspect, where the display control method includes: and under the same gray scale, providing a target data voltage for the target sub-pixel, and providing a non-target data voltage for the non-target sub-pixel, wherein the difference between the non-target data voltage and the target data voltage is less than or equal to 0.2V.
In a third aspect, an embodiment of the present application provides a method for determining a capacitance capacity, which is used to determine a difference between a capacity of a target storage capacitor and a capacity of a non-target storage capacitor in a display panel as an embodiment of the first aspect, a target pixel circuit includes a target driving transistor, the target driving transistor includes a target gate, and the method for determining the capacitance capacity includes: changing the capacity of a target storage capacitor under the same data voltage, and acquiring the potential of a target grid under the capacities of different target storage capacitors so as to determine the corresponding relation between the capacity of the target storage capacitor and the potential of the target grid; and determining the difference value between the capacity of the target storage capacitor and the capacity of the non-target storage capacitor according to the corresponding relation and the current difference value of the target sub-pixel and the non-target sub-pixel under the same gray scale.
In a fourth aspect, an embodiment of the present application provides a display device, which includes the display panel as in the first aspect.
The inventor of the present application finds that, under the same data voltage, the larger the capacity of the storage capacitor of the sub-pixel is, the lower the gate potential of the driving transistor of the sub-pixel is, and the lower the gate potential of the driving transistor is, the larger the driving current flowing through the sub-pixel is, and thus the larger the luminance of the sub-pixel is; the larger the capacity of the storage capacitor of a sub-pixel is at the same gate potential of the drive transistor, i.e. at the same drive current, the larger the data voltage required by the sub-pixel is. Therefore, on one hand, under the same data voltage, the capacity of the target storage capacitor is equal to that of the non-target storage capacitor, and the capacity of the target storage capacitor is larger than that of the non-target storage capacitor in the embodiment of the application, so that the current of the target sub-pixel can be increased, and further the brightness of the target sub-pixel can be increased; on the other hand, under the same gate potential of the target driving transistor, that is, under the same driving current, the capacity of the target storage capacitor is equal to the capacity of the non-target storage capacitor, in the embodiment of the present application, the capacity of the target storage capacitor is greater than the capacity of the non-target storage capacitor, which increases the data voltage of the target sub-pixel, that is, increases the down-regulation range of the data voltage corresponding to the target sub-pixel, so that when the target sub-pixel is required to have higher luminance, the data voltage corresponding to the target sub-pixel can be further reduced, and the problem that the luminance of the target sub-pixel cannot reach the required luminance is solved.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic top view of a display panel provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of a circuit structure of a target sub-pixel according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a circuit structure of one of the non-target sub-pixels according to an embodiment of the present application;
fig. 4 is a schematic diagram illustrating a corresponding relationship between a gate potential of a driving transistor and a capacity of a storage capacitor according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a data voltage versus storage capacitor capacitance according to an embodiment of the present application;
FIG. 6 is a schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 7 is a schematic view of an alternative cross-sectional configuration taken along line A-A of FIG. 1;
FIG. 8 is a schematic cross-sectional view taken along line A-A of FIG. 1;
FIG. 9 is a schematic diagram of another non-target sub-pixel circuit according to an embodiment of the present application;
FIG. 10 is a flowchart illustrating a display control method for a display panel according to an embodiment of the present application;
FIG. 11 is a flow chart illustrating a method for determining capacitance according to an embodiment of the present application;
FIG. 12 illustrates a timing diagram of FIG. 2 provided in accordance with an embodiment of the present application;
fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as target and non-target, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
The embodiment of the application provides a display panel, which can be an OLED display panel. The display panel of the embodiments of the present application may be presented in various forms, some examples of which will be described below.
Fig. 1 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure. Fig. 2 is a schematic circuit diagram of a target sub-pixel according to an embodiment of the present disclosure. Fig. 3 is a schematic circuit diagram of a non-target sub-pixel according to an embodiment of the present disclosure. As shown in fig. 1 to fig. 3, a display panel 100 provided in the embodiment of the present application includes a pixel unit 10. The number of the pixel units 10 may be plural, and the plural pixel units 10 are distributed in an array. The pixel unit 10 may include at least three color sub-pixels, at least one color sub-pixel may be the target sub-pixel 11, and at least one color sub-pixel may be the non-target sub-pixel 12. In the drawings of the present application, the pixel unit 10 includes three color sub-pixels, one color sub-pixel is the target sub-pixel 11, and the other two color sub-pixels are the non-target sub-pixels 12, which is not limited to the present application.
The target sub-pixel 11 includes a target pixel circuit 01 and a target light emitting element D1, and the non-target sub-pixel 12 includes a non-target pixel circuit 02 and a non-target light emitting element D2. Fig. 2 and 3 exemplarily show that the circuit structures of the target sub-pixel 11 and the non-target sub-pixel 12 are the same.
Referring to fig. 2, the target pixel circuit 01 may include a plurality of transistors M11, M12, M13, M14, M15, M16, and M17, and a target storage capacitor Cst11, and the transistor M11 may be a target driving transistor of the target pixel circuit 01. The gate of the transistor M11 is electrically connected to the node N1, the first pole of the transistor M11 is electrically connected to the node N2, and the second pole of the transistor M11 is electrically connected to the node N3. The gate of the transistor M12 is electrically connected to the second SCAN signal terminal SCAN2, the first pole of the transistor M12 is electrically connected to the data signal terminal VDATA, and the second pole of the transistor M12 is electrically connected to the node N2. A gate of the transistor M13 is electrically connected to the first SCAN signal terminal SCAN1, a first pole of the transistor M13 is electrically connected to the reference signal terminal VREF, and a second pole of the transistor M13 is electrically connected to the node N1. The gate of the transistor M14 is electrically connected to the second SCAN signal terminal SCAN2, the first pole of the transistor M14 is electrically connected to the node N3, and the second pole of the transistor M14 is electrically connected to the node N1. A gate of the transistor M15 is electrically connected to the emission control signal terminal EM, a first pole of the transistor M15 is electrically connected to the first voltage terminal PVDD, and a second pole of the transistor M15 is electrically connected to the node N2. A gate of the transistor M16 is electrically connected to the emission control signal terminal EM, a first pole of the transistor M16 is electrically connected to the node N3, and a second pole of the transistor M15 is electrically connected to the node N4. A gate of the transistor M17 is electrically connected to the first SCAN signal terminal SCAN1, a first pole of the transistor M17 is electrically connected to the reference signal terminal VREF, and a second pole of the transistor M13 is electrically connected to the node N4. A first pole of the target storage capacitor Cst11 is electrically connected to the first voltage terminal PVDD, and a second pole of the target storage capacitor Cst11 is electrically connected to the node N1. A first pole of the target light emitting element D1 is electrically connected to the node N4, and a second pole of the target light emitting element D1 is electrically connected to the second voltage terminal PVEE.
Referring to fig. 3, the non-target pixel circuit 02 may include a plurality of transistors M21, M22, M23, M24, M25, M26, and M27, and a non-target storage capacitor Cst21, and the transistor M21 may be a non-target driving transistor of the non-target pixel circuit 02. The electrical connection of the transistors M21, M22, M23, M24, M25, M26 and M27, the non-target storage capacitor Cst21 and the non-target light emitting element D2 of the non-target pixel circuit 02 may correspond to the electrical connection of the transistors M11, M12, M13, M14, M15, M16 and M17 of the target pixel circuit 01, and the electrical connection of the target storage capacitor Cst11 and the target light emitting element D1, which will not be described herein again.
The circuit configurations shown in fig. 2 and 3 are merely examples and are not intended to limit the present application.
In some alternative embodiments, the target light-emitting element D1 and the non-target light-emitting element D2 have different luminous efficiencies. Illustratively, the luminous efficiency of the target light emitting element D1 is less than that of the non-target light emitting element D2.
For example, the voltage of the first voltage terminal PVDD may be greater than the voltage of the second voltage terminal PVEE. Generally, the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE is 7V, the voltage of the first voltage terminal PVDD is 3.5V, and the voltage of the second voltage terminal PVEE is-3.5V. In some alternative embodiments, the power consumption of the display panel may be reduced by reducing a voltage across the first voltage terminal PVDD and the second voltage terminal PVEE. For example, the voltage of the first voltage terminal PVDD is 3.3V, the voltage of the second voltage terminal PVEE is-3.3V, and the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE is 6.6V. However, the inventors of the present application have found that, although the above method reduces the power consumption of the display panel, the actual luminance of the target light emitting device at certain gray levels cannot reach the required luminance.
Specifically, according to the circuit configuration shown in fig. 2 and 3, the current formulas of the target light emitting element and the non-target light emitting element may be as in formula (1):
I＝K×(Vdd-VN1-|Vth|)E (1)
wherein I is a current, K is a constant, Vdd is a voltage of the first voltage terminal PVDD, and VN1Is the potential of node N1, VthIs the threshold voltage of the drive transistor. In the case of ideal compensation effect, VN1＝Vdata-|VthVdata is a data voltage supplied from the data signal terminal Vdata, and therefore, ideally, the current formulas of the target light emitting element and the non-target light emitting element are the following equation (2):
I＝K×(Vdd-Vdata)2 (2)
as can be seen from the equations (1) and (2), in order to ensure that the luminance of the light emitting element before and after the voltage Vdd of the first voltage terminal PVDD decreases, i.e., the value of the current I does not change, the data voltage Vdata needs to be decreased accordingly at the same gray scale. Since the light emitting efficiency of the target light emitting element D1 is lower than that of the non-target light emitting element D2, the current of the target light emitting element D1 is required to be higher than that of the non-target light emitting element D2, and the data voltage Vdata of the target light emitting element D1 is required to be lower than that of the non-target light emitting element D2 at the same gray scale. The data voltage Vdata is usually supplied by a driving chip, and the driving chip generally cannot supply the negative data voltage Vdata, so that the actual luminance of the target light emitting element D1 at some gray scales cannot reach the required luminance. For example, at the 255 gray scale, even if the data voltage Vdata of the target light emitting element D1 is reduced to 0V, the actual luminance of the target light emitting element D1 cannot reach the required luminance at the 255 gray scale.
The inventors of the present application have found that the magnitude of the storage capacitor in the sub-pixel affects the gate potential of the driving transistor, i.e., the potential of the node N1, and thus the magnitude of the current. Specifically, fig. 4 shows the corresponding relationship between the gate potential of the driving transistor and the capacity of the storage capacitor under the same data voltage Vdata and the same shorter data writing duration, for example, the data writing duration is less than or equal to 24 us. The gate potential of the driving transistor is the potential of the node N1. It can be seen that, under the same data voltage Vdata, the larger the capacity of the storage capacitor is, the lower the gate potential of the driving transistor of the sub-pixel is, and the lower the gate potential of the driving transistor is, the larger the driving current flowing through the sub-pixel is, and thus the larger the luminance of the sub-pixel is. Fig. 5 shows the corresponding relationship between the data voltage and the capacity of the storage capacitor under the same current and the same short data writing duration, for example, the data writing duration is less than or equal to 24 us. As can be seen, the data voltage Vdata is increased, and the capacity of the storage capacitor is also increased, so that the currents can be made the same. That is, the data voltage Vdata is increased and the capacity of the storage capacitor is also increased, so that the potential of the node N1 can be made the same.
It is to be understood that the data writing period in the above is a period in which the data voltage supplied from the data signal terminal can be written to the gate of the driving transistor.
In the embodiment of the present application, the capacity of the target storage capacitor Cst11 is greater than the capacity of the non-target storage capacitor Cst12, and the capacity of the target storage capacitor Cst11 is equal to the capacity of the non-target storage capacitor Cst12, on one hand, under the same data voltage, the capacity of the target storage capacitor Cst11 is equal to the capacity of the non-target storage capacitor, and in the embodiment of the present application, the capacity of the target storage capacitor is greater than the capacity of the non-target storage capacitor, so that the current of the target sub-pixel can be increased, and further the luminance of the target sub-pixel can be increased; on the other hand, under the same gate potential of the target driving transistor, that is, under the same driving current, with respect to the capacity of the target storage capacitor being equal to the capacity of the non-target storage capacitor, the capacity of the target storage capacitor in the embodiment of the present application is greater than the capacity of the non-target storage capacitor, since the charging speed is slower as the capacity of the capacitor is larger, the data voltage provided by the data signal terminal to the target sub-pixel needs to be increased, so as to increase the data voltage actually written to the gate of the driving transistor of the target sub-pixel, which is equivalent to increasing the down-regulation range of the data voltage corresponding to the target sub-pixel, so that when the target sub-pixel needs to have higher luminance, the data voltage corresponding to the target sub-pixel can be further reduced, and therefore, the purpose of reducing power consumption can be achieved while reducing the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE, the problem that the brightness of the target sub-pixel cannot reach the required brightness is solved.
To better understand the effect of increasing the capacity of the target storage capacitor Cst11 in this application, a specific example is given below. For example, when the voltage between the first voltage terminal PVDD and the second voltage terminal PVEE is decreased and the capacity of the storage capacitor Cst11 is not increased, that is, the capacity of the storage capacitor Cst11 is equal to the capacity of the storage capacitor Cst12, at the gray level 255, if the data voltage Vdata corresponding to the target sub-pixel is 0.1V, the actual luminance of the target sub-pixel can reach the required luminance corresponding to the gray level 255; when the capacity of the target storage capacitor Cst11 is increased, that is, when the capacity of the target storage capacitor Cst11 is greater than the capacity of the non-target storage capacitor Cst12, and also when the data voltage Vdata corresponding to the target sub-pixel is 0.3V at the 255 gray scale, the actual luminance can reach the required luminance corresponding to the 255 gray scale, because the capacity of the storage capacitor is increased, and the charging speed is slower as the capacity of the capacitor is larger, the data voltage provided by the data signal terminal to the target sub-pixel needs to be increased to make the current the same, that is, the actual luminance the same.
Under the condition of reducing the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE, and when the capacity of the target storage capacitor Cst11 is not increased, that is, when the capacity of the target storage capacitor Cst11 is equal to the capacity of the non-target storage capacitor Cst12, at the 255 gray scale, if the data voltage Vdata corresponding to the target sub-pixel is 0.1V, the actual luminance cannot reach the required luminance corresponding to the 255 gray scale, the data voltage Vdata needs to be further reduced, and since the driving chip cannot provide the negative data voltage Vdata, the adjustable range is within 0.1V, even if the data voltage Vdata is reduced to 0V, the target sub-pixel cannot reach the required luminance corresponding to the 255 gray scale. After the capacity of the target storage capacitor Cst11 is increased, that is, when the capacity of the target storage capacitor Cst11 is greater than the capacity of the non-target storage capacitor Cst12, and also when the data voltage Vdata corresponding to the target sub-pixel is 0.3V at the 255 gray scale, the actual luminance cannot reach the required luminance corresponding to the 255 gray scale, the data voltage Vdata needs to be further reduced, and since the driving chip cannot provide the negative data voltage Vdata, the adjustable range of the data voltage Vdata is within 0.3V, compared with the case that the capacity of the target storage capacitor Cst11 is not increased, the adjustable range of the data voltage Vdata can be increased by increasing the capacity of the target storage capacitor Cst11, so that the possibility that the luminance of the target sub-pixel can reach the required luminance is increased.
It should be understood that the data in the above examples are only used for understanding the present application, and are not used to limit the present application.
In some alternative embodiments, the target light emitting element D1 may include a blue organic light emitting diode, and the non-target light emitting element D2 includes at least one of a red organic light emitting diode and a green organic light emitting diode. The light emitting efficiency of the blue organic light emitting diode is lower than that of the red organic light emitting diode and the green organic light emitting diode, so that the capacity of the storage capacitor corresponding to the blue organic light emitting diode is set to be larger than that of the storage capacitor corresponding to the red organic light emitting diode and/or the green organic light emitting diode, the purpose of reducing power consumption can be achieved by reducing the voltage across the first voltage end PVDD and the second voltage end PVEE, and the problem that the brightness of the blue organic light emitting diode cannot achieve the required brightness is solved.
In some alternative embodiments, the purpose of increasing the capacity of the target storage capacitor Cst11 may be achieved by at least one of the following ways. Increasing the plate area of the target storage capacitor Cst11, increasing the plate pitch of the target storage capacitor Cst11, and increasing the dielectric constant of the insulating layer between the plates of the target storage capacitor Cst 11.
In some alternative embodiments, the plate area of the target storage capacitor Cst11 may be set to be larger than the plate area of the non-target storage capacitor Cst21, thereby achieving a larger capacity of the target storage capacitor Cst11 than the non-target storage capacitor Cst 21. As shown in fig. 6, the target storage capacitor Cst11 includes a first plate C01 and a second plate C02, and the non-target storage capacitor Cst21 includes a third plate C03 and a fourth plate C04. For example, the areas of the first plate C01 and the second plate C02 may be increased at the same time, so as to increase the facing areas of the first plate C01 and the second plate C02, and the facing areas of the first plate C01 and the second plate C02 may be understood as the overlapping areas of the orthographic projections of the first plate C01 and the second plate C02 on the light-emitting surface of the display panel.
For example, the areas of the first plate C01 and the second plate C02 may be equal, the areas of the third plate C03 and the fourth plate C04 may be equal, and the areas of the first plate C01 and the second plate C02 are greater than the areas of the third plate C03 and the fourth plate C04. For another example, the areas of the first plate C01 and the third plate C03 may be equal, and the area of the second plate C02 may be greater than the area of the fourth plate C04.
With continued reference to fig. 2, 3, 6 or 7, the target pixel circuit 01 includes a target driving transistor M11. The target driving transistor M11 includes a target gate g 1. The non-target pixel circuit 02 includes a non-target drive transistor M21, and the non-target drive transistor M21 includes a non-target gate g 2. It is understood that the target driving transistor M11 may further include a source s1 and a drain d1, and the non-target driving transistor M21 may further include a source s2 and a drain d 2.
In some alternative embodiments, as shown in fig. 6, the first plate C01, the third plate C03, the target gate g1 and the non-target gate g2 may be disposed in the same layer and have the same material. The second and fourth polar plates C02 and C04 may be disposed in the same layer and have the same material. For example, the target driving transistor M11 and the non-target driving transistor M21 may both be a top gate structure.
In other alternative embodiments, as shown in fig. 7, the first plate C01 may be multiplexed as a target gate g1, and the third plate C03 may be multiplexed as a non-target gate g 2. Thus, the structure of the display panel can be simplified.
For example, in the case that the first plate C01 is reused as the target gate g1 and the third plate C03 is reused as the non-target gate g2, the area of the first plate C01 may be larger than that of the third plate C03, the area of the second plate C02 may be equal to that of the fourth plate C04, and the area of the second plate C02 is equal to or larger than that of the first plate C01, so that the capacity of the target storage capacitor Cst11 is larger than that of the non-target storage capacitor Cst 21.
For example, in the case that the first plate C01 is reused as the target gate g1, and the third plate C03 is reused as the non-target gate g2, the first plate C01 and the third plate C03 are disposed in the same layer, and the second plate C02 and the fourth plate C04 are disposed in the same layer, that is, the target gate g1 and the non-target gate g2 are disposed in the same layer, and the plate pitch of the target storage capacitor Cst11 is equal to the plate pitch of the non-target storage capacitor Cst 21. By arranging the second plate C02 and the fourth plate C04 in the same layer and in the same area, the second plate C02 and the fourth plate C04 can be formed simultaneously in the same process, thereby simplifying the process steps.
In some alternative embodiments, the plate pitch of the target storage capacitor Cst11 may be set to be smaller than the plate pitch of the non-target storage capacitor Cst 21. As shown in fig. 8, the first plate C01 may be disposed at the same layer as the target gate g1, and the second plate C02 may be located between the source s1, the drain d1 and the target gate g1 of the target drive transistor M11. The third plate C01 may be disposed at the same layer as the non-target gate g2, and the fourth plate C04 may be disposed at the same layer as the source s2 and the drain d2 of the non-target driving transistor M21. The target gate g1 and the non-target gate g2 are disposed on the same layer, and the source s1, the drain d1, the source s2 and the drain d2 are disposed on the same layer.
As shown in any one of fig. 6 to 8, the display panel may further include a substrate 20 and a driving device layer 30. A driving device layer 30 is disposed at one side of the substrate 10, and target pixel circuits 01 and non-target pixel circuits 02 are disposed in the driving device layer 30. The target light emitting element D1 and the non-target light emitting element D2 are disposed on a side of the driving device layer 30 opposite to the substrate 10. The target driving transistor M11 includes a target active layer b1, and the non-target driving transistor M21 includes a non-target active layer b 2. Illustratively, the driving device layer 30 includes a first insulating layer 31, a second insulating layer 32, a third insulating layer 33, a fourth insulating layer 34, and a planarization layer 35. The first insulating layer 31 is located between the target active layer b1 and the target gate g1, the second insulating layer 32 is located between the second substrate C02 and the target gate g1, the third insulating layer 33 is located between the second insulating layer 32 and the source s1 and the drain D1, the fourth insulating layer 34 is used for insulating the source s1 and the drain D1, and the planarization layer 35 is located between the fourth insulating layer 34 and the first electrodes D11 and D21.
In some alternative embodiments, as shown in fig. 6, a dielectric constant between the second insulating layer 32 between the first plate C01 and the second plate C02 of the target storage capacitor Cst11 may be greater than a dielectric constant of the second insulating layer 32 between the third plate C03 and the fourth plate C04 of the non-target storage capacitor Cst121, so that the capacity of the target storage capacitor Cst11 is greater than the capacity of the non-target storage capacitor Cst 121.
In some alternative embodiments, in the case where the data writing time period is 8us to 16us, the difference between the capacity of the target storage capacitor Cst11 and the capacity of the non-target storage capacitor Cst21 is in the range of 30 picofarads to 60 picofarads. Therefore, under the same gray scale, the data voltage of the target light-emitting element can be increased to be relatively close to the data voltage of the non-target light-emitting element, and the current of the target light-emitting element is ensured to be larger than that of the non-target light-emitting element.
It can be understood that, in the case where the data writing period is long enough, the gate of the driving transistor can be charged to the same potential under the same data voltage supplied from the data signal terminal regardless of the capacity of the storage capacitor. In addition, the smaller the data writing period, the smaller the range of the difference between the capacity of the target storage capacitor Cst11 and the capacity of the non-target storage capacitor Cst21 can be set, and the larger the data writing period, the larger the range of the difference between the capacity of the target storage capacitor Cst11 and the capacity of the non-target storage capacitor Cst21 can be set.
In some alternative embodiments, referring to fig. 1, 3 and 9, the non-target sub-pixel 12 includes a first non-target sub-pixel 121 and a second non-target sub-pixel 122, the first non-target sub-pixel 121 includes a first non-target pixel circuit 02 and a first non-target light emitting element D2, the second non-target sub-pixel 122 includes a second non-target pixel circuit 02 'and a second non-target light emitting element D2', the first non-target pixel circuit 02 includes a first non-target storage capacitor Cst21, and the second non-target pixel circuit 02 'includes a second non-target storage capacitor Cst 21'. The target light emitting element D1 includes a blue organic light emitting diode, the first non-target light emitting element D2 includes a green organic light emitting diode, the second non-target light emitting element D2 'includes a red organic light emitting diode, and the capacity of the first non-target storage capacitor Cst21 is greater than the capacity of the second non-target storage capacitor Cst 21'.
The green organic light emitting diode has a lower light emitting efficiency than the red organic light emitting diode, and thus, the current of the first non-target light emitting element D2 needs to be higher than the current of the second non-target light emitting element D2 'and the data voltage Vdata of the first non-target light emitting element D2 needs to be lower than the data voltage Vdata of the second non-target light emitting element D2' at the same gray scale. Therefore, the actual brightness of the second non-target light emitting device D2' at some gray levels may not reach the required brightness. For example, at the 255 gray scale, even if the data voltage Vdata of the second non-target light emitting element D2 'is reduced to 0V, the actual luminance of the second non-target light emitting element D2' cannot reach the required luminance at the 255 gray scale.
In the embodiment of the present application, the capacity of the first non-target storage capacitor Cst21 is greater than the capacity of the second non-target storage capacitor Cst 21', that is, the capacity of the first non-target storage capacitor Cst21 is increased, which is equivalent to increasing the adjustable range of the data voltage corresponding to the first non-target sub-pixel, so that when the first non-target sub-pixel needs to have higher luminance, the data voltage corresponding to the first non-target sub-pixel can be further reduced, and therefore, the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE can be reduced to achieve the purpose of reducing power consumption, and at the same time, the problem that the luminance of the first non-target sub-pixel cannot reach the required luminance is solved.
Illustratively, the second non-target storage capacitor Cst 21' includes a fifth plate C05 and a sixth plate C06, and the capacity of the first non-target storage capacitor Cst21 may be increased in a manner that the capacity of the target storage capacitor Cst11 is increased as described above. It is understood that the capacitance relationship of the three storage capacitors may be that the capacitance of the target storage capacitor Cst11 is greater than the capacitance of the first non-target storage capacitor Cst21, and the capacitance of the first non-target storage capacitor Cst21 is greater than the capacitance of the second non-target storage capacitor Cst 21'.
In addition, as shown in any one of fig. 6 to 8, the first non-target pixel circuit 02 includes a first non-target driving transistor M21, the first non-target driving transistor M21 includes a first non-target active layer b2, a first non-target gate g2, a source s2 and a drain d2, the second non-target pixel circuit 02 ' includes a second non-target driving transistor M21 ', and the second non-target driving transistor M21 ' includes a second non-target active layer b2 ', a second non-target gate g2 ', a source s2 ' and a drain d2 '. The structures of the first non-target driving transistor M21, the second non-target driving transistor M21', and the target driving transistor M11 may be the same.
In addition, the object light emitting element D1 includes a first electrode D11, a light emitting layer D12, and a second electrode D13, the first non-object light emitting element D2 includes a first electrode D21, a light emitting layer D22, and a second electrode D23, and the second non-object light emitting element D2 'includes a first electrode D21', a light emitting layer D22 ', and a second electrode D23'. The display panel may further include a pixel defining layer 40, and the pixel defining layer 40 includes a plurality of openings K for defining the light emitting layers D12 and D22.
Fig. 6 to 8 are merely examples, and do not limit the present application.
The embodiment of the present application further provides a display control method for a display panel, which is used for controlling the display panel according to any one of the above embodiments. As shown in fig. 10, the display control method of the display panel provided in the embodiment of the present application includes step 110.
Step 110, providing a target data voltage to the target sub-pixel and providing a non-target data voltage to the non-target sub-pixel under the same gray scale, wherein the difference between the non-target data voltage and the target data voltage is less than or equal to 0.2V.
In the case where the capacity of the target storage capacitor Cst11 is equal to the capacity of the non-target storage capacitor Cst21, the difference between the non-target data voltage and the target data voltage is usually 0.4V or more in order to ensure that the current of the target sub-pixel is greater than the current of the non-target sub-pixel. In the embodiment of the present application, since the capacitance of the target storage capacitor Cst11 is greater than the capacitance of the non-target storage capacitor Cst21, that is, the capacitance of the target storage capacitor Cst11 is increased, and the target data voltage is increased, so that the current of the target sub-pixel is not changed before and after the capacitance of the target storage capacitor Cst11 is increased, therefore, in the embodiment of the present application, the difference between the non-target data voltage and the target data voltage is less than or equal to 0.2V, and the adjustable range of the data voltage corresponding to the target sub-pixel can be increased, so that when the target sub-pixel needs to have higher luminance, the data voltage corresponding to the target sub-pixel can be further decreased, and therefore, the purpose of reducing power consumption can be achieved by decreasing the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE, and the problem that the luminance of the target sub-pixel cannot reach the required luminance is improved.
For example, the target data voltage corresponding to the target sub-pixel may be adjusted to be equal to the non-target data voltage corresponding to the non-target sub-pixel, that is, the difference between the non-target data voltage and the target data voltage is 0.
The embodiment of the present application further provides a method for determining a capacitance capacity, which is used to determine a difference between a capacity of a target storage capacitor and a capacity of a non-target storage capacitor in a display panel according to the above embodiment, where a target pixel circuit includes a target driving transistor, and the target driving transistor includes a target gate. As shown in fig. 11, the method for determining capacitance provided by the embodiment of the present application includes steps 210 to 220.
Step 210, acquiring a data voltage difference between the non-target sub-pixel and the target sub-pixel when the capacity of the target storage capacitor is equal to the capacity of the non-target storage capacitor at the same gray scale, and acquiring a corresponding relationship between the capacity of the target storage capacitor, the data voltage, and the potential of the target gate.
Step 220, determining the difference between the capacity of the target storage capacitor and the capacity of the non-target storage capacitor according to the data voltage difference and the corresponding relation.
In the embodiment of the application, the difference value between the capacity of the target storage capacitor and the capacity of the non-target storage capacitor is determined according to the data voltage difference value and the corresponding relation, so that the current of the target light-emitting element can be ensured to be larger than that of the non-target light-emitting element when the data voltage of the target light-emitting element is increased to be closer to the data voltage of the non-target light-emitting element under the same gray scale,
in some optional embodiments, the correspondence relationship between the capacity of the target storage capacitor, the data voltage and the potential of the target gate includes: under the same data voltage, the potential of the target grid electrode is in a linear relation with the capacity of the target storage capacitor, the potential of the target grid electrode is reduced along with the increase of the capacity of the target storage capacitor, and under the potential of the same target grid electrode, the capacity of the target storage capacitor is in a linear relation with the data voltage, and the data voltage is increased along with the increase of the capacity of the target storage capacitor.
For example, when the capacity of the target storage capacitor is equal to the capacity of the non-target storage capacitor at a gray scale of 255, the difference between the data voltages of the non-target sub-pixel and the target sub-pixel is 0.4V, and the data voltage of the target sub-pixel may be increased by 0.2V to 0.4V, so that the difference between the data voltages of the non-target sub-pixel and the target sub-pixel is less than or equal to 0.2V. For example, in the case where the potential of the node N1 changes by 0.01V and the capacitance of the target storage capacitor needs to change by 1.5 picofarads for the same data voltage, the capacitance of the target storage capacitor needs to increase by 30 picofarads to 60 picofarads when the data voltage of the target subpixel is increased by 0.2V to 0.4V in order to ensure that the potential of the target gate of the target subpixel is not changed even when the data voltage of the target subpixel is increased. Therefore, the current of the target sub-pixel can be larger than that of the non-target sub-pixel although the data voltage of the target sub-pixel is increased.
In some alternative embodiments, a plurality of target pixel circuits may be provided, and the target storage capacitors in each target pixel circuit have different capacities, different data voltages may be provided to the target pixel circuits, the potentials of the target gates in the target pixel circuits at the different data voltages may be measured, so as to obtain the capacities of the different target storage capacitors and the potentials of the target gates at the different data voltages, and the corresponding relationship between the capacities of the target storage capacitors, the data voltages, and the potentials of the target gates may be determined according to the capacities of the different target storage capacitors and the potentials of the target gates at the different data voltages.
In other alternative embodiments, the correspondence between the capacity of the target storage capacitor, the data voltage, and the potential of the target gate may be determined as follows.
Taking the transistors of the target pixel circuit as P-type transistors as an example, the transistor M11 is a target driving transistor. Stage T1 is an initialization stage, and during stage T1, the reference voltage signal VREF provided by the reference signal terminal VREF is written into the gate of the transistor M11. The stage T2 is a data writing stage, in which the data voltage VDATA provided by the data voltage terminal VDATA is written into the gate of the transistor M11.
It is understood that at time T0, i.e., the beginning of the T2 phase, the gate of the transistor M11 is at Vref. During the period T2, the current formula of the transistor M11 is as follows (3):
I＝K×(Vsg-|Vth|)2 (3)
wherein I is current, K is constant, VthFor the threshold voltage of the transistor M11, Vsg is Vdata-VN1。
After the time period t, the formula of the charge amount Q flowing to the node N1 through the transistor M11 is as follows (4):
Figure BDA0002842701890000151
from the charge amount Q ═ Cst11 × Δ V, formula (5) can be obtained:
Figure BDA0002842701890000152
the stage T2 can be divided into a plurality of stages according to equation (5), each stage has a certain duration, the potential of the node N1 at the end of the stage T2 is calculated by means of integration, and the potential of the node N1 at the end of the stage T2 is the final potential of the node N1.
For example, at time t1 after time t0, with time t0 being 0, the potential change Δ V1 of the node N1 can be calculated from equation (6):
Figure BDA0002842701890000153
at this time, VN1(t1)＝Vref+ΔV1。
For example, at time t2 after time t1, the potential change Δ V1 of the node N1 can be calculated from equation (6):
Figure BDA0002842701890000154
at this time, VN1(t2)＝VN1(t1)+ΔV2。
By analogy, the potential of the node N1 at the end time of the T2 phase can be calculated according to equation (7):
VN1＝VN1(tn)+ΔV(n-1) (7)
the T2 stage is divided into a plurality of stages, and the potential of the node N1 is calculated in an integral mode, so that the obtained calculation result is accurate.
For example, different values of Cst11 and different values of Vdata may be set, and the above integration method is used to calculate the potential V of the node N1 under different values of Cst11 and different values of VdataN1Therefore, according to the capacities of different target storage capacitors and the potentials of the target grid electrodes under different data voltages, the corresponding relation among the capacity of the target storage capacitor, the data voltage and the potential of the target grid electrode is determined.
According to the embodiment of the application, the design of target pixel circuits with different target storage capacitors can be avoided, the corresponding relation can be determined only by computer software, the efficiency can be improved, and the cost can be reduced.
In some optional embodiments, after the correspondence relationship can be determined by using computer software, the correspondence relationship determined by the computer software may be tested by using an actual pixel circuit to detect whether the correspondence relationship determined by the computer software is correct, so that the accuracy of the correspondence relationship can be improved while time is saved, and the setting accuracy of the storage capacitor capacity can be improved.
The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 13, fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Fig. 13 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 13 by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims (13)

1. A display panel, comprising:
a pixel unit including a target sub-pixel and a non-target sub-pixel, the target sub-pixel including a target pixel circuit and a target light emitting element, the target pixel circuit including a target storage capacitance, the non-target sub-pixel including a non-target pixel circuit and a non-target light emitting element, the non-target pixel circuit including a non-target storage capacitance;
wherein the capacity of the target storage capacitor is greater than the capacity of the non-target storage capacitor;
under the same gray scale, the difference value of the target data voltage provided for the target sub-pixel and the non-target data voltage provided for the non-target sub-pixel is less than or equal to 0.2V;
the target pixel circuit comprises a target drive transistor comprising a target gate;
the difference value between the capacity of the target storage capacitor and the capacity of the non-target storage capacitor is determined according to the corresponding relation between the capacity of the target storage capacitor, the data voltage and the potential of the target gate and the data voltage difference value, and the data voltage difference value is the data voltage difference value between the non-target sub-pixel and the target sub-pixel when the capacity of the target storage capacitor is equal to the capacity of the non-target storage capacitor at the same gray scale.
2. The display panel according to claim 1, wherein the target light-emitting element comprises a blue organic light-emitting diode;
the non-target light emitting element includes at least one of a red organic light emitting diode and a green organic light emitting diode.
3. The display panel according to claim 1, wherein a plate facing area of the target storage capacitor is larger than a plate facing area of the non-target storage capacitor.
4. The display panel according to claim 3, wherein the target pixel circuit comprises a target drive transistor comprising a target gate;
the target storage capacitor comprises a first polar plate and a second polar plate, and the first polar plate is reused as the target grid;
the non-target pixel circuit comprises a non-target drive transistor comprising a non-target gate;
the non-target storage capacitor comprises a third polar plate and a fourth polar plate, and the third polar plate is multiplexed as the non-target grid;
the area of the first polar plate is larger than that of the third polar plate, the area of the second polar plate is equal to that of the fourth polar plate, and the area of the second polar plate is larger than that of the first polar plate.
5. The display panel according to claim 4, wherein the first electrode plate and the third electrode plate are disposed in the same layer, and the second electrode plate and the fourth electrode plate are disposed in the same layer.
6. The display panel of claim 1, wherein the plate spacing of the target storage capacitor is smaller than the plate spacing of the non-target storage capacitors.
7. The display panel of claim 1, wherein the target storage capacitor comprises a first plate and a second plate, wherein the non-target storage capacitor comprises a third plate and a fourth plate, and wherein a dielectric constant of an insulating layer between the first plate and the second plate is greater than a dielectric constant of an insulating layer between the third plate and the fourth plate.
8. The display panel according to claim 1, wherein a difference between the capacity of the target storage capacitor and the capacity of the non-target storage capacitor is in a range of 30 picofarads to 60 picofarads.
9. The display panel according to claim 1, wherein the non-target sub-pixel comprises a first non-target sub-pixel and a second non-target sub-pixel, the first non-target sub-pixel comprises a first non-target pixel circuit and a first non-target light emitting element, the second non-target sub-pixel comprises a second non-target pixel circuit and a second non-target light emitting element, the first non-target pixel circuit comprises a first non-target storage capacitor, and the second non-target pixel circuit comprises a second non-target storage capacitor;
wherein the target light emitting element comprises a blue organic light emitting diode, the first non-target light emitting element comprises a green organic light emitting diode, the second non-target light emitting element comprises a red organic light emitting diode, and the capacity of the first non-target storage capacitor is greater than the capacity of the second non-target storage capacitor.
10. A display control method of a display panel for controlling the display panel according to any one of claims 1 to 9, the method comprising:
and under the same gray scale, providing a target data voltage for the target sub-pixel, and providing a non-target data voltage for the non-target sub-pixel, wherein the difference between the non-target data voltage and the target data voltage is less than or equal to 0.2V.
11. A capacitance capacity determination method for determining a difference between a capacity of the target storage capacitor and a capacity of the non-target storage capacitor in the display panel according to any one of claims 1 to 9, the target pixel circuit including a target drive transistor including a target gate, the method comprising:
acquiring a data voltage difference value of the non-target sub-pixel and the target sub-pixel when the capacity of the target storage capacitor is equal to that of the non-target storage capacitor under the same gray scale, and acquiring a corresponding relation among the capacity of the target storage capacitor, the data voltage and the potential of the target grid;
and determining the difference value between the capacity of the target storage capacitor and the capacity of the non-target storage capacitor according to the data voltage difference value and the corresponding relation.
12. The method of claim 11, wherein the correspondence relationship comprises: under the same data voltage, the potential of the target grid electrode is in a linear relation with the capacity of the target storage capacitor, the potential of the target grid electrode is reduced along with the increase of the capacity of the target storage capacitor, and under the potential of the same target grid electrode, the capacity of the target storage capacitor is in a linear relation with the data voltage, and the data voltage is increased along with the increase of the capacity of the target storage capacitor.
13. A display device comprising the display panel according to any one of claims 1 to 9.
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