CN112435628A - Display panel, display control method thereof, duty ratio adjusting method and display device - Google Patents

Display panel, display control method thereof, duty ratio adjusting method and display device Download PDF

Info

Publication number
CN112435628A
CN112435628A CN202011502657.XA CN202011502657A CN112435628A CN 112435628 A CN112435628 A CN 112435628A CN 202011502657 A CN202011502657 A CN 202011502657A CN 112435628 A CN112435628 A CN 112435628A
Authority
CN
China
Prior art keywords
sub
target
module
transistor
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011502657.XA
Other languages
Chinese (zh)
Other versions
CN112435628B (en
Inventor
张蒙蒙
周星耀
李玥
高娅娜
匡立莲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan Tianma Microelectronics Co Ltd
Original Assignee
Shanghai Tianma AM OLED Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Tianma AM OLED Co Ltd filed Critical Shanghai Tianma AM OLED Co Ltd
Priority to CN202011502657.XA priority Critical patent/CN112435628B/en
Publication of CN112435628A publication Critical patent/CN112435628A/en
Application granted granted Critical
Publication of CN112435628B publication Critical patent/CN112435628B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements

Abstract

The application discloses a display panel, a display control method, a duty ratio adjusting method and a display device thereof. The display panel comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels, each sub-pixel comprises a pixel circuit and a light-emitting element, the pixel circuit comprises an enabling module and a dimming module, the enabling module and the light-emitting element are connected between a first voltage end and a second voltage end in series, and the light-emitting element and the dimming module are connected between the enabling module and the second voltage end in parallel; the dimming module is used for adjusting the light emitting duration of the light emitting element. According to the embodiment of the application, the structure is simple, and the display panel can be easily adjusted in light.

Description

Display panel, display control method thereof, duty ratio adjusting method and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel, a display control method of the display panel, a method for adjusting a duty ratio of a dimming control signal, and a display device.
Background
An Organic Light Emitting Diode (OLED) display panel has many advantages of self-luminescence, low driving voltage, high luminous efficiency, short response time, high definition and contrast, a viewing angle of nearly 180 degrees, a wide range of use temperature, and capability of realizing flexible display and large-area full-color display, and is considered as a display device having the most potential for development in the industry.
In the prior art, a Pulse Width Modulation (PWM) driving circuit is widely used to control the duration of the driving current of the pixel unit, however, the structure of the PWM driving circuit is complicated, which is not favorable for dimming the OLED display panel.
Disclosure of Invention
The application provides a display panel, a display control method, a duty ratio adjusting method and a display device, which are simple in structure and can easily realize dimming of the display panel.
In a first aspect, an embodiment of the present application provides a display panel, which includes a plurality of pixel units, each pixel unit includes a plurality of sub-pixels, each sub-pixel includes a pixel circuit and a light emitting element, the pixel circuit includes an enable module and a dimming module, the enable module and the light emitting element are connected in series between a first voltage terminal and a second voltage terminal, and the light emitting element and the dimming module are connected in parallel between the enable module and the second voltage terminal; the dimming module is used for adjusting the light emitting duration of the light emitting element.
In a second aspect, an embodiment of the present application provides a display control method for a display panel, for controlling the display panel according to the embodiment of the first aspect, the method including: and controlling the time length of the dimming module in the turn-off state so as to adjust the light emitting time length of the light emitting element.
In a third aspect, an embodiment of the present application provides a method for adjusting a duty ratio of a dimming control signal, for adjusting a duty ratio of an off level of a dimming control signal received by a dimming module in a display panel as in the embodiment of the first aspect, the method includes: determining a target charging time length of the capacitor of the light-emitting element of the target sub-pixel according to the voltage across, the capacitance value and the current value of the light-emitting element of the target sub-pixel; determining the non-target charging time of the capacitor of the non-light-emitting element of the target sub-pixel according to the voltage, the capacitance and the current value of the light-emitting element of the non-target sub-pixel; and adjusting the duty ratio of the cut-off level of the dimming control signal received by the dimming module of the target sub-pixel and adjusting the duty ratio of the cut-off level of the dimming control signal received by the dimming module of the non-target sub-pixel.
In a fourth aspect, an embodiment of the present application provides a display device, which includes the display panel as in the first aspect.
In the embodiment of the application, because the dimming module is connected in parallel with the light-emitting element, when the dimming module is in a cut-off state, the driving current generated by the enabling module can completely flow through the light-emitting element, and at the moment, the light-emitting element can emit light; when the dimming module is in a conducting state, namely the light-emitting element is in a short circuit, most of the driving current generated by the enabling module flows into the dimming module, and the light-emitting element cannot emit light at the moment; therefore, the light emitting duration of the light emitting element can be adjusted by only arranging the light dimming module connected with the light emitting element in parallel and controlling the duration of the light dimming module in the cut-off state, so that the structure is simpler, and the light dimming of the display panel can be easily realized.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.
Fig. 1 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure;
FIG. 3 is a schematic current diagram of a sub-pixel of each color at a high gray level according to an embodiment of the present application;
FIG. 4 is a schematic current diagram of a sub-pixel of each color in low gray scale according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating dimming control signals corresponding to color sub-pixels according to an embodiment of the present disclosure;
FIG. 6 is a schematic circuit diagram of a sub-pixel according to another embodiment of the present disclosure;
FIG. 7 is a schematic circuit diagram of a sub-pixel according to another embodiment of the present disclosure;
FIG. 8 is a schematic circuit diagram of a sub-pixel according to another embodiment of the present disclosure;
FIG. 9 shows a timing diagram of FIG. 8;
FIG. 10 is a schematic circuit diagram of a sub-pixel according to another embodiment of the present application;
FIG. 11 is a schematic circuit diagram of a sub-pixel according to another embodiment of the present application;
FIG. 12 shows a timing diagram of FIG. 10;
FIG. 13 is a schematic top view of a display panel according to another embodiment of the present application;
fig. 14 is a flowchart illustrating a display control method for a display panel according to an embodiment of the present application;
fig. 15 is a flowchart illustrating a method for adjusting a duty ratio of a dimming control signal according to an embodiment of the present application;
fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It is noted that, herein, relational terms such as target and non-target, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.
The embodiment of the application provides a display panel, which can be an OLED display panel. The display panel of the embodiments of the present application may be presented in various forms, some examples of which will be described below.
Fig. 1 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure. Fig. 2 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure. As shown in fig. 1 and fig. 2, a display panel 100 provided in the embodiment of the present application includes a pixel unit PU. The number of the pixel units PU may be multiple, and the multiple pixel units PU are distributed in an array. Each pixel unit PU includes a plurality of subpixels P. Illustratively, each pixel unit PU may include at least three color sub-pixels. Each pixel unit PU is exemplarily shown in fig. 1 to include three color sub-pixels, which is not intended to limit the present application.
Each sub-pixel P includes a pixel circuit 10 and a light emitting element D. The pixel circuit 10 includes an enable module 01 and a dimming module 02. The enable module 01 and the light emitting element D are connected in series between the first voltage terminal PVDD and the second voltage terminal PVEE, and the light emitting element D and the dimming module 02 are connected in parallel between the enable module 01 and the second voltage terminal PVEE. The dimming module 02 is used for adjusting the light emitting duration of the light emitting element D.
In the embodiment of the application, since the dimming module 02 is connected in parallel with the light emitting element D, when the dimming module 02 is in an off state, all the driving current generated by the enabling module 01 flows into the light emitting element D, and at this time, the light emitting element D can emit light; when the dimming module 02 is in a conducting state, namely the light emitting element D is short-circuited, most of the driving current generated by the enabling module 01 flows into the dimming module 02, and at this time, the light emitting element D cannot emit light; therefore, the dimming module 02 connected in parallel with the light emitting element D is only needed to be arranged, and the light emitting duration of the light emitting element D can be adjusted by controlling the duration of the off state of the dimming module 02, so that the structure is simpler, and the dimming of the display panel can be easily realized.
For example, the voltage of the first voltage terminal PVDD may be greater than the voltage of the second voltage terminal PVEE. The voltage across the first voltage terminal PVDD and the second voltage terminal PVEE can be 7V, for example, the voltage of the first voltage terminal PVDD is 3.5V, and the voltage of the second voltage terminal PVEE is-3.5V. In some alternative embodiments, the power consumption of the display panel may be reduced by reducing a voltage across the first voltage terminal PVDD and the second voltage terminal PVEE. For example, the voltage of the first voltage terminal PVDD is 3.3V, and the voltage of the second voltage terminal PVEE is-3.3V, i.e., the voltage across the first voltage terminal PVDD and the second voltage terminal PVEE may be 6.6V.
Illustratively, the enabling module 01 may receive the emission control signal emit. Taking a low level of the light-emitting control signal emit as an on level, a high level of the light-emitting control signal emit as an off level, and taking a pixel circuit without a dimming module 02 as an example, please refer to fig. 3 and 4, where fig. 3 is a schematic current diagram of a sub-pixel of each color at a high gray level, fig. 4 is a schematic current diagram of a sub-pixel of each color at a low gray level, and when the light-emitting control signal emit is at a high level, a current of the light-emitting element D is 0, and the light-emitting element does not emit light; when the light emission control signal emit is at a low level, the anode of the light emitting element D is gradually charged to a normal operating potential, the current of the light emitting element D gradually reaches a normal operating current, and the light emitting element D emits light. However, the inventors of the present application have found that, due to the difference in the current of the sub-pixels of the respective colors and the difference in the capacitance of the light emitting element itself in the sub-pixels of the respective colors at the same gray scale, the lighting periods of the sub-pixels of the different colors are different, that is, the charging periods of the capacitances of the sub-pixels of the different colors are different. As shown in fig. 3 and 4, the red sub-pixel R and the blue sub-pixel B will start to light first, and the green sub-pixel G will start to light later, i.e. the on-time period T31-G of the green sub-pixel G is greater than the on-time period T31-R of the red sub-pixel R and the on-time period T31-B of the blue sub-pixel B, so that the effective light-emitting time periods of the sub-pixels of the colors are different. Especially at a low gray scale and a high refresh rate, the low level duty ratio of the emission control signal emit is small, which results in a relatively large on-time period T31-G of the green sub-pixel G, and an effective emission time period T32 of the green sub-pixel G is smaller than the effective emission time periods of the red sub-pixel R and the blue sub-pixel B, which results in a color cast phenomenon of the display panel, such as red or purple red.
In some alternative embodiments, as shown in fig. 1, the sub-pixel P may include a target sub-pixel P1 and a non-target sub-pixel P2. Illustratively, the on-time period of the light-emitting element of the target sub-pixel P1 is longer than the on-time period of the light-emitting element of the non-target sub-pixel P2. The control terminal of the dimming module 02 may receive the dimming control signal, and the dimming module 02 may be in a conducting state or a blocking state under the control of the dimming control signal. When the dimming control signal is at the off-level, the dimming module 02 is in the off-state, the driving circuit generated by the enabling module 01 can flow into the light emitting element D, and the light emitting element D can emit light after a certain lighting time period.
As shown in fig. 5, taking the high level as the off level as an example, in a frame time period, a time period of the dimming control signal sw1 received by the dimming module 02 corresponding to the target sub-pixel P1 being the off level is a target time period T1, a time period of the dimming control signals sw21 and sw22 received by the dimming module 02 corresponding to the non-target sub-pixel P2 being the off level is a non-target time period T2, and the target time period T1 is greater than the non-target time period T2, so that the effective light emitting time periods of the target sub-pixel P1 and the non-target sub-pixel P2 are the same, and the color cast phenomenon of the display panel is avoided.
In some alternative embodiments, the light emitting element of the target sub-pixel P1 may be a green organic light emitting diode, and the light emitting element of the non-target sub-pixel P2 may be at least one of a red organic light emitting diode and a blue organic light emitting diode, so as to prevent the display panel from generating red or purple.
In some alternative embodiments, as shown in fig. 1, the non-target subpixel P2 may include a first non-target subpixel P21 and a second non-target subpixel P22. Illustratively, the on-time period of the first non-target sub-pixel P21 is greater than the on-time period of the second non-target sub-pixel P22. As shown in fig. 5, in a frame time period, a time period during which the dimming control signal sw21 received by the dimming module 02 corresponding to the first non-target subpixel P21 is at an off level is a first non-target time period T21, a time period during which the dimming control signal sw22 received by the dimming module 02 corresponding to the second non-target subpixel P22 is at an off level is a second non-target time period T22, and the first non-target time period T21 is greater than the second non-target time period T22. That is, the target duration T1 is longer than the first non-target duration T21, and the first non-target duration T21 is longer than the second non-target duration T22, so that the effective emitting durations of the target sub-pixel P1, the first non-target sub-pixel P21 and the second non-target sub-pixel P22 are the same, and color cast of the display panel is further avoided.
Illustratively, the light emitting element of the target sub-pixel P1 may be a green organic light emitting diode, the first non-target sub-pixel P21 may be a red organic light emitting diode, and the second non-target sub-pixel P22 may be a blue organic light emitting diode, so as to further prevent the red or purple phenomenon from occurring in the display panel.
In the above embodiment, the high level of the dimming control signal is the off level and the low level is the on level, but the low level of the dimming control signal may be the off level and the high level may be the on level, which is not limited in the present application. In addition, it is understood that the off level of the dimming control signal may correspond to the light emitting phase of each sub-pixel. The starting time of the dimming control signals of the target sub-pixel, the first non-target sub-pixel and the second non-target sub-pixel being at the cut-off level may be the same.
In some alternative embodiments, as shown in fig. 6, the dimming module 02 may include a first transistor M1, a first pole of the first transistor M1 is electrically connected to the output terminal of the enable module 01, and a second pole of the first transistor M1 is electrically connected to the second voltage terminal PVEE. The gate of the first transistor M1 in the target subpixel P1 is electrically connected to the target dimming control signal terminal SW1, and the gate of the first transistor M1 in the non-target subpixel P2 is electrically connected to the non-target dimming control signal terminals SW21 and SW 22.
Illustratively, the non-target subpixel P2 includes a first non-target subpixel P21 and a second non-target subpixel P22, the non-target dimming control signal terminals include a first non-target dimming control signal terminal SW21 and a second non-target dimming control signal terminal SW22, the gate of the first transistor M1 in the first non-target subpixel P21 may be electrically connected to the first non-target dimming control signal terminal SW21, and the gate of the first transistor M1 in the second non-target subpixel P22 may be electrically connected to the second non-target dimming control signal terminal SW 22.
In the embodiment of the present application, the gates of the first transistors M1 of the target sub-pixel P1 and the non-target sub-pixel P2 are electrically connected to different dimming control signal terminals, so that the dimming control signals received by the sub-pixels can be conveniently and individually controlled.
In some alternative embodiments, the target dimming control signal terminal SW1 and the non-target dimming control signal terminals SW21 and SW22 output the dimming control signal in the form of pulse signals. Illustratively, the non-target dimming control signal terminals include a first non-target dimming control signal terminal SW21 and a second non-target dimming control signal terminal SW 22. The target dimming control signal terminal SW1 may output the dimming control signal SW1 in a pulse form as shown in fig. 5, the first non-target dimming control signal terminal SW21 may output the dimming control signal SW21 in a pulse form as shown in fig. 5, the second non-target dimming control signal terminal SW22 may output the dimming control signal SW22 in a pulse form as shown in fig. 5, and the duty ratio of the off-level of the dimming control signal SW1 output by the target dimming control signal terminal SW1 is greater than the duty ratio of the off-level of the dimming control signals SW21, SW22 in a pulse form output by the non-target dimming control signal terminals SW21, SW 22. Specifically, the duty ratio of the off level of the dimming control signal SW1 output from the target dimming control signal terminal SW1 is greater than the duty ratio of the off level of the pulse-form dimming control signal SW21 output from the first non-target dimming control signal terminal SW21, and the duty ratio of the off level of the pulse-form dimming control signal SW21 output from the first non-target dimming control signal terminal SW21 is greater than the duty ratio of the off level of the pulse-form dimming control signal SW22 output from the second non-target dimming control signal terminal SW 22. In this way, the effective light emitting durations of the target sub-pixel P1, the first non-target sub-pixel P21 and the second non-target sub-pixel P22 are ensured to be the same, thereby preventing the color cast of the display panel.
In some alternative embodiments, as shown in fig. 7, the enabling module 01 includes a driving sub-module 11, a data writing sub-module 12, a first initialization sub-module 13, a threshold compensation sub-module 14, a first light emission control sub-module 15, a second light emission control sub-module 16, and a storage sub-module 17. The driving sub-module 11 is electrically connected to the data writing sub-module 12, the data writing sub-module 12 is configured to write a data voltage into the driving sub-module 11, and the driving sub-module 11 is configured to generate a driving current. The first initialization submodule 13 is electrically connected to the control end of the driving submodule 11, and the first initialization submodule 13 is configured to initialize the control end of the driving submodule 11. The threshold compensation submodule 14 is electrically connected to the control terminal of the driving submodule 11, and the threshold compensation submodule 14 is configured to detect and self-compensate for a threshold voltage deviation in the driving submodule 11. The first light-emitting control sub-module 15 is connected in series between the first voltage terminal PVDD and the driving sub-module 11, the second light-emitting control sub-module 16 is connected in series between the driving sub-module 11 and the light-emitting element D, and the first light-emitting control sub-module 15 and the second light-emitting control sub-module 16 are used for controlling the driving current generated by the driving sub-module 11 to be transmitted to the light-emitting element D. The storage submodule 17 is electrically connected to the control terminal of the driving submodule 11, and the storage submodule 17 is configured to maintain the potential of the control terminal of the driving submodule 11.
For example, the control terminal of the first initialization sub-module 13 may be electrically connected to the first SCAN signal terminal SCAN1, and the input terminal of the first initialization sub-module 13 may be electrically connected to the reference signal terminal VREF. The control terminal of the threshold compensation submodule 14 may be electrically connected to the second SCAN signal terminal SCAN 2. The control terminal of the data write submodule 12 may be electrically connected to the third SCAN signal terminal SCAN3, and the input terminal of the data write submodule 12 may be electrically connected to the data signal terminal VDATA. The control terminal of the first emission control sub-module 15 may be electrically connected with the first emission control signal terminal EM1, and the control terminal of the second emission control sub-module 16 may be electrically connected with the second emission control signal terminal EM 2.
In some alternative embodiments, as shown in fig. 8, the driving sub-module 11 includes a driving transistor DT, the data writing sub-module 12 includes a second transistor M2, the first initialization sub-module 13 includes a third transistor M3, the threshold compensation sub-module 14 includes a fourth transistor M4, the first light emission control sub-module 15 includes a fifth transistor M5, the second light emission control sub-module 16 includes a sixth transistor M6, and the storage sub-module 17 includes a storage capacitor Cst. The gate of the third transistor M3 is electrically connected to the first SCAN signal terminal SCAN1, the first pole of the third transistor M3 is electrically connected to the reference signal terminal VREF, and the second pole of the third transistor M3 is electrically connected to the gate of the driving transistor DT. A gate electrode of the fourth transistor M4 is electrically connected to the second SCAN signal terminal SCAN2, a first electrode of the fourth transistor M4 is electrically connected to the second electrode of the driving transistor DT, and a second electrode of the fourth transistor M4 is electrically connected to the gate electrode of the driving transistor DT. The gate of the second transistor M2 is electrically connected to the third SCAN signal terminal SCAN3, the first pole of the second transistor M3 is electrically connected to the data signal terminal VDATA, and the second pole of the second transistor M2 is electrically connected to the first pole of the driving transistor DT. A gate of the fifth transistor M5 is electrically connected to the first emission control signal terminal EM1, a first pole of the fifth transistor M5 is electrically connected to the first voltage terminal PVDD, and a second pole of the fifth transistor M5 is electrically connected to the first pole of the driving transistor DT. A gate of the sixth transistor M6 is electrically connected to the second emission control signal terminal EM2, a first pole of the sixth transistor M6 is electrically connected to the second pole of the driving transistor DT, and a second pole of the sixth transistor M6 is electrically connected to the first pole of the light emitting element D and the dimming control module 02. A first electrode of the storage capacitor Cst is electrically connected to the first voltage terminal PVDD, and a second electrode of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor DT. The second pole of the light emitting device D is electrically connected to the second voltage terminal PVEE.
For example, as described above, the dimming control module 02 may include the first transistor M1, and the second pole of the sixth transistor M6 may be electrically connected to the first pole of the light emitting element D and the first pole of the first transistor M1. In addition, the gate of the first transistor M1 in the target sub-pixel is electrically connected to the target dimming control signal terminal SW1, the gate of the first transistor M1 in the first non-target sub-pixel is electrically connected to the first non-target dimming control signal terminal SW21, and the gate of the first transistor M1 in the second non-target sub-pixel is electrically connected to the second non-target dimming control signal terminal SW 22.
For example, the first pole of the light emitting element D may be an anode, and the second pole of the light emitting element D may be a cathode.
Illustratively, the type of each transistor in the pixel circuit may be the same, for example, each transistor in the pixel circuit is a P-type transistor or an N-type transistor. In the case where the second transistor M2 and the fourth transistor M4 are of the same type, the second SCAN signal terminal SCAN2 may be multiplexed as the third SCAN signal terminal SCAN3, that is, the gates of the second transistor M2 and the fourth transistor M4 may be electrically connected to the same SCAN signal terminal.
Since the oxide transistor has a lower leakage current than the P-type transistor, in order to avoid the influence of the leakage current of the third transistor M3 and the fourth transistor M4 on the gate potential of the driving transistor DT, as shown in fig. 8, the third transistor M3 and the fourth transistor M4 may adopt N-type transistors whose active layers are metal oxide active layers with better stability, and the other transistors may be P-type transistors.
FIG. 9 shows a timing diagram of FIG. 8. In a stage t1, which is also referred to as an initialization stage at stage t1, the first SCAN signal SCAN1 provided at the first SCAN signal terminal SCAN1 is at a high level, and the third transistor M3 is turned on to initialize the gate of the driving transistor DT. In a stage t2, which is also referred to as a data writing stage at stage t2, the second SCAN signal SCAN2 provided by the second SCAN signal terminal SCAN2 is at a high level, the third SCAN signal SCAN3 provided by the third SCAN signal terminal SCAN3 is at a low level, the second transistor M2 and the fourth transistor M4 are turned on, and the data voltage at the data signal terminal VDATA is written into the gate of the driving transistor DT. In a stage t3, which is also referred to as a light emitting stage t3, the first light emission control signal EM1 provided from the first light emission control signal terminal EM1 and the second light emission control signal EM2 provided from the second light emission control signal terminal EM2 are both low, the fifth transistor M5 and the sixth transistor M6 are turned on, the dimming control signals SW1, SW21 and SW22 provided from the dimming control signal terminals SW1, SW21 and SW22 are high, the first transistor M1 is turned off, and the light emitting element D emits light.
The high-level time length T1 of the dimming control signal sw1 is greater than the high-level time length T21 of the dimming control signal sw21, and the high-level time length T21 of the dimming control signal sw21 is greater than the high-level time length T22 of the dimming control signal sw22, so that the effective light emitting time lengths of the target sub-pixel P1, the first non-target sub-pixel P21 and the second non-target sub-pixel P22 are the same, and the color cast phenomenon of the display panel is avoided.
When the dimming control signals SW1, SW21 and SW22 supplied from the dimming control signal terminals SW1, SW21 and SW22 are at a low level, the first transistor M1 is turned on, and the voltage supplied from the second voltage terminal PVEE is written to the first electrode of the light emitting element D through the first transistor M1, so that the potential of the first electrode of the light emitting element D is fixed to be the same as the potential of the second voltage terminal PVEE, and the potential of the first electrode of the light emitting element D is prevented from being increased due to a leakage current, thereby preventing the light emitting element D from being turned on illegally.
In some alternative embodiments, during the period t3, the dimming control signals SW1, SW21 and SW22 provided by the dimming control signal terminals SW1, SW21 and SW22 may be signals with alternating high levels and low levels, that is, the light emitting device D is alternately in the light emitting state and the non-light emitting state during the period t3, so as to reduce the total duration of the light emitting device D in the light emitting state to adjust the brightness of the light emitting device D to meet the brightness requirement of the low gray scale.
In some alternative embodiments, the first emission control signal terminal EM1 may be multiplexed as the second emission control signal terminal EM2, that is, the gates of the fifth transistor M5 and the sixth transistor M6 may be connected to the same emission control signal terminal.
In some alternative embodiments, as shown in fig. 10, the enabling module 01 further comprises a second initialization sub-module 18, the second initialization sub-module 18 being electrically connected to the first pole of the light emitting element D for initializing the light emitting element D.
For example, as shown in fig. 10, the input terminal of the second initialization sub-module 18 may be electrically connected to the reference signal terminal VREF, and as shown in fig. 11, the input terminal of the second initialization sub-module 18 may be electrically connected to the second voltage terminal PVEE. In addition, the control terminal of the second initialization sub-module 18 may be electrically connected with the third SCAN signal terminal SCAN 3.
In some alternative embodiments, the second initialization sub-module 18 includes a seventh transistor M7, a gate of the seventh transistor M7 is electrically connected to the third SCAN signal terminal SCAN3, a second pole of the seventh transistor M7 is electrically connected to the first pole of the light emitting element D, and a first pole of the seventh transistor M7 is electrically connected to the reference signal terminal VREF.
The reference signal terminal VREF and the second voltage terminal PVEE have different potentials, and if the first transistor M1 and the seventh transistor M7 are turned on simultaneously, a short circuit is caused. In some alternative embodiments, as shown in fig. 12, when the third SCAN signal SCAN3 provided by the third SCAN signal terminal SCAN3 is at a low level, the dimming control signals SW1, SW21 and SW22 provided by the dimming control signal terminals SW1, SW21 and SW22 may be at a high level, so that when the seventh transistor M7 is in an on state, the dimming control module 02 is in an off state, that is, the first transistor M1 is in an off state, so as to avoid a short circuit.
As shown in fig. 11, the first pole of the seventh transistor M7 may be electrically connected to the second voltage terminal PVEE. At this time, even if the first transistor M1 and the seventh transistor M7 are simultaneously turned on, a short circuit is not caused.
In some alternative embodiments, the dimming control signal terminals SW1, SW21, SW22 may be integrated on the driving chip. Each target sub-pixel of the display panel may be electrically connected to the same dimming control signal terminal SW1, each first non-target sub-pixel may be electrically connected to the same dimming control signal terminal SW21, and each second non-target sub-pixel may be electrically connected to the same dimming control signal terminal SW 22.
In other alternative embodiments, the dimming control signal may be output by using a shift register. As shown in fig. 13, the display panel 100 further includes a plurality of cascaded target shift register cells 31 and a plurality of cascaded non-target register cells 32. For example, the non-target register unit 32 may include a first non-target register unit 321 and a second non-target shift register unit 322, where a plurality of the first non-target register units 321 are cascaded and a plurality of the second non-target shift register units 322 are cascaded. The output terminal of the target shift register unit 31 serves as a dimming control signal terminal SW1, and the output terminal of the target shift register unit 31 is electrically connected to the control terminal of the dimming module of the target sub-pixel P1. The output terminal of the first non-target register unit 321 serves as a first non-target dimming control signal terminal SW21, and the output terminal of the first non-target register unit 321 is electrically connected to the control terminal of the dimming module of the first non-target subpixel P21. The output terminal of the second non-target register unit 322 serves as a second non-target dimming control signal terminal SW22, and the output terminal of the second non-target register unit 322 is electrically connected to the control terminal of the dimming module of the second non-target subpixel P22.
Illustratively, the display panel 100 has a display area AA and a non-display area NA, the pixel units PU are distributed in the display area, and the plurality of cascaded target shift register units 31 and the plurality of cascaded non-target register units 32 are located in the non-display area NA. In the first direction X, a plurality of cascaded target shift register units 31 and a plurality of cascaded non-target register units 32 may be disposed on both sides of the display area AA to implement dual gate driving. The plurality of cascaded target shift register units 31 may be arranged in the second direction Y, and the plurality of cascaded non-target register units 32 may be arranged in the second direction Y. The first direction X may be a row direction and the second direction Y may be a column direction.
For example, the display panel may include N rows of pixel units, N and cascaded target shift register units 31, N cascaded first non-target shift register units 321, and N cascaded second non-target shift register units 322, where N is an integer greater than or equal to 1, an output terminal of the i-th stage target shift register unit 31 is electrically connected to a control terminal of the dimming module of the i-th row target sub-pixel P1, an output terminal of the i-th stage first non-target shift register unit 321 is electrically connected to a control terminal of the dimming module of the i-th row first non-target sub-pixel P21, and an output terminal of the i-th stage second non-target shift register unit 322 is electrically connected to a control terminal of the dimming module of the i-th row second non-target sub-pixel P22.
An embodiment of the present application further provides a display control method of a display panel, for controlling the display panel according to any one of the above embodiments, as shown in fig. 14, the display control method of the display panel includes step 140.
Step 140, controlling the time length of the dimming module in the off state to adjust the light emitting time length of the light emitting element.
In the embodiment of the application, because the dimming module is connected in parallel with the light-emitting element, when the dimming module is in a cut-off state, the driving current generated by the enabling module can completely flow through the light-emitting element, and at the moment, the light-emitting element can emit light; when the dimming module is in a conducting state, namely the light-emitting element is in a short circuit, most of the driving current generated by the enabling module flows into the dimming module, and the light-emitting element cannot emit light at the moment; therefore, the light emitting duration of the light emitting element can be adjusted by only arranging the light dimming module connected with the light emitting element in parallel and controlling the duration of the light dimming module in the cut-off state, so that the structure is simpler, and the light dimming of the display panel can be easily realized.
In some optional embodiments, the sub-pixels include a target sub-pixel and a non-target sub-pixel, and step 140 may specifically include: and controlling the time length of the dimming module in the target sub-pixel in the off state to be longer than the time length of the dimming module in the non-target sub-pixel in the off state so as to adjust the light emitting time lengths of the light emitting elements in the target sub-pixel and the non-target sub-pixel.
According to the application, the effective light emitting time of the target sub-pixel and the effective light emitting time of the non-target sub-pixel are the same, and the color cast phenomenon of the display panel is avoided.
In some optional embodiments, the non-target sub-pixels include a first non-target sub-pixel and a second non-target sub-pixel, and step 140 may specifically include: the duration of the dimming module in the target sub-pixel in the off state is controlled to be longer than the duration of the dimming module in the first non-target sub-pixel in the off state, and the duration of the dimming module in the first non-target sub-pixel in the off state is controlled to be longer than the duration of the dimming module in the second non-target sub-pixel in the off state, so that the light emitting duration of the light emitting elements in the target sub-pixel, the first non-target sub-pixel and the second non-target sub-pixel is adjusted.
According to the implementation of the application, the effective light emitting time lengths of the target sub-pixel, the first non-target sub-pixel and the second non-target sub-pixel are the same, and the color cast phenomenon of the display panel is further avoided.
It should be noted that, in the display control method of the display panel provided in the embodiment of the present application, the execution main body may be a control module of the display panel, and for example, the execution main body may be a driving chip of the display panel.
The embodiment of the present application further provides a method for adjusting a duty ratio of a dimming control signal, which is used to adjust a duty ratio of a cut-off level of a dimming control signal received by a dimming module in a display panel in an off state during a lighting phase according to any of the above embodiments. As shown in fig. 15, the method for adjusting the duty ratio of the dimming control signal includes steps 151 to 153.
Step 151, determining a target charging time period of the capacitor of the light emitting element of the target sub-pixel according to the voltage across, the capacitance value and the current value of the light emitting element of the target sub-pixel.
Step 152, determining a non-target charging time period of the capacitor of the light emitting element of the non-target sub-pixel according to the voltage across, the capacitance value and the current value of the light emitting element of the non-target sub-pixel.
Step 153, making the difference between the target time length and the target charging time length equal to the difference between the non-target time length and the non-target charging time length, adjusting the duty ratio of the dimming control signal received by the dimming module of the target sub-pixel to the cut-off level, and adjusting the duty ratio of the dimming control signal received by the dimming module of the non-target sub-pixel to the cut-off level.
For example, the target sub-pixel is a green sub-pixel, the non-target sub-pixels include a first non-target sub-pixel and a second non-target sub-pixel, the red sub-pixel is a first non-target sub-pixel, and the blue sub-pixel is a second non-target sub-pixel.
Since the light emitting element itself has a capacitance, the capacitance of the light emitting element itself needs to be charged, and the light emitting element is not lighted during the charging period. In steps 151 and 152, the charging period of the capacitances of the light emitting elements in the target sub-pixel and the non-target sub-pixels may be determined in the following manner.
The charging period of the capacitances of the light emitting elements in the target sub-pixel and the non-target sub-pixel may be determined according to equation (1), where equation (1) is:
Figure BDA0002843908900000141
where Q denotes an electric charge amount, C denotes a capacitance of a light emitting element, V denotes a voltage, I denotes a current, and t denotes a time period.
Specifically, the target charging period of the capacitance of the light emitting element of the target sub-pixel can be calculated according to equation (2):
Figure BDA0002843908900000142
wherein, tGIndicates a target charging period, Coled-GCapacitance, V, of light emitting element representing target sub-pixeloled-GVoltage across the light emitting element of the target sub-pixel, IGRepresenting the current of the light emitting element of the target sub-pixel.
The first non-target charging period of the capacitance of the light emitting element of the first non-target sub-pixel may be calculated according to equation (3):
Figure BDA0002843908900000151
wherein, tRRepresenting a first non-target charging period, Coled-RIndicating the capacitance, V, of the light-emitting element of the first non-target sub-pixeloled-RIndicating the voltage across the light-emitting element of the first non-target sub-pixel, IRRepresenting the current of the light emitting element of the first non-target sub-pixel.
The second non-target charging period of the capacitance of the light emitting element of the second non-target sub-pixel may be calculated according to equation (4):
Figure BDA0002843908900000152
wherein, tBRepresenting a second non-target charging period, Coled-BIndicating the capacitance, V, of the light-emitting element of the second non-target sub-pixeloled-BIndicating the voltage across the light-emitting element of the second non-target sub-pixel, IBRepresenting the current of the light emitting element of the second non-target sub-pixel.
In step 153, the duty ratio of the dimming control signal received by the dimming module to the off level may be adjusted according to equation (5).
T1-tG＝T21-tR＝T22-tB (5)
T1 is a duration of the dimming control signal received by the dimming module corresponding to the target sub-pixel being at the cut-off level, T21 is a duration of the dimming control signal received by the dimming module corresponding to the first non-target sub-pixel being at the cut-off level, and T22 is a duration of the dimming control signal received by the dimming module corresponding to the second non-target sub-pixel being at the cut-off level.
The formula (5) indicates that the effective light emitting durations of the target sub-pixel, the first non-target sub-pixel and the second non-target sub-pixel are the same, and further, under the condition that the effective light emitting durations of the target sub-pixel, the first non-target sub-pixel and the second non-target sub-pixel are the same, the duty ratio of the dimming control signal received by the dimming module of the target sub-pixel to the cut-off level is adjusted, and the duty ratio of the dimming control signal received by the dimming module of the non-target sub-pixel to the cut-off level is adjusted, so that the color cast of the display panel is avoided.
In the case where the structure of the light emitting element is fixed, the capacitance and the voltage across the light emitting element can be directly obtained. In the case of gray scale determination, the current of the light emitting element is also known. In addition, since the light emitting currents corresponding to the target sub-pixel and the non-target sub-pixel vary at different gray scales, the duty ratio at which the dimming control signals corresponding to the target sub-pixel and the non-target sub-pixel are at the off-level at any gray scale can be determined according to the above equations (2) to (5).
The method for adjusting the duty ratio of the dimming control signal according to the embodiment of the present application may be implemented by a control module, which is implemented by a device for adjusting the duty ratio of the dimming control signal or by a method for adjusting the duty ratio of the dimming control signal in the device for adjusting the duty ratio of the dimming control signal.
The device for adjusting the duty ratio of the dimming control signal in the embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in the terminal. The device can be mobile electronic equipment or non-mobile electronic equipment. By way of example, the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and the non-mobile electronic device may be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine or a self-service machine, and the like, and the embodiments of the present application are not particularly limited.
The adjusting device of the duty ratio of the dimming control signal in the embodiment of the present application may be a device having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not limited specifically.
The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 16, fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 16 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 16 by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.
In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims (16)

1. A display panel, comprising:
a plurality of pixel units, each of the pixel units including a plurality of sub-pixels, each of the sub-pixels including a pixel circuit and a light emitting element, the pixel circuit including an enable module and a dimming module, the enable module and the light emitting element being connected in series between a first voltage terminal and a second voltage terminal, the light emitting element and the dimming module being connected in parallel between the enable module and the second voltage terminal; the dimming module is used for adjusting the light emitting time of the light emitting element.
2. The display panel of claim 1, wherein the sub-pixels comprise a target sub-pixel and a non-target sub-pixel;
the control end of the dimming module is used for receiving a dimming control signal, in a frame time length, the time length of the dimming control signal received by the dimming module of the target sub-pixel, which is a cut-off level, is a target time length, the time length of the dimming control signal received by the dimming module of the non-target sub-pixel, which is a cut-off level, is a non-target time length, and the target time length is greater than the non-target time length.
3. The display panel of claim 2, wherein the control terminal of the enable module is configured to receive a scan signal and a light-emitting control signal, and the dimming control signal is different from both the scan signal and the light-emitting control signal.
4. The display panel of claim 2, wherein the light emitting element of the target sub-pixel comprises a green organic light emitting diode;
the light emitting element of the non-target sub-pixel includes at least one of a red organic light emitting diode and a blue organic light emitting diode.
5. The display panel of claim 2, wherein the non-target sub-pixels comprise a first non-target sub-pixel and a second non-target sub-pixel, and wherein the dimming control signal received by the dimming module of the first non-target sub-pixel is at an off-level for a first non-target duration and the dimming control signal received by the dimming module of the second non-target sub-pixel is at an off-level for a second non-target duration within a frame duration, and wherein the first non-target duration is greater than the second non-target duration.
6. The display panel of claim 5, wherein the light emitting element of the target sub-pixel comprises a green organic light emitting diode;
the light emitting element of the first non-target sub-pixel comprises a red organic light emitting diode;
the light emitting element of the second non-target sub-pixel includes a blue organic light emitting diode.
7. The display panel according to claim 2, wherein the dimming module comprises a first transistor, a first electrode of the first transistor is electrically connected to the output terminal of the enable module, a second electrode of the first transistor is electrically connected to the second voltage terminal, a gate of the first transistor in the target sub-pixel is electrically connected to a target dimming control signal terminal, and a gate of the first transistor in the non-target sub-pixel is electrically connected to a non-target dimming control signal terminal.
8. The display panel of claim 7, wherein the target dimming control signal terminal and the non-target dimming control signal terminal both output a dimming control signal in a pulse form, and a duty ratio of a cut-off level of the dimming control signal output by the target dimming control signal terminal is greater than a duty ratio of a cut-off level of the dimming control signal output by the non-target dimming control signal terminal.
9. The display panel of claim 1, wherein the enable module comprises a driving sub-module, a data writing sub-module, a first initialization sub-module, a threshold compensation sub-module, a first light emission control sub-module, a second light emission control sub-module, and a storage sub-module; wherein the content of the first and second substances,
the driving submodule is electrically connected with the data writing submodule, the data writing submodule is used for writing data voltage into the driving submodule, and the driving submodule is used for generating driving current;
the first initialization submodule is electrically connected with the control end of the driving submodule and is used for initializing the control end of the driving submodule;
the threshold compensation submodule is electrically connected with the control end of the driving submodule and is used for detecting and self-compensating threshold voltage deviation in the driving submodule;
the first light-emitting control sub-module is connected in series between the first voltage end and the driving sub-module, the second light-emitting control sub-module is connected in series between the driving sub-module and the light-emitting element, and the first light-emitting control sub-module and the second light-emitting control sub-module are used for controlling the driving current generated by the driving sub-module to be transmitted to the light-emitting element;
the storage submodule is electrically connected with the control end of the driving submodule, and the storage submodule is used for maintaining the potential of the control end of the driving submodule.
10. The display panel of claim 8, wherein the driving sub-module comprises a driving transistor, the data writing sub-module comprises a second transistor, the first initialization sub-module comprises a third transistor, the threshold compensation sub-module comprises a fourth transistor, the first emission control sub-module comprises a fifth transistor, the second emission control sub-module comprises a sixth transistor, and the storage sub-module comprises a storage capacitor; wherein the content of the first and second substances,
the grid electrode of the third transistor is electrically connected with a first scanning signal end, the first electrode of the third transistor is electrically connected with a reference signal end, and the second electrode of the third transistor is electrically connected with the grid electrode of the driving transistor;
a gate of the fourth transistor is electrically connected to a second scan signal terminal, a first electrode of the fourth transistor is electrically connected to a second electrode of the driving transistor, and the second electrode of the fourth transistor is electrically connected to the gate of the driving transistor;
the grid electrode of the second transistor is electrically connected with a third scanning signal end, the first electrode of the second transistor is electrically connected with a data signal end, and the second electrode of the second transistor is electrically connected with the first electrode of the driving transistor;
a gate of the fifth transistor is electrically connected to the first light emission control signal terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor;
a gate of the sixth transistor is electrically connected to a second light-emitting control signal terminal, a first electrode of the sixth transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element and the dimming control module;
the first electrode of the storage capacitor is electrically connected with the first voltage end, and the second electrode of the storage capacitor is electrically connected with the grid electrode of the driving transistor;
the second electrode of the light emitting element is electrically connected to the second voltage terminal.
11. The display panel of claim 10 wherein the enable module further comprises a second initialization sub-module electrically connected to the first poles of the light emitting elements for initializing the light emitting elements.
12. The display panel according to claim 11, wherein the second initialization sub-module includes a seventh transistor, a gate of the seventh transistor is electrically connected to the third scan signal terminal, and a second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element; wherein the content of the first and second substances,
a first electrode of the seventh transistor is electrically connected with the reference signal terminal, and when the seventh transistor is in a conducting state, the dimming control module is in a turn-off state; alternatively, the first and second electrodes may be,
a first electrode of the seventh transistor is electrically connected to the second voltage terminal.
13. The display panel of claim 2, wherein the display panel further comprises a plurality of cascaded target shift register cells and a plurality of cascaded non-target register cells, wherein an output terminal of the target shift register cell is electrically connected to the control terminal of the dimming module of the target sub-pixel, and an output terminal of the non-target register cell is electrically connected to the control terminal of the dimming module of the non-target sub-pixel.
14. A display control method of a display panel for controlling the display panel according to any one of claims 1 to 13, the method comprising:
and controlling the time length of the dimming module in the turn-off state so as to adjust the light emitting time length of the light emitting element.
15. A method for adjusting a duty cycle of a dimming control signal, for adjusting a duty cycle of a cut-off level of the dimming control signal received by the dimming module in the display panel of claim 2, the method comprising:
determining a target charging time length of a capacitor of the light-emitting element of the target sub-pixel according to the voltage, the capacitance and the current value of the light-emitting element of the target sub-pixel;
determining a non-target charging time period of the capacitor of the light-emitting element of the non-target sub-pixel according to the voltage, the capacitance and the current value of the light-emitting element of the non-target sub-pixel;
the difference between the target time length and the target charging time length is equal to the difference between the non-target time length and the non-target charging time length, the duty ratio of the dimming control signal received by the dimming module of the target sub-pixel as a cut-off level is adjusted, and the duty ratio of the dimming control signal received by the dimming module of the non-target sub-pixel as a cut-off level is adjusted.
16. A display device characterized by comprising the display panel according to any one of claims 1 to 13.
CN202011502657.XA 2020-12-17 2020-12-17 Display panel, display control method thereof, duty ratio adjusting method and display device Active CN112435628B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011502657.XA CN112435628B (en) 2020-12-17 2020-12-17 Display panel, display control method thereof, duty ratio adjusting method and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011502657.XA CN112435628B (en) 2020-12-17 2020-12-17 Display panel, display control method thereof, duty ratio adjusting method and display device

Publications (2)

Publication Number Publication Date
CN112435628A true CN112435628A (en) 2021-03-02
CN112435628B CN112435628B (en) 2021-12-28

Family

ID=74696759

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011502657.XA Active CN112435628B (en) 2020-12-17 2020-12-17 Display panel, display control method thereof, duty ratio adjusting method and display device

Country Status (1)

Country Link
CN (1) CN112435628B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023235A (en) * 2021-11-10 2022-02-08 昆山国显光电有限公司 Driving method of display panel, electronic device, and computer-readable storage medium
CN114863873A (en) * 2022-04-29 2022-08-05 武汉天马微电子有限公司 Display panel and display device
CN115171593A (en) * 2022-06-30 2022-10-11 武汉天马微电子有限公司 Display panel and display device
CN115547258A (en) * 2022-10-31 2022-12-30 武汉天马微电子有限公司 Display panel, driving method thereof and display device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060066525A1 (en) * 2002-11-23 2006-03-30 Koninklijke Philips Electronics, N.V. Colour control for active matrix electroluminescent display
CN101147185A (en) * 2005-01-26 2008-03-19 霍尼韦尔国际公司 Active matrix organic light emitting diode display
CN102054428A (en) * 2009-11-05 2011-05-11 宏碁股份有限公司 Organic light-emitting diode (OLED) display as well as driving method and pixel unit thereof
CN104167175A (en) * 2014-08-06 2014-11-26 上海和辉光电有限公司 Organic light-emitting displayer
CN204680360U (en) * 2015-02-02 2015-09-30 信利（惠州）智能显示有限公司 A kind of image element circuit and display device
CN110992885A (en) * 2019-12-25 2020-04-10 上海天马微电子有限公司 Pixel driving circuit, driving method thereof and display panel
CN111754920A (en) * 2020-07-17 2020-10-09 武汉华星光电半导体显示技术有限公司 Pixel driving circuit, driving method thereof and display panel

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060066525A1 (en) * 2002-11-23 2006-03-30 Koninklijke Philips Electronics, N.V. Colour control for active matrix electroluminescent display
CN101147185A (en) * 2005-01-26 2008-03-19 霍尼韦尔国际公司 Active matrix organic light emitting diode display
CN102054428A (en) * 2009-11-05 2011-05-11 宏碁股份有限公司 Organic light-emitting diode (OLED) display as well as driving method and pixel unit thereof
CN104167175A (en) * 2014-08-06 2014-11-26 上海和辉光电有限公司 Organic light-emitting displayer
CN204680360U (en) * 2015-02-02 2015-09-30 信利（惠州）智能显示有限公司 A kind of image element circuit and display device
CN110992885A (en) * 2019-12-25 2020-04-10 上海天马微电子有限公司 Pixel driving circuit, driving method thereof and display panel
CN111754920A (en) * 2020-07-17 2020-10-09 武汉华星光电半导体显示技术有限公司 Pixel driving circuit, driving method thereof and display panel

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114023235A (en) * 2021-11-10 2022-02-08 昆山国显光电有限公司 Driving method of display panel, electronic device, and computer-readable storage medium
CN114023235B (en) * 2021-11-10 2023-09-15 昆山国显光电有限公司 Display panel driving method, electronic device, and computer-readable storage medium
CN114863873A (en) * 2022-04-29 2022-08-05 武汉天马微电子有限公司 Display panel and display device
CN115171593A (en) * 2022-06-30 2022-10-11 武汉天马微电子有限公司 Display panel and display device
CN115547258A (en) * 2022-10-31 2022-12-30 武汉天马微电子有限公司 Display panel, driving method thereof and display device

Also Published As

Publication number Publication date
CN112435628B (en) 2021-12-28

Similar Documents

Publication Publication Date Title
CN112435628B (en) Display panel, display control method thereof, duty ratio adjusting method and display device
CN109523956B (en) Pixel circuit, driving method thereof and display device
CN109036279B (en) Array substrate, driving method, organic light emitting display panel and display device
US11355051B2 (en) Display device, display panel, and pixel drive circuit of display panel
CN108417149B (en) Display panel, driving method thereof and display device
US10565934B2 (en) Drive compensation circuit, display panel and driving method thereof
US11069298B2 (en) Driving circuit, display panel, driving method and display device
US11482171B2 (en) Display panel, display module, and display device and control method therefor
US11475831B2 (en) Display panel, method of driving display panel, and display device
US11205385B2 (en) Display panel and method of controlling the same, and display apparatus
CN112349250B (en) Display panel and driving method
US10997905B2 (en) Display panel and display device
CN111276097B (en) Pixel driving circuit, driving method thereof and display substrate
US10997920B2 (en) Pixel drive circuit and drive method, and display apparatus
CN109346009B (en) Organic light emitting display panel and display device
CN108376534B (en) Pixel circuit, driving method thereof and display panel
CN111599308B (en) Display device, control method thereof and electronic equipment
CN110429120B (en) Array substrate, driving method thereof, display panel and display device
US20240046859A1 (en) Display substrate and display device
US20220208099A1 (en) Pixel circuit and driving method thereof, light-emitting control circuit, display panel, and display device
US11935491B2 (en) Display device
CN112352274A (en) Pixel compensation circuit, display panel, driving method and display device
US11170701B2 (en) Driving circuit, driving method thereof, display panel and display device
CN110400542B (en) Pixel driving circuit, display panel and display device
EP3726517A1 (en) Pixel circuit, method for driving same, display panel, and electronic device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20211019

Address after: No.8, liufangyuanheng Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province, 430074

Applicant after: WUHAN TIANMA MICRO-ELECTRONICS Co.,Ltd.

Applicant after: Wuhan Tianma Microelectronics Co.,Ltd. Shanghai Branch

Address before: Room 509, building 1, No. 6111, Longdong Avenue, Pudong New Area, Shanghai, 201201

Applicant before: SHANGHAI TIANMA AM-OLED Co.,Ltd.

GR01 Patent grant
GR01 Patent grant