CN112447716A - 垂直晶体管阵列以及形成垂直晶体管阵列的方法 - Google Patents

垂直晶体管阵列以及形成垂直晶体管阵列的方法 Download PDF

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CN112447716A
CN112447716A CN202010909151.4A CN202010909151A CN112447716A CN 112447716 A CN112447716 A CN 112447716A CN 202010909151 A CN202010909151 A CN 202010909151A CN 112447716 A CN112447716 A CN 112447716A
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transistor
conductor
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D·C·潘迪
刘海涛
K·M·考尔道
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Micron Technology Inc
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Micron Technology Inc
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Abstract

本申请案涉及一种垂直晶体管阵列，以及一种用于形成垂直晶体管阵列的方法。一种垂直晶体管阵列包括隔开的导柱，其个别地包括个别垂直晶体管的沟道区。水平拉长的导体线将多个所述垂直晶体管的所述导柱的所述沟道区中的个别沟道区直接电耦合在一起。上部源极/漏极区在所述导柱的所述个别沟道区上方，下部源极/漏极区在所述导柱的所述个别沟道区下方，且导电栅极线以操作方式在所述导柱的所述个别沟道区旁边，且互连多个所述垂直晶体管。公开了方法。

Description

垂直晶体管阵列以及形成垂直晶体管阵列的方法
技术领域
本文所公开的实施例涉及垂直晶体管阵列以及形成垂直晶体管阵列的方法。
背景技术
存储器是一种集成电路，且在计算机系统中用于存储数据。存储器可制造于个别存储器单元的一或多个阵列中。可使用数字线(其也可称作位线、数据线或感测线)和存取线(其也可称作字线)对存储器单元进行写入或从存储器单元进行读取。数字线可使存储器单元沿着阵列的列以导电方式互连，并且存取线可使存储器单元沿着阵列的行以导电方式互连。可通过数字线与存取线的组合对每个存储器单元进行唯一地寻址。
存储器单元可以是易失性的、半易失性的或非易失性的。非易失性存储器单元可在不通电的情况下将数据存储很长一段时间。按照惯例，将非易失性存储器指定为具有至少约10年保留时间的存储器。易失性存储器会消散，且因此经刷新/重写以维持数据存储。易失性存储器可具有数毫秒或更少的保留时间。无论如何，存储器单元经配置以在至少两个不同的可选择状态下保留或存储存储内容。在二进制系统中，所述状态被视为“0”或“1”。在其它系统中，至少一些个别存储器单元可经配置以存储多于两个电平或信息状态。
场效晶体管是一种可用于存储器单元中的电子组件。这些晶体管包括一对导电源极/漏极区，所述一对导电源极/漏极区在其间具有半导电沟道区。导电栅极邻近所述沟道区，且通过薄栅极绝缘体与所述沟道区分离。向栅极施加合适的电压允许电流通过沟道区从源极/漏极区中的一个区流动到另一个区。当从栅极移除电压时，大大地防止了电流流经沟道区。栅极绝缘体可能够编程为处于至少两个保持电容性状态之间，借此晶体管是非易失性。或者，栅极绝缘体可不具有此能力，借此晶体管是易失性。不管怎样，场效晶体管还可包含额外结构，例如，作为栅极绝缘体与导电栅极之间的栅极构造的部分的可以可逆方式编程的电荷储存区。
电容器是可用于存储器单元中的另一类型的电子组件。电容器具有由电绝缘材料分离的两个电导体。能量如电场可以静电方式储存在此类材料内。取决于绝缘体材料的组成，所述所储存的场将是易失性的或非易失性的。举例来说，仅包含SiO2的电容器绝缘体材料将是易失性的。一种类型的非易失性电容器是铁电电容器，所述铁电电容器具有铁电材料作为绝缘材料的至少部分。铁电材料的特征在于具有两个稳定极化状态，且由此可包括电容器和/或存储器单元的可编程材料。铁电材料的极化状态可通过施加合适的编程电压来改变，且在移除编程电压之后保持(至少持续一定时间)。每一极化状态具有彼此不同的电荷储存电容，所述电荷储存电容理想地可用于写入(即，存储)和读取存储器状态，而不逆转极化状态直到期望进行此逆转为止。不太期望的是，在具有铁电电容器的某一存储器中，读取存储器状态的行为可逆转极化。因此，在确定极化状态后，即刻进行对存储器单元的重写，以紧接在其确定之后将存储器单元置于预读取状态中。无论如何，由于形成电容器的部分的铁电材料的双稳态特性，因此并入有铁电电容器的存储器单元理想地是非易失性的。其它可编程材料可用作电容器绝缘体来使电容器变为非易失性的。
电容器和晶体管当然可用于除存储器电路之外的集成电路中，且制造成可或可不为存储器阵列的至少一部分的阵列。
发明内容
在一些实施例中，一种形成垂直晶体管阵列的方法包括形成包括晶体管材料的横向隔开且水平拉长的线，以及位于紧接横向邻近的晶体管-材料线之间的水平拉长的导体线。晶体管材料包括沟道区，其将成为个别垂直晶体管。所述导体线直接电耦合到导体线的两个侧边上的晶体管-材料线的沟道区。切割晶体管-材料线，以形成个别地包括个别垂直晶体管的沟道区的隔开的导柱。导体线将多个垂直晶体管的导柱的沟道区中的个别沟道区直接电耦合在一起。上部源极/漏极区形成于导柱的个别沟道区上方，下部源极/漏极区形成于导柱的个别沟道区下方，且导电栅极线以操作方式形成于导柱的个别沟道区的旁边，且互连多个垂直晶体管。
在一些实施例中，一种形成垂直晶体管阵列的方法包括在列方向上形成横向隔开且水平拉长的晶体管-材料线。所述晶体管材料包括上部源极/漏极区、下部源极/漏极区，以及垂直在其间的沟道区，这将是个别垂直晶体管。在形成晶体管-材料线之后，在列方向上，在紧接横向邻近的晶体管-材料线之间形成水平拉长的导体线。在形成导体线之后，形成导电材料，其将导体线直接电耦合到在导体线的两个侧边上的晶体管-材料线的沟道区。在单个掩蔽步骤中，对以下各项进行切割：(a)晶体管-材料线，以形成个别地包括个别垂直晶体管的沟道区的隔开的第一导柱，其中导体线在列方向上在多个垂直晶体管的第一导柱的沟道区中的个别沟道区直接电耦合在一起；以及(b)导体线，以形成从导体线的导体材料的连续线向上突起的隔开的导电第二导柱。导电栅极线以操作方式形成于第一导柱的个别沟道区旁边，且在行方向上互连多个垂直晶体管。
在一些实施例中，一种形成垂直晶体管阵列的方法包括形成包括晶体管材料的横向隔开且水平拉长的线。晶体管材料包括沟道区，其将成为个别垂直晶体管。位于晶体管-材料线之间的沟槽的侧边加衬有绝缘材料。水平拉长的导体线形成于紧接横向邻近的晶体管-材料线之间的绝缘材料加衬的沟槽的个别沟槽中。绝缘材料垂直凹入，以具有低于其间的导体线的顶部的顶部，从而形成垂直凹进部分，其横向位于导体线与导体线的每一侧边上的紧接横向邻近的晶体管-材料线的沟道区之间。导电材料形成于导体线的每一所述侧边上的垂直凹进部分中，且导电材料将导体线直接电耦合到导体线的每一侧边上的紧接横向邻近的晶体管-材料线的沟道区。切割晶体管-材料线，以形成个别地包括个别垂直晶体管的沟道区的隔开的导柱。导体线将多个垂直晶体管的导柱的沟道区中的个别沟道区直接电耦合在一起。上部源极/漏极区形成于导柱的个别沟道区上方，下部源极/漏极区形成于导柱的个别沟道区下方，且导电栅极线以操作方式形成于导柱的个别沟道区的旁边，且互连多个垂直晶体管。
在一些实施例中，一种垂直晶体管阵列包括隔开的导柱，其个别地包括个别垂直晶体管的沟道区。水平拉长的导体线将多个垂直晶体管的导柱的沟道区中的个别沟道区直接电耦合在一起。上部源极/漏极区在导柱的个别沟道区上方，下部源极/漏极区在导柱的个别沟道区下方，且导电栅极线以操作方式在导柱的个别沟道区的旁边，且互连多个垂直晶体管。
在一些实施例中，一种垂直晶体管阵列包括隔开的第一导柱，其个别地包括个别垂直晶体管的沟道区，以及在所述沟道区正上方的上部源极/漏极区。在列方向上水平拉长的导体线将多个垂直晶体管的第一导柱的沟道区中的个别沟道区直接电耦合在一起。所述导体线包括从导体线的导体材料的连续线向上突起的隔开的导电第二导柱。下部源极/漏极区在第一导柱的个别沟道区下方。导电栅极线以操作方式在第一导柱的个别沟道区旁边，且在行方向上互连多个垂直晶体管。
附图说明
图1是根据本发明的实施例的处理中衬底的一部分的图解横截面视图，并穿过图2中的线1-1截取。
图2是穿过图1中的线2-2截取的图解横截面图。
图3到27是根据本发明的一些实施例的在处理中的图1和2的构造或其部分的图解依序截面图和/或放大视图。
图28是根据本发明的一实施例的衬底的一部分的图解横截面视图。
具体实施方式
本发明的实施例包含用于形成例如可在存储器或其它集成电路中使用的晶体管阵列的方法。本发明的实施例还包含与制造方法无关的晶体管阵列。参考图1到27描述形成晶体管阵列的方法的实例实施例。
参看图1到3，示出实例衬底构造8，其包括已相对于基底衬底11制造的阵列或阵列区域10。衬底11可包括导电/导体/传导、半导电/半导体/半传导以及绝缘/绝缘体/隔绝(即，在本文中电气地)材料中的任一个。各种材料在基底衬底11上方。材料可在图1-3所描绘材料的旁边、竖向内侧或竖向外侧。举例来说，集成电路的其它部分制造或完全制造的组件可提供于基底衬底11上方、周围或内部某处。还可制造用于操作存储器阵列内的组件的控制电路和/或其它外围电路，且所述电路可或可不完全或部分地在存储器阵列或子阵列内。此外，也可相对彼此独立地、先后地或以其它方式制造和操作多个子阵列。如此文件中所使用，“子阵列”也可被视为阵列。
实例材料12(例如绝缘体材料、未掺杂或轻掺杂半导电材料、电路组件等)在基底衬底11上方。在一个实施例中，其间具有绝缘体材料16的横向隔开的金属-材料线14在材料12上方。在一个此类实施例中，金属-材料线14可包括存储器电路的数字线。实例绝缘体材料16包含二氧化硅与氮化硅的组合，例如沉积为先前形成的金属-材料线14之间的衬套层(未图示)，且可平面化回来，以提供其最上面的平面表面。
晶体管材料18在材料12上方，且在一个实施例中，直接抵靠且从而直接电耦合到金属-材料线14。晶体管材料18作为最小体可被认为包括在制造结束时将是个别垂直晶体管的沟道区。在所描绘的实例中，且在一个实施例中，晶体管材料18可被认为包括上部源极/漏极区19、下部源极/漏极区21，以及垂直位于其间的沟道区20，这将是正在制造的个别垂直晶体管。在处理中的此点处，区19、20和21可或可不本质上处于所要的导电性/半导性。无论如何，且仅作为实例，晶体管材料18可替代地包括仅一沟道区(未图示)、沟道区与仅下部源极/漏极区的组合(未图示)，或上部源极/漏极区与仅沟道区的组合(未图示)。实例晶体管材料18包含任何现有或未来开发且最终经适当掺杂的半导电材料，且其可包含LDD、卤基等区(未图示)。
参看图4和5，晶体管材料18已形成为其间具有沟槽24的横向隔开且水平拉长的线25。本文为简单起见，将所有沟槽示出为具有垂直侧壁，但所述侧壁可横向向内和/或向外渐细。线25可由任何现有或未来开发的技术形成，包含例如光刻图案化以及具有或不具有距乘法的蚀刻。在一个实施例中，晶体管-材料线25可被认为在列方向26上延伸。在一个实施例中且如所示出，晶体管-材料线25已形成于正上方、直接抵靠，且水平地沿个别金属-材料线14。将线25(和线14)示出为直线性的，但可使用曲线、相对彼此成角度的不同笔直片段的组合、笔直和弯曲片段的组合等。
参看图6和7，晶体管-材料线25之间的沟槽24的侧边已加衬有绝缘材料28(例如二氧化硅或其它低k[不大于3.9]材料)。硬掩蔽材料(例如氮化硅且未图示)可保持在晶体管-材料线25之上，且上面沉积有绝缘材料28(未图示)。
参看图8和9，导体材料30已沉积，且过填充沟槽24。实例导体材料30是导电掺杂的半导电材料，例如重导电掺杂多晶硅。薄金属-材料衬套(未图示)可首先沉积为导体材料30的一部分。替代地，且仅作为实例，导体材料30可至少主要包括金属材料。
参看图10，导体材料30已垂直凹回，从而在个别绝缘材料加衬的沟槽24中，在紧接横向邻近的晶体管-材料线25之间形成水平拉长的导体线32。在一个实施例中，导体线32形成于列方向26上。
上述处理仅为形成在紧接横向邻近的晶体管-材料线25之间具有水平拉长的导体线32的横向隔开且水平拉长的晶体管-材料线25的一个实例方法，且在一个实施例中，在形成晶体管-材料线25之后形成导体线32。可使用替代的现有或未来开发的技术。无论如何，且在一个实施例中，将晶体管-材料线25形成为比导体线32高。在一个实施例中，将导体线32示出为具有相应顶部33，且低于在个别导体线32的两个侧边上的晶体管-材料线25的沟道区20的顶部34。替代地，作为实例，导体线可形成为具有与在导体线的两个侧边上的晶体管-材料线的沟道区的顶部竖向一致的顶部(未图示)。
参看图11和12，绝缘材料28已垂直凹入(例如通过相对于材料18和30选择性地湿式蚀刻)，以具有低于其间的导体线32的相应顶部33的顶部36。这形成垂直凹进部分38，其横向在导体线32与导体线32的每一侧边上的紧接横向邻近的晶体管-材料线25的沟道区20之间。
参看图13和14，导电材料40已形成于导体线32的每一侧边上的垂直凹进部分38中，且将导体线32直接电耦合到个别导体线32的每一侧边上的紧接横向邻近的晶体管-材料线25的沟道区20。可使用任何适合的导电材料。此材料的成分可与材料30的成分相同或不同，其中示出相同成分的实例。在一个实施例中，沉积材料44，其包括未掺杂的半导电材料(例如未掺杂多晶硅)，其通过在导体线32中的增加导电性的掺杂剂的向外扩散来经导电掺杂，从而形成导电材料40。这可在材料44的沉积期间或随后发生。充足的掺杂剂向外扩散可使垂直凹进部分38上方的材料40中的一些导电，如所示出，但这不应充分高地延伸，以短路到上部源极/漏极区19。作为替代实例，可将金属材料沉积到垂直凹进部分38中。
参看图15，导电材料40已经任选地从导体线32的顶部33去除(例如通过短各向同性或通过各向异性刻蚀)。图16和17示出涂在晶体管-材料线25的侧面的实例材料44之间的绝缘体材料46(例如二氧化硅)的后续形成。
上述处理仅为形成将电耦合到导体线32的两个侧边上的晶体管-材料线25的沟道区20的导体线32的一个实例方法。可使用任何替代现有或未来开发的技术。上述也是仅一个实例实施例，其中导体线32最初形成为不直接电耦合到沟道区20，其中通过形成直接抵靠且横跨其两个侧边上的导体线32与沟道区20之间的导电材料40，导体线32随后直接电耦合到沟道区20。
参看图18到22，晶体管-材料线25(数值上未指定)已切割(例如通过光刻图案化，以及具有或不具有距乘法的蚀刻)，以形成个别地包括沟道区20的隔开的导柱48。在一些实施例中，导柱48被称作第一导柱48，以与下文所识别的第二导柱区分开。无论如何，导体线32将正形成(例如在列方向26上)的多个垂直晶体管的导柱48的个别沟道区20直接电耦合在一起。在一个实施例中且如所示出，切割不是完全穿过晶体管-材料线25的晶体管材料18，因此留下晶体管材料18的连续线52(下部源极/漏极区21)水平铺设在导柱48下方，且导柱48从其向上突起。
在一个实施例中且如所示出，导体线32也已经切割，以形成从导体线32的导体材料30的连续线54向上突起的隔开的导电柱50(在一些实施例中，被称作第二导柱50)。在一个此类实施例中且如所示出，切割晶体管-材料线25和切割导体线32的动作将单个/共用掩蔽步骤用于两者。举例来说且作为实例，可在行方向65商，在晶体管-材料线25和绝缘体材料46顶上提供经图案化的掩蔽材料(未图示)，其中如上文所描述相对于晶体管-材料线25和导体线32的切割动作基本上在相同时间或至少在相同的单个共用掩蔽步骤中发生，且形成所说明的沟槽55。
最终形成导柱的个别沟道区上方的上部源极/漏极区和导柱的个别沟道区下方的下部源极/漏极区。在所描绘的实例实施例中，上部源极/漏极区19和下部源极/漏极区21已形成于个别导柱48中。将下部源极/漏极区19示出为个别导柱48和连续线52的一部分。替代地，作为实例，下部源极/漏极区可整体形成于导柱48下方(未图示)，和/或上部源极/漏极区可至少部分地形成导柱48上方(未图示)。
图23到27示出后续处理，借此导电栅极线60(两者均示出)已经以操作方式形成于导柱48的个别沟道区20的旁边，从而形成垂直晶体管75(为了绘制的清晰，仅示出几个轮廓75)。栅极线60互连多个垂直晶体管75(例如在行方向65上)。栅极绝缘体61位于导电栅极线60与沟道区20之间。在一个实施例中且如所示出，导体线32和导电栅极线60相对彼此成角度(即，除平角之外)，其中在一个此类实施例中，导电栅极线60在行方向65上形成。可使用任何合适的现有或未来开发的方法来形成图23到27的实例构造。作为实例，在形成栅极绝缘体61之后，将在沟槽55中形成绝缘体或牺牲材料，以具有将成为导电栅极线60的底部表面的顶表面。导电栅极线的一层导电材料接着将沉积到线型沟槽55，接着将以与形成间隔物类似的方式各向异性地蚀刻回来，以将其从水平表面大体上去除，且形成所描绘的导电栅极线60。如果使用牺牲材料，那么现在可将其去除。无论如何，将沉积绝缘体材料76(例如二氧化硅和/或氮化硅)来填充沟槽55的剩余体积。
可相对于上述实施例使用如本文中关于其它实施例所示和/或描述的任何其它属性或方面。
上文所述并示出的实施例形成直接抵靠导体线32的侧边45(图14、15、17、22、27)的导电材料40。图22和27还示出实例实施例，其中直接抵靠导体线32的导电材料40形成为在成品构造中仅直接抵靠导体线32的侧边(实例导电柱50固有地是导体线32的一部分)。替代地且仅作为实例，导电材料可形成为在成品构造中直接抵靠导体线的顶部，且在一个此类实施例中，在成品构造中仅直接抵靠导体线的顶部。举例来说，且仅作为实例，如果不进行图14的产生图15的构造的实例蚀刻，那么图14的构造的材料30和40将在成品构造中，借此导电材料40直接抵靠导体线顶部33。参考图28描述示出构造8a的替代实例。已在适当时使用来自上文所描述的实施例的相同标号，其中用后缀“a”或用不同标号指示某些构造差异。实例导电材料40a，其中直接抵靠导体线32，示出为在成品构造中仅直接抵靠导体线32的顶部33(实例导电柱50固有地是导体线32的一部分)。可使用如所示出和/或本文中关于其它实施例所描述的任何其它属性或方面。
上述仅为形成晶体管阵列的实例方法。这可或可不包括存储器电路的一部分，其中个别晶体管可或可不包括存储单元阵列的存储器单元的一部分。因此且无论如何，集成电路结构的处理和形成可在并入有实例晶体管75的集成电路的进一步制造中，在如图所示且上文所述的处理之前或之后发生。
垂直晶体管75的阵列10可固有地包括存储器单元，其中例如栅极绝缘体61包括可编程材料，例如铁电材料，和/或其中垂直晶体管包括可编程电荷储存结构作为其相应栅极构造(未图示)的一部分。替代地且仅作为实例，存储装置，例如电荷储存装置，例如电容器85(示意性地示出)可个别地耦合到个别上部源极/漏极区19，借此形成存储器单元90，其个别地包括电容器85和晶体管75(为了清楚起见，图24、27和28中的每一者中仅示出一个轮廓90)。替代地且仅作为实例，交叉点存储器单元(未图示)可形成于上部源极/漏极区19上方，其中晶体管75充当选择装置。进一步替代地且仅作为实例，存储装置可形成于所描绘的结构(未图示)下方，且直接电耦合到下部源极/漏极区21和上部源极/漏极区19，其耦合到数字线(未图示)。
本发明的实施例包含与制造方法无关的晶体管阵列。然而，此阵列可具有如本文中在方法实施例中所描述的属性中的任一个。同样地，上文所描述的方法实施例可并入有且形成相对于装置实施例描述的属性中的任一个。
本发明的实施例包含垂直晶体管(例如75)的阵列(例如10)，其包括隔开的导柱(例如48)，所述导柱个别地包括个别垂直晶体管的沟道区(例如20)。水平拉长的导体线(例如32/54/50)将多个垂直晶体管的导柱的个别沟道区直接电耦合在一起。上部源极/漏极区(例如19)在导柱的个别沟道区上方，且下部源极/漏极区(例如21)在导柱的个别沟道区下方。导电栅极线(例如60)以操作方式在导柱的个别沟道区旁边，且互连多个垂直晶体管。可使用如所示出和/或本文中关于其它实施例所描述的任何其它属性或方面。
本发明的实施例包含垂直晶体管(例如75)的阵列(例如10)，其包括隔开的第一导柱(例如48)，所述导柱个别地包括个别垂直晶体管的沟道区(例如20)以及在所述沟道区正上方的上部源极/漏极区(例如19)。导体线(例如32/54/50)在列方向(例如26)上水平拉长，且将多个垂直晶体管的第一导柱的沟道区中的个别沟道区直接电耦合在一起。所述导体线包括从导体线的导体材料(例如30)的连续线(例如54)向上突起的隔开的导电第二导柱(例如50)。下部源极/漏极区(例如21)在第一导柱的个别沟道区下方。导电栅极线(例如60)以操作方式在第一导柱的个别沟道区旁边，且在行方向(例如65)上互连多个垂直晶体管。可使用如所示出和/或本文中关于其它实施例所描述的任何其它属性或方面。
上述处理或构造可被视为与组件阵列相关，所述组件阵列形成为底层的基底衬底上方或作为底层的基底衬底的部分的此类组件的单个堆叠或单个叠组或在所述单个堆叠或单个叠组内(但所述单个堆叠/叠组可具有多个层)。用于操作或存取阵列内的此类组件的控制和/或其它外围电路系统还可作为成品构造的部分形成于任何位置，且在一些实施例中可在阵列下方(例如，阵列下CMOS)。无论如何，一或多个额外此类堆叠/叠组可提供或制造于图中示出或上文描述的堆叠/叠组上方和/或下方。另外，组件的阵列在不同堆叠/叠组中可相对于彼此相同或不同，且不同堆叠/叠组可相对于彼此具有相同的厚度或不同厚度。介入结构可提供于竖直紧邻的堆叠/叠组之间(例如，额外电路和/或电介质层)。并且，不同堆叠/叠组可相对彼此电耦合。多个堆叠/叠组可以单独地且依序地(例如，一个在另一个顶上)制造，或两个或更多个堆叠/叠组可以基本上同时制造。
上文所论述的组合件和结构可用于集成电路/电路系统中且可并入于电子系统中。此类电子系统可用于例如存储器模块、装置驱动器、功率模块、通信调制解调器、处理器模块和专用模块中，且可包含多层、多芯片模块。电子系统可以是以下广泛范围的系统中的任一个：例如相机、无线装置、显示器、芯片组、机顶盒、游戏、照明、交通工具、时钟、电视机、手机、个人计算机、汽车、工业控制系统、飞机等。
在本文中，除非另外指明，否则“竖向”、“更高”、“上部”、“下部”、“顶部”、“顶上”、“底部”、“上方”、“下方”、“在...之下”、“在...下面”、“上”和“下”大体上参照垂直方向。“水平”指代沿着主衬底表面的大体方向(即，在10度内)，且可相对于在制造期间处理的衬底，且垂直是大体与其正交的方向。提及“恰好水平”是指沿着主衬底表面(即，与所述表面不形成度数)，且在制造期间处理衬底可相对的方向。此外，如本文中所使用的“垂直”和“水平”是相对于彼此的大体上垂直方向，且与三维空间中衬底的定向无关。另外，“竖向延伸”和“竖向地延伸”是指从恰好水平偏离至少45°的方向。此外，相对于场效晶体管“竖向地延伸”、“竖向延伸的”、“水平地延伸”、“水平延伸的”以及其类似者是参考晶体管的沟道长度的定向，在操作中电流在源极/漏极区之间沿着所述定向流动。对于双极结晶体管，“竖向地延伸”、“竖向延伸的”、“水平地延伸”、“水平延伸的”以及其类似者是参考基底长度的定向，在操作中，电流在发射极与集极之间沿着所述定向流动。在一些实施例中，竖向延伸的任何组件、特征和/或区垂直或在垂直的10°内延伸。
此外，“正上方”、“处于正下方”和“正下方”要求两个所陈述区/材料/组件相对于彼此的至少一些橫向重叠(即，水平地)。而且，使用前面没有“正”的“上方”仅要求在另一所陈述区/材料/组件上方的所陈述区/材料/组件的某一部分从另一所陈述区/材料/组件的竖向向外(即，与两个所陈述区/材料/组件是否存在任何橫向重叠无关)。类似地，使用前面没有“正”的“下方”和“下面”仅要求在另一所陈述区/材料/组件下方/下面的所陈述区/材料/组件的某一部分在另一所陈述区/材料/组件的竖向向内(即，与否存在两个所陈述区/材料/组件的任何横向重叠无关)。
本文中所描述的材料、区和结构中的任一个可以是均匀的或非均匀的，且无论如何在其上覆的任何材料上方可以是连续的或不连续的。当针对任何材料提供一或多种实例成分时，所述材料可包括此一或多种成分、主要由此一或多种成分组成或由此一或多种成分构成。此外，除非另行说明，否则可使用任何合适的现有或未来开发的技术来形成每一材料，其中原子层沉积、化学气相沉积、物理气相沉积、外延生长、扩散掺杂和离子植入是实例。
另外，单独使用的“厚度”(前面无方向性形容词)被定义为从具有不同成分的紧邻材料或紧邻区的最接近表面垂直穿过给定材料或区的平均直线距离。另外，本文中所描述的各种材料或区可具有大体上恒定的厚度或具有可变的厚度。如果具有可变的厚度，那么除非另有指示，否则厚度是指平均厚度，且此类材料或区由于厚度可变而将具有某一最小厚度和某一最大厚度。如本文中所使用，“不同成分”仅要求两个所陈述材料或区域的可彼此直接抵靠的那些部分在化学上和/或在物理上不同，例如在此类材料或区域不均匀的情况下。如果两个所陈述材料或区彼此并未直接抵靠，那么在此类材料或区并不均匀的情况下，“不同成分”仅要求两个所陈述材料或区的彼此最接近的那些部分在化学上和/或在物理上不同。在本文中，当所陈述材料、区或结构相对于彼此存在至少某一物理接触时，所述材料、区或结构“直接抵靠”另一材料、区或结构。相比之下，前面没有“正”的“上方”、“上”、“邻近”、“沿着”和“抵靠”涵盖“直接抵靠”以及其中居间材料、区域或结构使得所陈述材料、区域或结构相对于彼此无物理接触的构造。
在本文中，如果在正常操作中，电流能够从一个区域/材料/组件连续流动到另一区域/材料/组件，且在充足地产生亚原子正和/或负电荷时主要通过所述亚原子正和/或负电荷的移动来进行流动，那么所述区域/材料/组件相对于彼此“电耦合”。另一电子组件可在所述区域-材料-组件之间且电耦合到所述区域-材料-组件。相比之下，当区-材料-组件被称作“直接电耦合”时，直接电耦合的区-材料-组件之间没有介入的电子组件(例如，没有二极管、晶体管、电阻器、换能器、交换器、熔断器等)。
在本文中使用“行”和“列”是为了方便区分一个系列或定向的特征与另一系列或定向的特征，且组件已经或可沿着所述“行”和“列”形成。“行”和“列”相对于任何系列的区、组件和/或特征同义地使用，与功能无关。无论如何，行可以是相对于彼此直的和/或弯曲和/或平行和/或不平行，列可同样如此。此外，行和列可相对于彼此以90°或以一或多个其它角度(即，除平角之外)相交。
本文中的导电/导体/传导材料中的任一者的成分可以是金属材料和/或导电掺杂的半导电/半导体/半传导材料。“金属材料”是元素金属、两种或大于两种元素金属的任何混合物或合金以及任何一或多种导电金属化合物中的任一者或组合。
在本文中，关于蚀刻(etch，etching)、移除、沉积、形成(forming)和/或形成(formation)而对“选择性”的任何使用是一种所陈述材料相对于所作用的另一种所陈述材料以至少2:1的体积比率进行的此类动作。此外，对选择性地沉积、选择性地生长或选择性地形成的任何使用是以至少2:1的体积比率使一种材料相对于另一种或多种所陈述材料沉积、生长或形成达至少第一75埃的沉积、生长或形成。
除非另有指示，否则本文中“或”的使用涵盖任一者和两者。
结论
根据规定，已经就结构和方法特征来说以更具体或更不具体的语言描述了本文中所公开的标的物。然而，应理解，所附权利要求书不限于所示出和描述的特定特征，因为本文中所公开的装置包括实例实施例。因此，所附权利要求书被赋予如书面所说明的整个范围，且应根据等效物原则恰当地进行解释。

Claims (43)

1.一种形成垂直晶体管阵列的方法，其包括：
形成包括晶体管材料的横向隔开且水平拉长的线，以及位于紧接横向邻近的所述晶体管-材料线之间的水平拉长的导体线，所述晶体管材料包括沟道区，其将成为个别垂直晶体管，所述导体线直接电耦合到所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区；
切割所述晶体管-材料线，以形成个别地包括所述个别垂直晶体管的所述沟道区的隔开的导柱，所述导体线将多个所述垂直晶体管的所述导柱的所述沟道区中的个别沟道区直接电耦合在一起；以及
在所述导柱的所述个别沟道区上方形成上部源极/漏极区，在所述导柱的所述个别沟道区下方形成下部源极/漏极区，且形成导电栅极线，所述导电栅极线以操作方式在所述导柱的所述个别沟道区的旁边，且互连多个所述垂直晶体管。
2.根据权利要求1所述的方法，其包括在形成所述晶体管-材料线之后形成所述导体线。
3.根据权利要求1所述的方法，其包括将所述晶体管-材料线形成为比所述导体线高。
4.根据权利要求1所述的方法，形成所述导体线以具有低于在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区的顶部的顶部。
5.根据权利要求1所述的方法，形成所述导体线以具有与在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区的顶部竖向重合的顶部。
6.根据权利要求1所述的方法，其中，
最初将所述导体线形成为不直接电耦合到所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区；且
在形成所述晶体管-材料线和所述导体线之后，通过形成直接抵靠且横跨所述导体线与所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区之间的导电材料，所述导体线直接电耦合所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区。
7.根据权利要求6所述的方法，其包括将所述导电材料形成为在成品构造中直接抵靠所述导体线的侧边。
8.根据权利要求7所述的方法，其包括形成所述导电材料，其在所述成品构造中，直接抵靠将仅直接抵靠所述导体线的所述侧边的所述导体线。
9.根据权利要求6所述的方法，其包括将所述导电材料形成为在成品构造中直接抵靠所述导体线的顶部。
10.根据权利要求9所述的方法，其包括形成所述导电材料，其在所述成品构造中，直接抵靠将仅直接抵靠所述导体线的所述顶部的所述导体线。
11.根据权利要求1所述的方法，其中所述切割并不完全穿过所述晶体管-材料线的所述晶体管材料，因此留下所述晶体管材料的连续线，其水平铺设在所述导柱下方，且所述导柱从其向上突起。
12.根据权利要求1所述的方法，其包括切割所述导体线，以形成从所述导体线的导体材料的连续线向上突起的隔开的导电柱。
13.根据权利要求12所述的方法，其中所述晶体管-材料线的所述切割和所述导体线的所述切割将单个共用掩蔽步骤用于两者。
14.根据权利要求1所述的方法，其包括在个别金属-材料线正上方、直接抵靠所述个别金属-材料线以及水平地沿所述个别金属-材料线形成所述晶体管-材料线。
15.根据权利要求1所述的方法，其包括将所述导体线和所述导电栅极线形成为相对于彼此成角度。
16.根据权利要求1所述的方法，其包括在所述导柱中的个别导柱中形成所述上部源极/漏极区。
17.根据权利要求1所述的方法，其包括在所述导柱的个别导柱中形成所述下部源极/漏极区。
18.根据权利要求1所述的方法，其包括在所述导柱的个别导柱中形成所述上部和下部源极/漏极区。
19.根据权利要求1所述的方法，其包括将所述垂直晶体管形成为包括存储器阵列的个别存储器单元。
20.一种形成垂直晶体管阵列的方法，其包括：
在列方向上形成横向隔开且水平拉长的晶体管-材料线；所述晶体管材料包括上部源极/漏极区、下部源极/漏极区和垂直在其间的沟道区，其将为个别垂直晶体管；在形成所述晶体管-材料线之后，在紧接横向邻近的所述晶体管-材料线之间，在所述列方向上形成水平拉长的导体线；
在形成所述导体线之后，形成导电材料，其将所述导体线直接电耦合到在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区；
在单个掩蔽步骤中，切割：
(a)所述晶体管-材料线，以形成隔开的第一导柱，其个别地包括所述个别垂直晶体管的所述沟道区，所述导体线在所述列方向上将多个所述垂直晶体管的所述第一导柱的所述沟道区中的个别沟道区直接电耦合在一起；以及
(b)所述导体线，以形成隔开的导电第二导柱，其从所述导体线的导体材料的连续线向上突起；以及
形成导电栅极线，其以操作方式在所述第一导柱的所述个别沟道区旁边，且在行方向上互连多个所述垂直晶体管。
21.根据权利要求20所述的方法，形成所述导体线以具有低于在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区的顶部的顶部。
22.根据权利要求20所述的方法，形成所述导体线以具有与在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区的顶部竖向重合的顶部。
23.根据权利要求20所述的方法，其中所述切割并不完全穿过所述晶体管-材料线的所述晶体管材料，因此留下所述晶体管材料的连续线，其水平铺设在所述第一导柱下方，且所述第一导柱从其向上突起，所述连续线包括所述个别晶体管的所述下部源极/漏极区。
24.根据权利要求20所述的方法，其包括将所述导电材料形成为在成品构造中直接抵靠所述导体线的侧边。
25.根据权利要求20所述的方法，其包括将所述导电材料形成为在成品构造中直接抵靠所述导体线的顶部。
26.一种形成垂直晶体管阵列的方法，其包括：
形成包括晶体管材料的横向隔开且水平拉长的线，所述晶体管材料包括沟道区，其将成为个别垂直晶体管；
用绝缘材料来为位于所述晶体管-材料线之间的沟槽的侧边加衬；
将水平拉长的导体线形成于紧接横向邻近的所述晶体管-材料线之间的所述绝缘材料加衬的沟槽的个别沟槽中；
使所述绝缘材料垂直凹进，以具有低于其间的所述导体线的顶部的顶部，从而形成横向在所述导体线与在所述导体线的每一侧边上的所述紧接横向邻近的晶体管-材料线的所述沟道区之间的垂直凹进部分；
将导电材料形成于所述导体线的每一所述侧边上的所述垂直凹进部分中，且所述导电材料将所述导体线直接电耦合到所述导体线的每一侧边上的所述紧接横向邻近的晶体管-材料线的所述沟道区；
切割所述晶体管-材料线，以形成个别地包括所述个别垂直晶体管的所述沟道区的隔开的导柱，所述导体线将多个所述垂直晶体管的所述导柱的所述沟道区中的个别沟道区直接电耦合在一起；以及
在所述导柱的所述个别沟道区上方形成上部源极/漏极区，在所述导柱的所述个别沟道区下方形成下部源极/漏极区，且形成导电栅极线，所述导电栅极线以操作方式在所述导柱的所述个别沟道区的旁边，且互连多个所述垂直晶体管。
27.根据权利要求26所述的方法，其中所述切割并不完全穿过所述晶体管-材料线的所述晶体管材料，因此留下所述晶体管材料的连续线，其水平铺设在所述导柱下方，且所述导柱从其向上突起。
28.根据权利要求26所述的方法，其包括切割所述导体线，以形成从所述导体线的导体材料的连续线向上突起的隔开的导电柱。
29.根据权利要求26所述的方法，其包括将所述导体线和所述导电栅极线形成为相对于彼此成角度。
30.一种垂直晶体管阵列，其包括：
隔开的导柱，其个别地包括个别垂直晶体管的沟道区；
水平拉长的导体线，其将多个垂直晶体管的所述导柱的所述沟道区中的个别沟道区直接电耦合在一起；以及
在所述导柱的所述个别沟道区上方的上部源极/漏极区，在所述导柱的所述个别沟道区下方的下部源极/漏极区，以及导电栅极线，其以操作方式在所述导柱的所述个别沟道区的旁边，且互连多个所述垂直晶体管。
31.根据权利要求30所述的阵列，其中所述导体线具有低于在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区的顶部的顶部。
32.根据权利要求30所述的阵列，其中所述导体线具有与在所述导体线的两个侧边上的所述晶体管-材料线的所述沟道区的顶部竖向重合的顶部。
33.根据权利要求30所述的阵列，其中所述导电材料直接抵靠所述导体线的侧边。
34.根据权利要求33所述的阵列，其中直接抵靠所述导体线的所述导电材料仅直接抵靠所述导体线的所述侧边。
35.根据权利要求30所述的阵列，其中所述导电材料直接抵靠所述导体线的顶部。
36.根据权利要求35所述的阵列，其中直接抵靠所述导体线的所述导电材料仅直接抵靠所述导体线的所述顶部。
37.根据权利要求30所述的阵列，其中所述晶体管材料的连续线水平铺设在所述导柱下方，且所述导柱从其向上突起。
38.根据权利要求30所述的阵列，其中所述导体线和所述导电栅极线相对于彼此成角度。
39.根据权利要求30所述的阵列，其中所述上部源极/漏极区位于所述导柱的个别导柱中。
40.根据权利要求30所述的阵列，其中所述下部源极/漏极区位于所述导柱的个别导柱中。
41.根据权利要求30所述的阵列，其中所述上部和下部源极/漏极区位于所述导柱的个别导柱中。
42.根据权利要求30所述的阵列，其中所述垂直晶体管包括存储器阵列的个别存储器单元。
43.一种垂直晶体管阵列，其包括：
隔开的第一导柱，其个别地包括个别垂直晶体管的沟道区，以及在所述沟道区正上方的上部源极/漏极区；
导体线，其在列方向上水平拉长，所述导体线将多个所述垂直晶体管的所述第一导柱的所述沟道区的个别沟道区直接电耦合在一起，所述导体线包括从所述导体线的导体材料的连续线向上突起的隔开的导电第二导柱；
下部源极/漏极区，其在所述第一导柱的所述个别沟道区下方；以及
导电栅极线，其以操作方式在所述第一导柱的所述个别沟道区旁边，且在行方向上互连多个所述垂直晶体管。
CN202010909151.4A 2019-09-03 2020-09-02 垂直晶体管阵列以及形成垂直晶体管阵列的方法 Pending CN112447716A (zh)

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