CN112435925B - Process method of ONO side wall - Google Patents

Process method of ONO side wall Download PDF

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Publication number
CN112435925B
CN112435925B CN202011361902.XA CN202011361902A CN112435925B CN 112435925 B CN112435925 B CN 112435925B CN 202011361902 A CN202011361902 A CN 202011361902A CN 112435925 B CN112435925 B CN 112435925B
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layer
thickness
side wall
ono
teos
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CN112435925A (en
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任小兵
熊伟
陈华伦
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Hua Hong Semiconductor Wuxi Co Ltd
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Hua Hong Semiconductor Wuxi Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention discloses a process method of an ONO side wall, which enables TOES layers at the minimum silicon gate spacing to be connected into a whole by increasing the thickness of TEOS at the outermost layer. After the etching starts, the TEOS of the sparse region is etched normally. Dense areas require etching the TEOS with the top connections. After the TEOS on the top is etched, the TEOS on the side wall of the silicon gate is etched, so that the time for the TEOS on the side wall of the polycrystalline silicon gate in the sparse region to be subjected to transverse etching is longer than that of the TEOS in the dense region, the difference that the transverse thickness of the sparse region is larger than that of the dense region is balanced, the width of SiN in the middle layer of the side wall is determined by the transverse thickness of the TEOS, and the difference of the thickness of the side wall between the dense region and the sparse region is balanced finally.

Description

Process method of ONO side wall
Technical Field
The invention relates to the field of semiconductors, in particular to a process method of an ONO side wall.
Background
In the manufacture of a submicron integrated circuit, a source-drain lightly doped region is defined by a side wall process, and the width of the source-drain lightly doped region has important influence on the threshold voltage, the leakage current and the saturation current of a short-channel device.
The ONO sidewall spacer is a sidewall formation process that is very widely used. As shown in the left diagram of fig. 1, the Gate (Gate) is in the middle and the first layer (inner layer) of the Gate outer wrap is a thin LPTEOS (low pressure TEOS) layer, about 150 a. The second layer is LPSiN (silicon nitride formed by LPCVD process) and is approximately 300 a thick. The third layer (close to the outer layer) is thicker LPTEOS, and the thickness range is 400-1000A.
After the ONO side wall is etched, the transverse width of the L-shaped SiN and the thickness of the first layer of LPTEOS on the side wall of the polycrystalline silicon are combined to form the width of the side wall. As shown in the right drawing of fig. 1. The lateral width of the "L" type SIN is essentially determined by the thickness of the uppermost TEOS layer on the sidewall, but since the TEOS is laterally etched at the TEOS over-etching stage, the sidewall width is greatly affected by the over-etching time.
In the submicron integrated circuit, the thickness of TEOS at the outermost layer of the ONO side wall is in the same order of magnitude as the distance between the polysilicon grid bars. In the dense bar regions and the sparse regions of the polysilicon gate, a fill effect begins to occur. The sidewall TOES of the sparse region is deposited to a thickness greater than that of the dense region. Therefore, the width of the final sidewall is also larger than that of the sparse region than that of the dense region, as shown in fig. 2.
The difference in the width of the side walls between the dense area and the sparse area reduces the yield window. And this difference cannot be compensated for by an OPC (Optical Proximity Correction) technique.
The sidewall width has a tendency to decrease as the gate pitch decreases, as shown in fig. 3. Mainly in the booth apart from the district, the side wall width reduces very fast, and is bigger with the district difference of dredging.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a process method of an ONO side wall, which can reduce the problem of the thickness difference of the side wall of a polysilicon dense area and a sparse area.
In order to solve the problems, the technical method of the ONO side wall forms transistors on a wafer, and the transistors are distributed unevenly to form a dense area and a sparse area of a polysilicon grid bar; when the ONO side wall of the grid is formed by deposition, after the innermost oxide layer and the middle nitride layer are deposited, the thickness of the outermost oxide layer is increased, and then etching is carried out.
The further improvement is that the lowest oxide layer is formed by an LPTEOS process, the middle layer is a silicon nitride layer formed by an LPCVD process, and the third layer is formed by an LPTEOS process.
A further improvement is that the innermost oxide layer has a thickness of 150A, the intermediate layer nitride layer has a thickness of 300A, and the outermost oxide layer has a thickness of 400-1000A.
The further improvement is that the thickness of the outermost oxide layer and the lower limit of the thickness of the outermost oxide layer at least meet the requirement of a dense area of the polycrystalline silicon grid bars, and the deposition thickness is ensured to ensure that the outermost oxide at the tops of the polycrystalline silicon grid bars and the outermost oxide deposited on the adjacent polycrystalline silicon grid bars can be connected into a whole; the upper limit of the thickness of the outermost oxide layer is that no residual TEOS exists at the minimum distance between the polysilicon grid bars after the outermost oxide layer is over-etched.
The further improvement is that the width of the side wall is increased due to the increase of the thickness of the outermost oxide layer, and the TEOS over-etching time needs to be increased for compensation.
According to the technical method of the ONO side wall, the TOES layers can be connected at the minimum silicon gate interval by increasing the thickness of the third layer, namely the TEOS (tetraethyl orthosilicate) layer at the outermost layer. After the etching starts, the TEOS of the sparse region is etched normally. Dense areas require etching the top connected TEOS first. After the TEOS at the top is etched, the TEOS on the side wall of the silicon gate is etched, so that the time for the TEOS on the side wall of the polycrystalline silicon gate in the sparse region to undergo transverse etching is more than that of the TEOS in the dense region, the difference that the transverse thickness of the sparse region is greater than that of the dense region is balanced, the width of SiN in the middle layer of the side wall is actually determined by the transverse thickness of the TEOS, and finally, the difference of the width of the side wall between the dense region and the sparse region is reduced.
Drawings
FIG. 1 is a schematic illustration of a conventional ONO sidewall film layer after deposition and after etching.
FIG. 2 is a schematic diagram of a conventional ONO sidewall spacer formation process.
Fig. 3 is a graph of gate spacing versus sidewall thickness.
FIG. 4 is a schematic diagram of an ONO sidewall spacer formation process according to the present invention.
Figure 5 is a schematic illustration of the sidewall connection formed by incomplete etching due to excessive TEOS thickness in the outermost layer.
Detailed Description
The invention is used for the process of using an ONO structure as a side wall in the manufacture of a submicron integrated circuit, and the process method of the ONO side wall is described as follows by combining the accompanying drawings:
after transistors are manufactured and formed on a wafer, due to the chip layout, the transistors are not uniformly distributed, and a polycrystalline silicon grid electrode of the transistors and a polycrystalline silicon grid bar formed by connecting the polycrystalline silicon grid electrode form a dense area and a sparse area of the polycrystalline silicon grid bar. A first layer, i.e. the innermost oxide layer, is first formed using a conventional process, typically on the basis of an LPTEOS process, deposited at a thickness of 150 a, and a second layer, i.e. an intermediate layer of silicon nitride layer, is then deposited, using an LPCVD process, to form a layer having a thickness of 300 a. Therefore, the first layer and the middle layer of the ONO side wall are deposited without difference from the traditional process, when the outermost layer of the ONO side wall of the grid is formed by deposition, the thickness of the oxide layer of the outermost layer is increased, and then etching is carried out.
The requirement of the lower limit and the upper limit of the thickness of the outermost oxide layer is met by increasing the thickness of the outermost oxide layer:
the lower limit of the thickness of the polycrystalline silicon grid bar is at least required to meet the requirement of a dense area of the polycrystalline silicon grid bar, and the deposition thickness is ensured to ensure that the outermost oxide at the top of the polycrystalline silicon grid bar can be connected with the outermost oxide deposited on the adjacent polycrystalline silicon grid bar into a whole; the upper limit of the thickness of the outermost oxide layer is that no residual TEOS exists at the minimum distance between the polysilicon grid bars after the outermost oxide layer is over-etched.
As shown in fig. 3, after depositing the third layer of TEOS with increased thickness, the TEOS layer on the top of the poly-silicon grid in the dense area will form a seal-like effect, so that the TEOS layers on the top of the adjacent poly-silicon grid are connected into a whole, and in combination with the above-mentioned thickness upper limit, the deposition of the TEOS on the uppermost layer is completed by controlling the appropriate thickness.
After the etching starts, the TEOS of the sparse region is etched normally. Dense areas require etching the TEOS with the top connections. After the TEOS at the top is etched, the TEOS on the side wall of the silicon gate can be etched, so that the time that the TEOS on the side wall of the polycrystalline silicon gate in the sparse region is subjected to transverse etching is more than that of the TEOS in the dense region, the characteristic that the TEOS is filled in the top of the interval between the polycrystalline silicon gates in the dense region to seal is utilized, the TEOS in the side wall in the dense region and the side wall in the sparse region is subjected to different etching times, the width of SiN in the middle layer of the side wall is actually determined by the transverse thickness of the TEOS, and finally the difference of the widths of the side walls in the dense region and the sparse region is reduced.
After the thickness of the outermost oxide layer is increased, the width of the sidewall is increased, and the TEOS over-etching time needs to be increased for compensation.
If the deposition thickness of the TEOS layer on the outermost layer is too large, the ONO layer in the dense region cannot be completely etched due to over-etching, and the sidewalls are still connected after etching, as shown in fig. 5, so the upper limit of the deposition thickness of the TEOS layer on the uppermost layer must be controlled.
According to the process method of the ONO side wall, the thickness of TEOS on the outermost layer is increased, so that the TOES layers can be connected at the minimum silicon gate interval, the TEOS on the side wall of the dense area and the sparse area is subjected to different etching time, and the difference of the lateral thicknesses of the TEOS in the dense area and the sparse area is balanced.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. A process method of an ONO side wall is characterized in that: forming transistors on the wafer, wherein the different layouts of the transistors form a dense area and a sparse area of the polycrystalline silicon grid bars; when an ONO side wall of a grid is formed by deposition, after an oxide layer at the innermost layer and a nitride layer at the middle layer are deposited, the thickness of the oxide layer at the outermost layer is increased, and then etching is carried out; the lower limit of the thickness of the outermost oxide layer is at least required to meet the requirement of a dense area of the polycrystalline silicon grid bars, and the deposition thickness is ensured to ensure that the outermost oxide at the tops of the polycrystalline silicon grid bars and the outermost oxide deposited on the adjacent polycrystalline silicon grid bars can be connected into a whole; the upper limit of the thickness of the outermost oxide layer is that no residual TEOS exists at the minimum distance between the polysilicon grid bars after the outermost oxide layer is over-etched.
2. The process method for fabricating the ONO spacer of claim 1, wherein: the innermost oxide layer is formed by an LPTEOS process, the middle layer is a silicon nitride layer formed by an LPCVD process, and the outermost oxide layer is formed by an LPTEOS process.
3. The process method for fabricating the ONO spacer of claim 1, wherein: the ONO side walls are sequentially deposited and cover the top and two side surfaces of the polysilicon grid bar to form a package for the polysilicon grid bar; and etching the ONO layer to form the ONO side wall of the polysilicon grid bar.
4. The process method for fabricating the ONO spacer of claim 1, wherein: the thickness of the innermost layer oxide layer is 150A, the thickness of the middle layer nitride layer is 300A, and the thickness of the outermost layer oxide layer is 400-1000A.
5. The process method for fabricating the ONO spacer as set forth in claim 1 or 2, wherein: the width of the side wall is increased due to the increase of the thickness of the outermost oxide layer, and the compensation is carried out by increasing the over-etching time of TEOS.
6. The process method for fabricating the ONO spacer of claim 1, wherein: the ONO side wall can shield the lower part of the polysilicon grid when ion implantation is carried out, so that implantation windows of a source region and a drain region are defined.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106169479A (en) * 2016-08-01 2016-11-30 上海华虹宏力半导体制造有限公司 SONOS memorizer and process
CN108133940A (en) * 2017-12-21 2018-06-08 上海华力微电子有限公司 Nonvolatile storage and its manufacturing method with side wall type selection grid
CN108666317A (en) * 2018-05-17 2018-10-16 上海华虹宏力半导体制造有限公司 Divide the manufacturing method of grid SONOS flash memories

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW591741B (en) * 2003-06-09 2004-06-11 Taiwan Semiconductor Mfg Fabrication method for multiple spacer widths
US7915129B2 (en) * 2009-04-22 2011-03-29 Polar Semiconductor, Inc. Method of fabricating high-voltage metal oxide semiconductor transistor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106169479A (en) * 2016-08-01 2016-11-30 上海华虹宏力半导体制造有限公司 SONOS memorizer and process
CN108133940A (en) * 2017-12-21 2018-06-08 上海华力微电子有限公司 Nonvolatile storage and its manufacturing method with side wall type selection grid
CN108666317A (en) * 2018-05-17 2018-10-16 上海华虹宏力半导体制造有限公司 Divide the manufacturing method of grid SONOS flash memories

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