CN112434483A - Data transmission system and generation method thereof - Google Patents

Data transmission system and generation method thereof Download PDF

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CN112434483A
CN112434483A CN202011511259.4A CN202011511259A CN112434483A CN 112434483 A CN112434483 A CN 112434483A CN 202011511259 A CN202011511259 A CN 202011511259A CN 112434483 A CN112434483 A CN 112434483A
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nodes
ports
node
intermediate transmission
input
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CN112434483B (en
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陈麒
凌长师
黄小立
王宇成
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Shenzhen Guomicrochip Technology Co ltd
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Guowei Group Shenzhen Co ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/32Circuit design at the digital level
    • G06F30/327Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

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Abstract

The invention discloses a generation method of a data transmission system and the data transmission system, and relates to the technical field of integrated circuit design and simulation verification. The method for generating the data transmission system specifically comprises the following steps: acquiring the number of input ports and output ports, wherein the number of the output ports is smaller than that of the input ports; calculating at least one layer of intermediate transmission nodes connected between the input port and the output port according to the number of the input port and the output port and the number of access ports of the intermediate transmission nodes, wherein when the intermediate transmission nodes are multi-layer, the number of the intermediate transmission nodes contained in each layer in the direction from the input port to the output port is decreased progressively; instantiating all the input ports, the intermediate transmission nodes and the output ports and conducting the input ports, the intermediate transmission nodes and the output ports to form the data transmission system. The transmission speed of the interactive circuit is improved and the fan-out of the circuit is reduced.

Description

Data transmission system and generation method thereof
Technical Field
The invention relates to the technical field of integrated circuit design and simulation verification, in particular to a generation method of a data transmission system and the data transmission system.
Background
In the SCEMI universal standard interface in software and hardware collaborative simulation, a simulation platform is conveniently built by a user, the plug and play characteristic is realized, and the user is allowed to use any plurality of interfaces and freely define the bit width of the interfaces to carry out data interaction of software and hardware.
For the implementer of the SCEMI protocol, how to collect all the SCEMI interface data of the user together needs to be considered, and data interaction of software and hardware is realized through common interfaces such as PCIE. Since the number of the user interfaces and the bit width are unpredictable in advance, the implementer of the SCEMI protocol needs to dynamically generate the corresponding processing circuit after knowing the number of the user interfaces and the bit width.
The use of a simple multiplexer to poll the data for each interface in turn results in slow transmission and, when the amount of data is large, results in excessive fan-out of the circuit (i.e., the number of devices driven behind a device). If a complex arbitration scheme is incorporated in the circuit, it would be very complicated to automatically generate the circuit according to the number of interfaces and bit width. Therefore, how to increase the transmission speed of the interactive circuit and reduce the fan-out of the circuit becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention mainly aims to provide a generation method of a data transmission system and the data transmission system, aiming at improving the transmission speed of an interactive circuit and reducing the fan-out of the circuit.
In order to achieve the above object, the present invention provides a method for generating a data transmission system, including:
acquiring the number of input ports and output ports, wherein the number of the output ports is smaller than that of the input ports;
calculating at least one layer of intermediate transmission nodes connected between the input port and the output port according to the number of the input port and the output port and the number of access ports of the intermediate transmission nodes, wherein when the intermediate transmission nodes are multi-layer, the number of the intermediate transmission nodes contained in each layer in the direction from the input port to the output port is decreased progressively;
instantiating all the input ports, the intermediate transmission nodes and the output ports and conducting the input ports, the intermediate transmission nodes and the output ports to form the data transmission system.
In an embodiment of the present application, the level and the number of layers of the intermediate transmission node are calculated by the following steps:
step 1, generating root nodes with the same number in the intermediate transmission nodes according to the number of the input ports, and continuing the next step by taking the number of the root nodes as the number of the current nodes;
and 2, the number of the current nodes is added up with the number of the access ports of the intermediate transmission nodes, the integer number of the obtained result is used as the number of the next-level nodes of the root node, the obtained number of the next-level nodes is used as the number of the current nodes, the step 2 is repeated until the obtained number of the next-level nodes is equal to the number of the output ports, and the next node at the moment is used as the tail end node of the intermediate transmission node.
In an embodiment of the present application, when a root node of the intermediate transmission node is inconsistent with a transmission frequency of data transmitted by the input port, a first cache module is disposed between the root node and the input port; and/or
When the transmission frequencies of the data transmitted between the intermediate transmission nodes are not consistent, a second cache module is arranged between the two intermediate transmission nodes; and/or
And when the transmission frequencies of the data transmitted between the end node and the output port are not consistent, a third cache module is arranged between the end node and the output port.
In an embodiment of the present application, the cache module is a FIFO memory.
In an embodiment of the present application, the number of the output ports is 1.
In an embodiment of the present application, it is set that a transmission frequency of the i +1 th layer intermediate transmission node is n times of a transmission frequency of the i th layer intermediate transmission node, where n is a port number of the intermediate transmission node, and when i takes a minimum value in a range thereof, the i th layer intermediate transmission node is a root node, and the 1 st layer intermediate transmission node is a root node.
The application also discloses a data transmission system, which comprises an input port, an output port and a control module, wherein the data transmission system is dynamically generated by the control module according to the number of the input port and the output port and the generation method of the data transmission system.
In an embodiment of the present application, the input port supports setting of a bit width of the input port.
In an embodiment of the present application, the apparatus further includes a PCIE interface connected in series to the output port and configured to implement interaction between data and the terminal.
In an embodiment of the present application, the input port is a SCEMI interface for implementing user logical access.
The number of the input modules is obtained, so that the levels and the number of the transmission modules can be obtained, and the data transmission system is constructed according to the obtained levels and the number of the transmission modules.
Drawings
The invention is described in detail below with reference to specific embodiments and the attached drawing figures, wherein:
FIG. 1 is a schematic diagram of a computing process of an intermediate transmission node in the data transmission system according to the present invention;
fig. 2 is a schematic structural diagram of a data transmission system according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and examples. It should be understood that the following specific examples are only for illustrating the present invention and are not to be construed as limiting the present invention.
In order to achieve the above object, the present invention provides a method for generating a data transmission system, including:
acquiring the number of input ports and output ports, wherein the number of the output ports is smaller than that of the input ports;
calculating at least one layer of intermediate transmission nodes connected between the input port and the output port according to the number of the input port and the output port and the number of access ports of the intermediate transmission nodes, wherein when the intermediate transmission nodes are multi-layer, the number of the intermediate transmission nodes contained in each layer in the direction from the input port to the output port is decreased progressively;
instantiating all the input ports, the intermediate transmission nodes and the output ports and conducting the input ports, the intermediate transmission nodes and the output ports to form the data transmission system.
Specifically, before generating the data transmission system, the number of input ports and output ports that a user needs to configure is obtained, where an input port in this application refers to an SCEMI port. The number of the input ports is larger than or equal to that of the output ports, so that the fan-out of the system is reduced.
Calculating and obtaining according to the number of input ports and output ports and the number of access ports of intermediate transmission nodes, wherein at least one layer of intermediate transmission nodes is arranged between the input ports and the output ports, the intermediate nodes are used for carrying out convergence transmission on data of the input ports to the output ports, and when the number of the intermediate transmission nodes is at least two layers, the number of intermediate transfer nodes contained in each layer in the direction from the input ports to the output ports of the intermediate transmission nodes is decreased; thereby reducing the fan-out of the system.
After the hierarchical arrangement of the intermediate transmission nodes is completed, all input ports, the intermediate transmission nodes and the output ports are instantiated and conducted among the input ports, the intermediate transmission nodes and the output ports to form a data transmission system.
The number of the input modules is obtained, so that the levels and the number of the transmission modules can be obtained, and the data transmission system is constructed according to the obtained levels and the number of the transmission modules.
As shown in fig. 1, in an embodiment of the present application, the level and the number of layers of the intermediate transmission node are calculated by the following steps:
step 1, generating root nodes with the same number in the intermediate transmission nodes according to the number of the input ports, and continuing the next step by taking the number of the root nodes as the number of the current nodes;
and 2, the number of the current nodes is added up with the number of the access ports of the intermediate transmission nodes, the integer number of the obtained result is used as the number of the next-level nodes of the root node, the obtained number of the next-level nodes is used as the number of the current nodes, the step 2 is repeated until the obtained number of the next-level nodes is equal to the number of the output ports, and the next node at the moment is used as the tail end node of the intermediate transmission node.
The specific decomposition process is as follows:
step 1.1: acquiring the number of input ports, calculating the number of root nodes according to the number of the input ports, and taking the number of the root nodes as the number of current nodes;
step 2.1: judging whether the number of the current nodes is zero or not;
step 3.1: if the current number is not zero, executing the step 4.1; if the current node is zero, executing step 7.1;
step 4.1: calculating the number of next nodes according to the current root node;
step 5.1: judging whether the number of the next nodes is less than or equal to a preset threshold value or not;
step 6.1: if the number of the next nodes is larger than the preset threshold value, the next node number is taken as the current node, and the step 4.1 is returned; if the value is less than or equal to the preset threshold value, executing the step 8.1;
step 7.1: instantiating all the input modules and the output modules and conducting the input modules and the output modules to generate a single link;
step 8.1: instantiating all input modules, pass modules and output modules and conducting the input modules, output modules and pass modules and generating a single link.
In step 1.1, the number of the input ports is obtained, that is, obtained through input or through a polling manner, specifically, the number of the input ports is defined as integer data, and the number of the input ports is complemented with the number of access ports of the intermediate transmission node, where an integer part in a complementation result is the number of transfer modules directly connected to the input module, that is, a root node.
In step 2.1, whether the integer part in the remainder result is greater than zero is judged, when the integer part in the remainder result is greater than zero, at least one layer of root nodes directly connected with the input port is represented, and when the integer part in the remainder result is equal to zero, the number of the root nodes directly connected with the input module is represented to be zero, that is, data transmission is performed without using intermediate transmission nodes in a transmission system, and the input port is directly connected with the output port.
When the integer part in the remainder result is larger than zero, that is, there is at least one layer of intermediate transfer node, in step 4.1, taking the intermediate transfer module directly connected with the input port as the current node, obtaining the number of the next node according to the number of the current node, continuing to remainder the number of the next intermediate transfer node and the number of the intermediate transfer node access ports, wherein the integer part is the number of the next intermediate transfer node, recording the hierarchy of the intermediate transfer node and the number information of the intermediate output nodes corresponding to the hierarchy, and continuing to judge whether the number of the next intermediate transfer node plus the remainder is less than or equal to the number of the output port input interfaces.
In step 5.1, when the number of next intermediate transfer nodes plus the remainder is less than or equal to the number of input interfaces of the output module, the information of the hierarchy of the intermediate transfer nodes and the number of transfer modules corresponding to the hierarchy is output. And when the number of the next intermediate transmission nodes plus the remainder is greater than the number of the input interfaces of the output module, returning the number of the next nodes as the number of the current nodes to 4.1 until the number of the transmission modules plus the remainder is less than or equal to the number of the input interfaces of the output module, and terminating.
Examples are as follows:
example 1, the number of interfaces is defined as 6, the number of incoming interfaces of the transfer module is 2, and the number of incoming interfaces of the output module is 2;
the number of the input modules is 6 according to the number of the interfaces 6. And (3) the acquired number 2 of the input modules 6 and the transmission interfaces of the transmission modules is complemented to obtain a result of 3-0, wherein 3 is the number of the transmission modules. Because 3 is greater than 0 and 3 adds 0 and is greater than 2 of the interface quantity that comes into of output module, define 3 transmission modules as last level transmission module this moment, continue 3 transmission modules of last level transmission module to be complemented with the quantity 2 of the interface that comes into of transmission module, the result is 1 surplus 1 for the quantity of transmission module, 1 of the quantity of transmission module this moment adds 1 remainder 1 and is less than or equal to the quantity 2 of the interface that comes into of input module, the output result: the number of the transmission modules is 2, the number of the transmission modules of the first stage is 3, and the number of the transmission modules of the second stage is 1.
Example 2, the number of the interfaces is defined to be 6, the number of the incoming interfaces of the transmission module is 2, and the number of the incoming interfaces of the output module is 3;
the number of the input modules is 6 according to the number of the interfaces 6. And (3) the acquired number 2 of the input modules 6 and the transmission interfaces of the transmission modules is complemented to obtain a result of 3-0, wherein 3 is the number of the transmission modules. Since the number 3 of the transfer modules is greater than 0, but the number 3 of the transfer modules plus 0 is less than or equal to the number 3 of the incoming interfaces of the output module, the result is directly output: the number of pass modules is 1 stage and the number of pass modules of the first stage is 3.
Example 3, the number of the interfaces is defined to be 6, the number of the incoming interfaces of the transfer module is 3, and the number of the incoming interfaces of the output module is 2;
the number of the input modules is 6 according to the number of the interfaces 6. The obtained number 3 of the input module 6 and the incoming interface of the transmission module is complemented to obtain a result of 2-0, wherein 2 is the number of the transmission module, and since the number 2 of the transmission module is greater than 0, but the number 2 of the transmission module plus 0 is less than or equal to the number 2 of the incoming interface of the output module, the result is directly output: the transfer modules are of level 1 and the number of first transfer modules is 2.
In an embodiment of the present application, when a root node of the intermediate transmission node is inconsistent with a transmission frequency of data transmitted by the input port, a first cache module is disposed between the root node and the input port; and/or
When the transmission frequencies of the data transmitted between the intermediate transmission nodes are not consistent, a second cache module is arranged between the two intermediate transmission nodes; and/or
And when the transmission frequencies of the data transmitted between the end node and the output port are not consistent, a third cache module is arranged between the end node and the output port.
The first buffer module, the second buffer module and the third buffer module are FIFO memories, which are simply FIFO memories, the first buffer module is arranged between the root node and the input port, the second buffer module is arranged between two intermediate transmission nodes, and the third buffer module is arranged between the end node and the output port, so that the transmission rate between each node or port is increased. Through the FIFO memory, the data with low transmission rate is temporarily stored in the FIFO memory, and then the data is transmitted out in a high-rate mode, so that the technical problem that the data transmission is slow due to unmatched or unequal transmission rates is solved, and the transmission efficiency of the data is improved.
In an embodiment of the present application, the cache module is a FIFO memory.
In an embodiment of the present application, the number of the output ports is 1.
In an embodiment of the present application, the transmission frequency of the i +1 th layer intermediate transmission node is set to be n times of the transmission frequency of the i layer intermediate transmission node, where n is the number of ports of the intermediate transmission node, and when i is the minimum value in the range, the i layer intermediate transmission node is a root node.
Specifically, when the range of i is defined as i ≧ 1, i =1, which indicates that the first-layer intermediate transmission node is a root node; when the range of i is i ≧ 0, i =0 indicates that the intermediate transfer node of the zeroth layer is the root node.
By adopting the technical scheme, the data transmission efficiency is improved.
As shown in fig. 2, the present application further discloses a data transmission system, which includes an input port and an output port, and a control module, where the data transmission system is dynamically generated by the control module according to the number of the input port and the output port according to the generation method of the data transmission system.
Including a printed circuit board for connecting various electrical components, which contains the relevant components for making the relevant devices normally communicate, and is not described in detail herein since it is prior art. The printed circuit board is connected with an input port, the input port in the application is an SCEMI interface, and of course, other interfaces can be adopted for data transmission according to the design requirement, including but not limited to USB, MAC interfaces and the like, and the input port is used for connecting external equipment.
The printed circuit board is connected with an input module in communication connection with the input port, where the input module is used to process a time sequence of input port data input and send data with any bit width according to a fixed bit width, and the example is as follows: when channel information is generated, setting bit widths of an input port and an intermediate transmission node, and when transmitted data is less than one bit width data, supplementing the transmitted data to one bit width data for sending; when the transmitted data exceeds one bit width, the transmitted data is divided into a plurality of equal parts according to the fixed bit width and is sequentially sent out, and the data which is less than one bit width after the division is supplemented and then sent out.
The circuit board is provided with an output port, and the output port is used for acquiring the user logic input by the input port and forwarding the user logic to the computer terminal.
When the number of the input ports is larger than that of the input ports of the output ports, an intermediate transfer node is generated, the intermediate transfer node, the input module and the output module are instantiated through a control instruction, and the instantiated intermediate transfer node polls the input ports hung on the intermediate transfer node and transfers the transferred user logic to the intermediate transfer node or the output ports.
It is of course conceivable that when the output port comprises at least two incoming interfaces, the output port also needs to poll the data of the input port or the intermediate transmission node mounted thereon to ensure that the data transfer does not interfere with each other.
In an embodiment of the present application, the input port supports setting of a bit width of the input port.
By adopting the scheme, the bit widths of different input ports can be set, and the applicability of the system is improved.
In an embodiment of the present application, the apparatus further includes a PCIE interface connected in series to the output port and configured to implement interaction between data and the terminal.
In an embodiment of the present application, the input port is a SCEMI interface for implementing user logical access.
It is conceivable that the data transmission system in the present application belongs to a bidirectional data system, and the work flow thereof is roughly as follows:
the interface sends data:
1. after the SCEMI interface responds to a data sending request of a user, a complete data packet sent by the user request is stored in the FIFO, and the integrity of data is ensured.
2. And after the input port detects that the data is stored in the FIFO, enabling a sending request signal, and applying for sending the data to the intermediate transmission node.
3. The intermediate transmission node polls the input port hung on the intermediate transmission node or the previous intermediate transmission node, enables a transmission request signal of the next level after detecting a transmission request of the previous level, enables a transmission completion signal after complete data is transmitted to the next level, and completes the transmission of feedback data of the next level.
4. And finally, the output port sends the data acquired by the output port to the computer terminal by using the bus. Wherein the data is composed of an ID of a corresponding input port and user logic transmitted through the port.
The interface receives data:
1. the computer terminal analyzes the ID of the input port and establishes a data transmission channel which is the same as the incoming path according to the last intermediate transmission node corresponding to the ID or the incoming interface of the input port.
2. After the transmission channel is established, data is firstly stored in the FIFO, the FIFO is changed into a non-empty state, and the SCEMI interface extracts the data from the FIFO and sends the data to the user logic after detecting that the FIFO is not in the empty state.
After the sections are adopted, the intermediate transmission nodes for establishing the channel can be added or deleted according to the needs, and additional scripts are not needed, so that the expansion difficulty is greatly simplified, and the resource consumption is reduced.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (10)

1. A method for generating a data transmission system, comprising:
acquiring the number of input ports and output ports, wherein the number of the output ports is smaller than that of the input ports;
calculating at least one layer of intermediate transmission nodes connected between the input port and the output port according to the number of the input port and the output port and the number of access ports of the intermediate transmission nodes, wherein when the intermediate transmission nodes are multi-layer, the number of the intermediate transmission nodes contained in each layer in the direction from the input port to the output port is decreased progressively;
instantiating all the input ports, the intermediate transmission nodes and the output ports and conducting the input ports, the intermediate transmission nodes and the output ports to form the data transmission system.
2. The method of claim 1, wherein the hierarchy of intermediate transmission nodes and the number of layers are calculated by:
step 1, generating root nodes with the same number in the intermediate transmission nodes according to the number of the input ports, and continuing the next step by taking the number of the root nodes as the number of the current nodes;
and 2, the number of the current nodes is added up with the number of the access ports of the intermediate transmission nodes, the integer number of the obtained result is used as the number of the next-level nodes of the root node, the obtained number of the next-level nodes is used as the number of the current nodes, the step 2 is repeated until the obtained number of the next-level nodes is equal to the number of the output ports, and the next node at the moment is used as the tail end node of the intermediate transmission node.
3. The generation method of the data transmission system according to claim 2, wherein a first cache module is provided between a root node of the intermediate transmission node and the input port when a transmission frequency of data transmitted by the root node is not consistent with that of data transmitted by the input port; and/or
When the transmission frequencies of the data transmitted between the intermediate transmission nodes are not consistent, a second cache module is arranged between the two intermediate transmission nodes; and/or
And when the transmission frequencies of the data transmitted between the end node and the output port are not consistent, a third cache module is arranged between the end node and the output port.
4. The method of claim 3, wherein the buffer module is a FIFO memory.
5. The method of generating a data transmission system according to claim 1, wherein the number of the output ports is 1.
6. The generation method of the data transmission system according to claim 1, wherein the transmission frequency of the i +1 th layer intermediate transmission node is set to be n times the transmission frequency of the i layer intermediate transmission node, where n is the number of ports of the intermediate transmission node, and when i takes the minimum value within its range, the i layer intermediate transmission node is a root node.
7. A data transmission system comprising input ports and output ports, and a control module, characterized in that the data transmission system is dynamically generated by the control module according to the generation method of the data transmission system according to any one of claims 1 to 5 using the number of the input ports and the output ports.
8. The data transmission system of claim 7, wherein the input port supports setting a bit width of the input port.
9. The data transmission system of claim 7, further comprising a PCIE interface serially connected to the output port for implementing data interaction with the terminal.
10. The data transmission system of claim 7, wherein the input port is a SCEMI interface for enabling user logical access.
CN202011511259.4A 2020-12-18 Method for generating data transmission system and data transmission system Active CN112434483B (en)

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Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1401081A (en) * 2000-10-19 2003-03-05 因特拉克迪克控股有限责任公司 Scalable apparatue and method for increasing throughput in multiple level minimum logic networks using a plurality o control lines
CN1818912A (en) * 2005-02-11 2006-08-16 思尔芯(上海)信息科技有限公司 Scalable reconfigurable prototyping system and method
US7230917B1 (en) * 2001-02-22 2007-06-12 Cisco Technology, Inc. Apparatus and technique for conveying per-channel flow control information to a forwarding engine of an intermediate network node
US20080008204A1 (en) * 2006-07-10 2008-01-10 Nec Corporation Load balanced type switching apparatus and load balanced type switching method
US20080124077A1 (en) * 2006-11-27 2008-05-29 Ching-Fong Su Optical burst transport using an electro-optic switch
CN101383712A (en) * 2008-10-16 2009-03-11 电子科技大学 Routing node microstructure for on-chip network
CN101663829A (en) * 2006-09-29 2010-03-03 联发科技股份有限公司 Architecture for joint detection hardware accelerator
CN102096741A (en) * 2011-02-21 2011-06-15 华北电力大学 Thermodynamic system dynamic model establishing method
CN102457285A (en) * 2010-10-27 2012-05-16 国际商业机器公司 Calibration of multiple parallel data communications lines for high skew conditions
CN103107943A (en) * 2013-02-22 2013-05-15 中国人民解放军国防科学技术大学 Self-adaption routing method for no-cache optical switching network
CN103548303A (en) * 2011-05-18 2014-01-29 马维尔国际贸易有限公司 Network traffic scheduler and associated method, computer program and computer program product
CN106664257A (en) * 2014-07-22 2017-05-10 阿尔卡特朗讯公司 Signaling for transmission of coherent data flow within packet-switched network
CN108268940A (en) * 2017-01-04 2018-07-10 意法半导体股份有限公司 For creating the tool of reconfigurable interconnection frame
EP3346426A1 (en) * 2017-01-04 2018-07-11 STMicroelectronics Srl Reconfigurable interconnect, corresponding system and method
CN108306652A (en) * 2017-04-11 2018-07-20 华南理工大学 A kind of low complex degree polarization code CA-SCL decoders
CN109783954A (en) * 2019-01-23 2019-05-21 北京轩宇信息技术有限公司 A kind of IES joint FPGA hardware emulation acceleration system
CN110163263A (en) * 2019-04-30 2019-08-23 首钢京唐钢铁联合有限责任公司 Fault identification method and device
CN110187865A (en) * 2019-05-15 2019-08-30 中科亿海微电子科技(苏州)有限公司 Full flowing water high-throughput accumulator and its data processing method
CN110290074A (en) * 2019-07-01 2019-09-27 西安电子科技大学 The Crossbar crosspoint design method interconnected between FPGA piece
CN112068467A (en) * 2020-08-24 2020-12-11 国微集团(深圳)有限公司 Data transmission system and data storage system

Patent Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1401081A (en) * 2000-10-19 2003-03-05 因特拉克迪克控股有限责任公司 Scalable apparatue and method for increasing throughput in multiple level minimum logic networks using a plurality o control lines
US7230917B1 (en) * 2001-02-22 2007-06-12 Cisco Technology, Inc. Apparatus and technique for conveying per-channel flow control information to a forwarding engine of an intermediate network node
CN1818912A (en) * 2005-02-11 2006-08-16 思尔芯(上海)信息科技有限公司 Scalable reconfigurable prototyping system and method
US20080008204A1 (en) * 2006-07-10 2008-01-10 Nec Corporation Load balanced type switching apparatus and load balanced type switching method
CN101663829A (en) * 2006-09-29 2010-03-03 联发科技股份有限公司 Architecture for joint detection hardware accelerator
US20080124077A1 (en) * 2006-11-27 2008-05-29 Ching-Fong Su Optical burst transport using an electro-optic switch
CN101383712A (en) * 2008-10-16 2009-03-11 电子科技大学 Routing node microstructure for on-chip network
CN102457285A (en) * 2010-10-27 2012-05-16 国际商业机器公司 Calibration of multiple parallel data communications lines for high skew conditions
CN102096741A (en) * 2011-02-21 2011-06-15 华北电力大学 Thermodynamic system dynamic model establishing method
CN103548303A (en) * 2011-05-18 2014-01-29 马维尔国际贸易有限公司 Network traffic scheduler and associated method, computer program and computer program product
CN103107943A (en) * 2013-02-22 2013-05-15 中国人民解放军国防科学技术大学 Self-adaption routing method for no-cache optical switching network
CN106664257A (en) * 2014-07-22 2017-05-10 阿尔卡特朗讯公司 Signaling for transmission of coherent data flow within packet-switched network
CN108268940A (en) * 2017-01-04 2018-07-10 意法半导体股份有限公司 For creating the tool of reconfigurable interconnection frame
EP3346426A1 (en) * 2017-01-04 2018-07-11 STMicroelectronics Srl Reconfigurable interconnect, corresponding system and method
CN108306652A (en) * 2017-04-11 2018-07-20 华南理工大学 A kind of low complex degree polarization code CA-SCL decoders
CN109783954A (en) * 2019-01-23 2019-05-21 北京轩宇信息技术有限公司 A kind of IES joint FPGA hardware emulation acceleration system
CN110163263A (en) * 2019-04-30 2019-08-23 首钢京唐钢铁联合有限责任公司 Fault identification method and device
CN110187865A (en) * 2019-05-15 2019-08-30 中科亿海微电子科技(苏州)有限公司 Full flowing water high-throughput accumulator and its data processing method
CN110290074A (en) * 2019-07-01 2019-09-27 西安电子科技大学 The Crossbar crosspoint design method interconnected between FPGA piece
CN112068467A (en) * 2020-08-24 2020-12-11 国微集团(深圳)有限公司 Data transmission system and data storage system

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