CN112421977A - Independent capacitor voltage control method of three-level converter - Google Patents
Independent capacitor voltage control method of three-level converter Download PDFInfo
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- CN112421977A CN112421977A CN202011061703.7A CN202011061703A CN112421977A CN 112421977 A CN112421977 A CN 112421977A CN 202011061703 A CN202011061703 A CN 202011061703A CN 112421977 A CN112421977 A CN 112421977A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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Abstract
The invention relates to an independent capacitor voltage control method of a three-level converter. The independent capacitor voltage control method of the three-level converter comprises the following steps of S1, collecting output voltage of the three-phase three-level converter and upper and lower capacitor voltage of a direct current side, and determining an upper and lower capacitor voltage control mode of the three-level converter according to the positive and negative relation of the output voltage; step S2, determining the corresponding positive and negative current offsets in the upper and lower capacitor voltage control modes; step S3, controlling the neutral point voltage balance according to the positive and negative current offset to stabilize the DC side voltage; in step S1, determining an upper and lower capacitance-voltage control mode of the three-level converter according to the positive-negative relationship of the output voltage; according to the independent capacitor voltage control method of the three-level converter, the upper capacitor voltage and the lower capacitor voltage on the direct current side are independently controlled, so that the control precision is improved while the midpoint voltage is controlled to keep balance, and the midpoint voltage is more stable on the direct current side.
Description
Technical Field
The invention belongs to the technical field of capacitor voltage control of a three-level converter, and particularly relates to an independent capacitor voltage control method of the three-level converter.
Background
With the development of power electronic technology, three-level converters are receiving wide attention, especially in high-capacity and high-voltage occasions. Compared with the traditional two-level converter, the three-level converter has the advantages of lower total harmonic distortion rate, lower device voltage stress and higher energy conversion efficiency.
As a power electronic device which is very common at present, a three-phase three-level converter has higher and higher control requirements. At present, the main methods for researching the system control of the three-phase converter adopt Proportional Integral (PI) control, PR control, repetitive control or dead-beat control, etc. For direct current input signals, PI can achieve no-static-error tracking, and the method has the advantages of being simple in control structure, fast in dynamic response, good in robustness and the like, and is widely applied to the field of electrical engineering. Because the open-loop system of the three-phase converter cannot ensure stable output of voltage and high waveform quality, a double-loop control strategy is usually adopted to improve the system performance. At present, the most widely used dual-loop control method mainly includes a voltage outer loop and an inductive current inner loop, and in order to improve the control performance, researchers have made a lot of researches on improving the inductive current inner loop, but the improvement method related to the voltage outer loop is rarely adopted.
Disclosure of Invention
The invention aims to solve the problems and provide an independent capacitor voltage control method of a three-level converter, which has a simple structure and is reasonably designed.
The invention realizes the purpose through the following technical scheme:
a method for controlling independent capacitor voltage of a three-level converter comprises the following steps,
step S1, collecting output voltage of a three-phase three-level converter and upper and lower capacitor voltage at a direct current side, and determining an upper and lower capacitor voltage control mode of the three-level converter according to the positive and negative relation of the output voltage;
step S2, determining the corresponding positive and negative current offsets in the upper and lower capacitor voltage control modes;
and step S3, controlling the midpoint voltage balance according to the positive and negative current offsets so as to stabilize the direct current side voltage.
As a further optimized solution of the present invention, in step S1, the determining the upper and lower capacitance-voltage control modes of the three-level converter according to the positive and negative relationship of the output voltage specifically includes: when the output voltage is a positive voltage, an upper capacitor voltage control mode is adopted, and when the output voltage is a negative voltage, a lower capacitor voltage control mode is adopted.
As a further optimized solution of the present invention, in step S2, the positive and negative current offsets corresponding to the upper and lower capacitor voltage control modes are determined, specifically: and respectively inputting the difference calculation results of the collected upper capacitor voltage and the collected lower capacitor voltage with a preset upper capacitor voltage reference value and a preset lower capacitor voltage reference value into a PI (proportional integral) regulator, and then outputting the positive and negative current offsets.
As a further preferable embodiment of the present invention, the step S3 of controlling the midpoint voltage balance according to the positive and negative current offsets to stabilize the dc side voltage further includes:
adding corresponding output positive and negative current offsets to the phase current, inputting current inner loop control to obtain corresponding voltage increment, adding the voltage increment and the phase voltage to obtain modulation voltage, comparing the modulation voltage with a carrier, determining a switching sequence of a switching tube, controlling neutral point voltage balance after executing the switching sequence of the switching tube, and stabilizing the voltage at the direct current side.
As a further optimization scheme of the present invention, the adding of the corresponding output positive and negative current offsets to the phase currents further includes a positive and negative current offset determination process in an upper and lower capacitor voltage control mode, specifically:
in the upper capacitor voltage control state, if the upper capacitor voltage is greater than the upper capacitor voltage reference value, adding a negative current offset; if the upper capacitor voltage is smaller than the set upper capacitor voltage reference value, adding a positive current offset;
under the control state of the lower capacitor voltage, if the lower capacitor voltage is greater than the lower capacitor voltage reference value, adding a positive current offset; if the lower capacitor voltage is less than the set lower capacitor voltage reference value, a negative current offset is added.
The invention has the beneficial effects that: compared with the traditional voltage outer ring inductance current inner ring double PI control method, the control method still adopts a PI regulator on the outer ring but uses the direct current side upper (lower) capacitance voltage as the control quantity, the two controls are mutually independent and do not influence each other, and meanwhile, a DBC regulator can be adopted on the inner ring for improving the response speed;
the invention changes the traditional DC side voltage control into independent DC side upper and lower capacitor voltage control, thereby improving the control performance of the system. Meanwhile, the purpose of controlling the neutral point voltage balance and stabilizing the direct current side voltage is achieved by adding a specific current offset on the phase current.
Drawings
FIG. 1 is a flow chart of an independent capacitor voltage control method of a three-level converter according to the present invention;
FIG. 2 is a main circuit diagram of a midpoint clamping type three-level converter in the prior art;
fig. 3 is a simple control block diagram of the three-level converter system of the present invention.
Detailed Description
The present application will now be described in further detail with reference to the drawings, it should be noted that the following detailed description is given for illustrative purposes only and is not to be construed as limiting the scope of the present application, as those skilled in the art will be able to make numerous insubstantial modifications and adaptations to the present application based on the above disclosure.
Example 1
As shown in fig. 1-3, a method for controlling independent capacitor voltage of a three-level converter includes a step S1, collecting output voltage of a three-phase three-level converter, and upper and lower capacitor voltages at a dc side, so as to determine an upper and lower capacitor voltage control mode of the three-level converter according to a positive-negative relationship of the output voltage; in this step, the method for determining the upper and lower capacitor voltage control modes of the three-level converter according to the positive and negative relationship of the output voltage specifically includes: when the output voltage is a positive voltage, an upper capacitor voltage control mode is adopted, and when the output voltage is a negative voltage, a lower capacitor voltage control mode is adopted;
step S2, determining the corresponding positive and negative current offsets in the upper and lower capacitor voltage control modes; in this step, the corresponding positive and negative current offsets are determined in the upper and lower capacitor voltage control modes, specifically: respectively inputting the difference calculation results of the collected upper capacitor voltage and the collected lower capacitor voltage with a preset upper capacitor voltage reference value and a preset lower capacitor voltage reference value into a PI (proportional integral) regulator, and then outputting positive and negative current offsets;
step S3, controlling the neutral point voltage balance according to the positive and negative current offset to stabilize the DC side voltage; in this step, the method for controlling the midpoint voltage balance according to the positive and negative current offsets to stabilize the dc side voltage further includes:
adding corresponding output positive and negative current offsets to the phase current, inputting current inner loop control to obtain corresponding voltage increment, adding the voltage increment and the phase voltage to obtain modulation voltage, comparing the modulation voltage with a carrier, determining a switching sequence of a switching tube, controlling neutral point voltage balance after executing the switching sequence of the switching tube, and stabilizing the voltage at the direct current side.
The method comprises the steps of adding corresponding output positive and negative current offsets to phase currents, and determining the positive and negative current offsets in an upper and lower capacitor voltage control mode, wherein the steps specifically comprise:
in the upper capacitor voltage control state, if the upper capacitor voltage is greater than the upper capacitor voltage reference value, adding a negative current offset; if the upper capacitor voltage is smaller than the set upper capacitor voltage reference value, adding a positive current offset;
under the control state of the lower capacitor voltage, if the lower capacitor voltage is greater than the lower capacitor voltage reference value, adding a positive current offset; if the lower capacitor voltage is smaller than the set lower capacitor voltage reference value, adding a negative current offset;
specifically, in the present embodiment, it should be noted that, in step S1, the upper capacitor voltage u on the dc side of the three-level converter in fig. 2 may be collected by a voltage sensorC1Lower capacitor voltage uC2Three-phase output phase voltage ua、ubAnd uc(ii) a Three-phase output current i of the three-level converter in fig. 2 is sensed by a current sensora、ibAnd ic。
Regarding the influence of the phase current on the capacitor voltage, the corresponding capacitor voltage control basis is obtained as follows:
defining the phase current flowing from the converter as a positive direction, the influence of the phase current on the capacitor voltage can be divided into the following two cases:
(1) when the voltage is positive, only the influence of the phase current on the upper capacitor voltage is considered: if the phase current is positive, the upper capacitor is charged, and the voltage of the upper capacitor rises; if the phase current is negative, the upper capacitor discharges, and the voltage of the upper capacitor is reduced;
(2) when the voltage is negative, only the influence of the phase current on the lower capacitor voltage is considered: if the phase current is positive, the lower capacitor discharges, and the voltage of the lower capacitor decreases; if the phase current is negative, the lower capacitor charges, and the lower capacitor voltage will rise.
In order to keep the midpoint voltage balanced, the dc-side upper and lower capacitor voltages need to be adjusted. From the above analysis, it can be seen that to change the dc-side upper and lower capacitor voltages, a specific current offset can be superimposed on the phase current. In correspondence with the influence of the phase current on the capacitor voltage, the capacitor voltage control is also divided into two cases:
(1) when the upper capacitor voltage control is adopted, if the sampled upper capacitor voltage is greater than the set upper capacitor voltage reference value, a negative current offset is added, so that the upper capacitor voltage can be reduced; if the sampled upper capacitor voltage is smaller than the set upper capacitor voltage reference value, adding a positive current offset to enable the upper capacitor voltage to rise;
(2) when the lower capacitor voltage control is adopted, if the sampled lower capacitor voltage is greater than the set lower capacitor voltage reference value, a positive current offset is added, so that the lower capacitor voltage can be reduced; if the sampled lower capacitor voltage is less than the set lower capacitor voltage reference value, a negative current offset is added to raise the upper capacitor voltage.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention.
Claims (5)
1. A method for controlling independent capacitor voltage of a three-level converter is characterized by comprising the following steps,
step S1, collecting output voltage of a three-phase three-level converter and upper and lower capacitor voltage at a direct current side, and determining an upper and lower capacitor voltage control mode of the three-level converter according to the positive and negative relation of the output voltage;
step S2, determining the corresponding positive and negative current offsets in the upper and lower capacitor voltage control modes;
and step S3, controlling the midpoint voltage balance according to the positive and negative current offsets so as to stabilize the direct current side voltage.
2. The independent capacitor voltage control method of a three-level converter according to claim 1, wherein: in step S1, determining the upper and lower capacitance-to-voltage control modes of the three-level converter according to the positive and negative relationship of the output voltage, specifically including: when the output voltage is a positive voltage, an upper capacitor voltage control mode is adopted, and when the output voltage is a negative voltage, a lower capacitor voltage control mode is adopted.
3. The independent capacitor voltage control method of the three-level converter according to claim 2, wherein: in step S2, the positive and negative current offsets corresponding to the upper and lower capacitor voltage control modes are determined, specifically: and respectively inputting the difference calculation results of the collected upper capacitor voltage and the collected lower capacitor voltage with a preset upper capacitor voltage reference value and a preset lower capacitor voltage reference value into a PI (proportional integral) regulator, and then outputting the positive and negative current offsets.
4. The independent capacitor voltage control method of a three-level converter according to claim 3, wherein: in step S3, the method further includes controlling the midpoint voltage balance according to the positive and negative current offsets to stabilize the dc side voltage, and further includes:
adding corresponding output positive and negative current offsets to the phase current, inputting current inner loop control to obtain corresponding voltage increment, adding the voltage increment and the phase voltage to obtain modulation voltage, comparing the modulation voltage with a carrier, determining a switching sequence of a switching tube, controlling neutral point voltage balance after executing the switching sequence of the switching tube, and stabilizing the voltage at the direct current side.
5. The independent capacitor voltage control method of the three-level converter according to claim 4, wherein: the method comprises the steps of adding corresponding output positive and negative current offsets to phase currents, and determining the positive and negative current offsets in an upper and lower capacitor voltage control mode, wherein the steps specifically comprise:
in the upper capacitor voltage control state, if the upper capacitor voltage is greater than the upper capacitor voltage reference value, adding a negative current offset; if the upper capacitor voltage is smaller than the set upper capacitor voltage reference value, adding a positive current offset;
under the control state of the lower capacitor voltage, if the lower capacitor voltage is greater than the lower capacitor voltage reference value, adding a positive current offset; if the lower capacitor voltage is less than the set lower capacitor voltage reference value, a negative current offset is added.
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| CN108667333A (en) * | 2018-04-04 | 2018-10-16 | 广东科学技术职业学院 | A kind of bidirectional converter system |
| US20190312521A1 (en) * | 2018-04-05 | 2019-10-10 | Nanyang Technological University | Dual voltage and current loop linearization control and voltage balancing control for solid state transformer |
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2020
- 2020-09-30 CN CN202011061703.7A patent/CN112421977A/en active Pending
Patent Citations (5)
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|---|---|---|---|---|
| CN103607131A (en) * | 2013-12-03 | 2014-02-26 | 上海理工大学 | Neutral point potential balancing control system and method of three-level inverter |
| CN104917416A (en) * | 2015-07-06 | 2015-09-16 | 中国矿业大学 | Neutral point potential balance control method of diode clamping type three-level inverter |
| CN107070278A (en) * | 2017-06-26 | 2017-08-18 | 合肥工业大学 | A kind of discontinuous pulse duration modulation method of three-level current transformer neutral-point potential balance |
| CN108667333A (en) * | 2018-04-04 | 2018-10-16 | 广东科学技术职业学院 | A kind of bidirectional converter system |
| US20190312521A1 (en) * | 2018-04-05 | 2019-10-10 | Nanyang Technological University | Dual voltage and current loop linearization control and voltage balancing control for solid state transformer |
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