CN112420823A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112420823A
CN112420823A CN202010289279.5A CN202010289279A CN112420823A CN 112420823 A CN112420823 A CN 112420823A CN 202010289279 A CN202010289279 A CN 202010289279A CN 112420823 A CN112420823 A CN 112420823A
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layer
gate
substrate
dimensional material
region
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徐志安
杨世海
章勋明
曹敏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开提供一种半导体装置，其包含设置于栅极电极与基底之间的二维材料层。半导体装置包括铁电介电层、栅极电极以及源极/漏极区。铁电介电层设置于半导体基底上并与其接触，铁电介电层包括二维材料；栅极电极设置于铁电介电层上；源极/漏极区设置于栅极电极的两侧。

Description

半导体装置
技术领域
本公开实施例涉及半导体装置，尤其涉及具有二维材料层的半导体装置。
背景技术
半导体装置应用于各种电子产品，例如：个人电脑、行动电话、数字相机以及其他电子设备。半导体装置通常由以下方式制造：依序在半导体基底上沉积绝缘或介电层、导电层、半导体材料层，并使用光刻技术图案化各种材料层，在其上形成电路组件和元件。
通过不断地缩减最小部件尺寸，半导体产业持续改善各种电子元件(例如：晶体管、二极管、电阻器、电容器等等)的积集密度，使更多元件得以整合至特定面积内。然而，随着最小部件尺寸的缩减，也出现了应解决的其他问题。
发明内容
本公开实施例的目的在于提供一种半导体装置，以解决上述至少一个问题。
本公开实施例提供一种半导体装置，包括铁电介电层、栅极电极以及多个源极/漏极区。铁电介电层设置于半导体基底上并与其接触，铁电介电层包括二维材料；栅极电极设置于铁电介电层上；多个源极/漏极区设置于栅极电极的两侧。
本公开实施例提供一种半导体装置的形成方法，包括：形成二维材料层于基底上，二维材料层包括铁电材料；形成虚设栅极电极于二维材料层上；蚀刻虚设栅极电极，以形成露出二维材料层的第一开口；以及形成一金属栅极电极于开口中。
本公开实施例提供一种半导体装置，包括：栅极堆叠，包括：第一界面层，位于基底上；二维材料层，位于第一界面层上；第二界面层，位于二维材料层上；及栅极电极，位于第二界面层上；以及源极/漏极区，邻近于栅极堆叠。
附图说明
由以下的详细叙述配合所附附图，可最好地理解本公开实施例。应注意的是，依据在业界的标准做法，各种特征并未按照比例绘制。事实上，可任意地放大或缩小各种元件的尺寸，以清楚地表现出本公开实施例的特征。
图1、图2、图3A、图3B、图4-图9、图10A、图10B、图11A、图11B、图12及图13是根据一些实施例，示出制造金属氧化物半导体场效晶体管的多个中间阶段的剖面示意图。
图14A、图14B、图15A及图15B是根据一些实施例，示出鳍式场效晶体管的剖面示意图。
附图标记如下：
50:基底
50N,50P:区域
51:分隔符号
52:隔离区
53a:第一界面层
53b:第二界面层
54:二维材料层
56:虚设栅极层
58:第一掩膜层
60:第二掩膜层
66:虚设栅极
68:第一掩膜
70:第二掩膜
72:栅极密封间隔物
74:栅极间隔物
76:外延源极/漏极区
77:接触蚀刻停止层
78:第一层间电介质
80:凹槽
82:栅极电极
82A:衬层
82B:功函数调整层
82C:填充材料
83:区域
84:栅极掩膜
86:第二层间电介质
88:栅极接触件
90:源极/漏极接触件
92:鳍片
94:通道区
具体实施方式
以下公开提供了许多的实施例或范例，用于实施本公开实施例的不同元件。各元件和其配置的具体范例描述如下，以简化本公开实施例的说明。当然，这些仅仅是范例，并非用以限定本公开实施例。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本公开实施例可能在各种范例中重复参考数值以及/或字母。如此重复是为了简明和清楚的目的，而非用以表示所讨论的不同实施例及/或配置之间的关系。
再者，其中可能用到与空间相对用词，例如“在……之下”、“下方”、“较低的”、“上方”、“较高的”等类似用词，是为了便于描述附图中一个(些)部件或特征与另一个(些)部件或特征之间的关系。空间相对用词用以包括使用中或操作中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，其中所使用的空间相对形容词也将依转向后的方位来解释。
本公开的各种实施例提供改善的栅极介电层及其形成方法，其用于半导体装置。栅极介电层可由具有负电容的材料形成，例如铁电二维(2D)材料。可将栅极介电层形成于具有正电容的基底上，且可选择栅极介电层的厚度，使栅极介电层的负电容匹配基底的正电容。包含前述栅极介电层的半导体装置可具有增加的开关电流比(ION/IOFF)、增加的栅极电压(VG)以及改善的整体性能。
此中讨论的实施例是在使用栅极后制工艺(gate-last process)所形成的平面金属氧化物半导体场效晶体管的背景下讨论。在其他实施例中，可以使用栅极先制工艺(gate-first process)。一些实施例也考虑了用于鳍式场效晶体管中的多个面向。
图1至图9是根据一些实施例，示出制造平面金属氧化物半导体场效晶体管的多个中间阶段的剖面示意图。图1示出基底50。基底50可为半导体基底，例如块体半导体(bulksemiconductor)、绝缘体上覆半导体(semiconductor-on-insulator,SOI)基底或其他类似的基底，其可为掺杂的(例如以p型或n型掺质掺杂)或未掺杂的。基底50可为晶片，例如硅晶片。一般而言，绝缘体上覆半导体基底是形成于绝缘层上的半导体材料层。举例而言，此绝缘层可为埋入式氧化物(buried oxide,BOX)层、氧化硅层或其他类似的绝缘层。将前述绝缘层提供于基底上，此基底通常为硅基底或玻璃基底。也可使用其他基底，例如多层(multi-layered)或梯度(gradient)基底。一些实施例中，基底50的半导体材料可包含：硅；锗；化合物半导体，包含碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟；合金半导体，包含SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或前述的组合。
基底50具有区域50N和区域50P。区域50N可用于形成n型装置，如n型金属氧化物半导体(NMOS)晶体管，例如n型金属氧化物半导体场效晶体管。区域50P可用于形成p型装置，如p型金属氧化物半导体(PMOS)晶体管，例如p型金属氧化物半导体场效晶体管。区域50N可与区域50P物理上分开(如分隔符号51所示)，且可在区域50N与区域50P之间设置任何数量的装置部件(例如：其他主动装置、掺杂区、隔离结构或其他类似部件)。
图2示出在基底50中形成隔离区52，例如浅沟槽隔离(STI)区。可通过在基底50中形成凹槽(未单独示出)来形成隔离区52。可通过适当的蚀刻工艺来形成凹槽，例如：反应性离子蚀刻(RIE)、中性粒子束蚀刻(NBE)、其他类似工艺、前述的组合。此蚀刻工艺可为各向异性的。
然后将绝缘材料形成于基底上并填充凹槽。绝缘材料可为氧化物(例如氧化硅)、氮化物、其他类似材料或前述的组合，且其形成方法可为高密度等离子体化学气相沉积(HDP-CVD)、流动式化学气相沉积(FCVD)(例如在远距等离子体(remote plasma)系统进行化学气相沉积为主的材料沉积且进行后续的固化，使其转换为另一种材料，例如氧化物)、其他类似方法或前述的组合。也可使用由任何适当的工艺所形成的其他绝缘材料。在示出的实施例中，绝缘材料为流动式化学气相沉积工艺所形成的氧化硅。形成绝缘材料后即可执行退火工艺。在一实施例中，形成绝缘材料而使得多余的绝缘材料覆盖基底50的顶表面。可利用单层或多层的绝缘材料。举例而言，在一些实施例中，衬层(未单独示出)可先沿着基底50的表面形成并填充凹槽。此后，可在衬层上形成填充材料，例如以上讨论的材料。
对绝缘材料实施移除工艺，以移除基底50上的多余绝缘材料。一些实施例中，可利用平坦化工艺(例如化学机械研磨)、回蚀刻(etch-back)工艺、前述的组合或其他类似工艺。在完成前述平坦化工艺后，其露出基底50，使基底50与隔离区52的顶表面齐平。
虽然未具体示出，但可在基底50中形成合适的井区。举例而言，可在p型装置(例如p型金属氧化物半导体场效晶体管)将形成的区域中(例如，在区域50P中)的基底50中形成n型井区。可通过在基底50上方形成光刻胶来形成n型井区于基底50中。将光刻胶图案化以露出基底50中将要形成n型井区的区域。可使用旋涂技术(spin-on technique)来形成光刻胶，并可使用适当的光刻技术将其图案化。将光刻胶图案化后，即运用光刻胶作为掩膜来执行n型杂质注入，以防止将n型杂质注入至预期的注入区域之外的基底50中。n型杂质可为磷、砷、锑或类似杂质，其注入至基底50中的浓度小于或等于约1018atoms/cm3，例如从约1016atoms/cm3至约1018atoms/cm3。在注入后，通过适当的工艺移除光刻胶，如灰化(ashing)或其他类似工艺。此外，可在注入之后执行退火，以活化注入的杂质。由此可在基底50中形成n型井区。
p型井区也可在将要形成n型装置(例如p型金属氧化物半导体场效晶体管)的区域中(例如在区域50N中)的基底50中形成。可使用与上述用于形成n型井区的相同或相似的工艺来形成p型井区。用于形成p型井区的p型杂质可为硼、氟化硼(BF2)、铟(In)或其他类似杂质，且注入浓度可小于或等于约1018atoms/cm3，例如从约1016atoms/cm3至约1018atoms/cm3。
图3A示出在基底50和隔离区52上方形成的二维材料层54。二维材料层54可由负电容材料形成，例如铁电材料。举例而言，可用于二维材料层54的铁电材料包括：In2Se3、CuInP2S6(CIPS)、SnTe、GeS、GeSe、SnS、SnSe、前述的组合或前述的多层或其他类似材料。可通过适当的技术来沉积二维材料层54，例如：化学气相沉积(CVD)、等离子体辅助化学气相沉积(PECVD)、金属有机化学气相沉积(MOCVD)、原子层沉积(ALD)、等离子体辅助原子层沉积(PEALD)或其他类似技术。如图3A所示，二维材料层54可直接沉积于基底50及隔离区52上，在其之间不设置材料，例如界面层。
二维材料层54的电容取决于二维材料层54的层数，且因此取决于二维材料层54的厚度。举例而言，二维材料层54的沉积层数增加，可增加二维材料层54的电容大小(magnitude)。二维材料层54的沉积层数可基于以下条件来控制：成长时间、前驱物流率(flowrate)(包括反应物分压)、前驱物量、成长温度、成长压力、特定前驱物的选择、沉积后退火(post-deposition anneal)温度或其他条件。在通过化学气相沉积、金属有机化学气相沉积或类似工艺来沉积二维材料层54的实施例中，二维材料层54可在约700℃至约1100℃的温度下沉积。在通过原子层沉积、等离子体辅助原子层沉积或类似工艺来沉积二维材料层54的实施例中，二维材料层54可在约100℃至约600℃的温度下沉积。可在压力约10Torr至100Torr下沉积二维材料层54。依使用于沉积二维材料层54的前驱物而定，可在约500℃至约1100℃的温度下，对二维材料层54执行5分钟至3小时的沉积后退火。如此，可沉积具有预定负电容值的二维材料层54。
基底50具有正电容CS，而二维材料层54具有负电容CFE。通过沉积特定层数的二维材料层54，将二维材料层54的负电容CFE与基底的正电容CS匹配，导致包含二维材料层54的装置的开/关电流比(ION/IOFF)以及栅极电压(VG)增加。因此，包含二维材料层54的装置具有改善的性能。对于节点小于或等于28nm的先进互补金属氧化物半导体(CMOS)技术，二维材料层54可为1层至6层，且厚度为约1nm至约3nm，例如约2nm。对于节点在28nm以上的较旧的互补金属氧化物半导体技术，二维材料层54可为5至16层，且厚度为约3nm至约8nm，例如约5.5nm。可将二维材料层54的电容匹配至基底50的电容的±50％内。
图3B示出了另一实施例，其中二维材料层54形成于基底50及隔离区52上，第一界面层53a形成于二维材料层与基底50及隔离区52之间，且第二界面层53b形成于二维材料层54上。第一界面层53a及第二界面层53b可由氧化物材料形成，例如氧化硅，且可通过热氧化、化学氧化、原子层沉积或类似工艺来形成。
第一界面层53a及第二界面层53b可由具有正电容的材料形成，且可将其包括以进一步调整装置的电容。如参考图3A所讨论的，二维材料层54的负电容CFE可与基底50的正电容CS匹配。然而，增加或降低二维材料层54的层数可能过度增加或减少二维材料层54的负电容CFE，而无法将二维材料层54的负电容CFE与基底50的正电容CS匹配。前述情况下，可因此包括第一界面层53a及第二界面层53b，以提供电容匹配的微调。
通过选择适当厚度的二维材料层54、第一界面层53a及第二界面层53b，将二维材料层54的负电容CFE与基底的正电容CS及第一界面层53a和第二界面层53b的正电容匹配，进而增加包含二维材料层54及任何第一界面层53a和第二界面层53b的组合的装置对开关电流比(ION/IOFF)和栅极电压(VG)的控制。因此，包含二维材料层54及任何第一界面层53a和第二界面层53b的组合的装置具有改善的性能。二维材料层54的厚度约1nm至约3nm，例如约2nm，或约3nm至约8nm，例如约5.5nm；第一界面层53a的厚度约0.5nm至约3nm，例如约1.75nm；且第二界面层53b的厚度约2nm至约5nm，例如约3.5nm。随后叙述的实施例中的任何一个可包括仅二维材料层54、第一界面层53a及二维材料层54；第二界面层53b及二维材料层54；或第一界面层53a、第二界面层53b及二维材料层54。
图4示出在二维材料层54上方形成的虚设栅极层56、第一掩膜层58以及第二掩膜层60。可在二维材料层54上方沉积虚设栅极层56，然后使用工艺将其平坦化，例如使用化学机械研磨。虚设栅极层56可为导电或非导电材料，且可选自包括非晶硅、多晶硅(polysilicon)、多晶硅锗(poly-SiGe)、金属氮化物、金属硅化物、金属氧化物及金属的群组。虚设栅极层56的沉积可通过物理气相沉积、化学气相沉积、溅镀(sputter)沉积或用于沉积所选材料的已知并运用于本领域中的其他技术。虚设栅极层56可由在隔离区52的蚀刻中具有高蚀刻选择性的其他材料来形成。
在虚设栅极层56上形成第一掩膜层58，且在第一掩膜层58上形成第二掩膜层60。在一实施例中，第一掩膜层58可包括氮化硅，且第二掩膜层60可以包含氧化硅(由前躯物形成，例如四乙基正硅酸盐(TEOS))；然而，第一掩膜层58及第二掩膜层60的其中一个可包括：氮化硅、氧化硅、碳化硅、碳氧化硅、氮氧化硅、其他类似材料或前述的组合。第一掩膜层58和第二掩膜层60可通过以下工艺沉积，例如：化学气相沉积、原子层沉积、其他类似的工艺或前述的组合。
图5至图10B示出制造实施例的装置的各种附加步骤。图5至图10B所示出的部件是在区域50N及区域50P的其中之一。举例而言，图5至图10B所示出的结构可适用区域50N及区域50P两者。区域50N和区域50P的结构差异(若存在)在每个附图相应的说明中描述。
在图5中，可使用适当的光刻和蚀刻技术来图案化第二掩膜层60(见图4)和第一掩膜层58，以形成第一掩膜68和第二掩膜70。然后可将第一掩膜68和第二掩膜70的图案转移至虚设栅极层56，以形成虚设栅极66。在一些实施例中，也可通过适当的蚀刻技术将第一掩膜68和第二掩膜70的图案转移至二维材料层54。虚设栅极66覆盖基底50的个别通道区。第一掩膜68和第二掩膜70的图案可用于将每个虚设栅极66与邻近的虚设栅极66物理分离。
可在形成虚设栅极66、第一掩膜68及第二掩膜70之后执行轻掺杂源极/漏极(LDD)区(未单独示出)的注入。在区域50N和区域50P中形成不同装置类型的实施例中，类似于以上在图2中讨论的注入，可在区域50N上方形成掩膜，例如光刻胶，而暴露区域50P，且可将适当类型(例如p型)的杂质注入至区域50P中的基底50所露出的部分。然后可移除掩膜。随后，可在区域50P上方形成掩膜，例如光刻胶，而暴露区域50N，且可将适当类型的杂质(例如n型)注入至区域50N中的基底50所露出的部分。然后可移除掩膜。n型杂质可为先前讨论的任何n型杂质，且p型杂质可为先前讨论的任何p型杂质。轻掺杂源极/漏极区的杂质浓度可为约1015atoms/cm3至约1019atoms/cm3。可使用退火来修复注入损坏且活化注入的杂质。
在图6中，形成栅极密封间隔物72及栅极间隔物74于虚设栅极66、第一掩膜68、第二掩膜70及/或基底50露出的表面上。可由热氧化或沉积(例如：化学气相沉积、原子层沉积或其他类似的工艺)来形成栅极密封间隔物72。栅极密封间隔物72可由氧化硅、氮化硅、氮氧化硅或其他类似材料来形成。然后在沿着虚设栅极66、第一掩膜68及第二掩膜70的侧壁的栅极密封间隔物72上，形成栅极间隔物74。栅极间隔物74的形成可通过顺应性地沉积绝缘材料于栅极密封间隔物72上。接着可各向异性地蚀刻栅极密封间隔物72及栅极间隔物74，以形成图6所示的结构。栅极间隔物74的绝缘材料可为氧化硅、氮化硅、氮氧化硅、氮化碳硅(silicon carbonitride)、前述的组合或其他类似材料。
应注意的是，以上公开大致上叙述了形成间隔物及轻掺杂源极/漏极区的工艺。可使用其他工艺及顺序。举例而言，可利用较少或额外的间隔物、可利用不同的步骤顺序(例如，可在形成栅极间隔物74之前蚀刻栅极密封间隔物72，产生“I形”的栅极密封间隔物)、可形成及移除多个间隔物及/或其他类似的工艺及顺序。此外，可使用不同的结构及步骤来形成n型及p型装置。举例而言，可在形成栅极密封间隔物72之前形成用于n型装置的轻掺杂源极/漏极区，而可在形成栅极密封间隔物72之后形成用于p型装置的轻掺杂源极/漏极区。
图7中，形成外延源极/漏极区76于基底50中，以在个别通道区中施加应力，从而改善性能。形成外延源极/漏极区76于基底50中，使每个虚设栅极66设置于各个相邻成对的外延源极/漏极区76之间。一些实施例中，使用栅极间隔物74及栅极密封间隔物72将外延源极/漏极区76与虚设栅极66分隔适当的横向距离，使外延源极/漏极区76不会导致随后形成的金属氧化物半导体场效晶体管的栅极短路。
在区域50N(例如n型金属氧化物半导体区)中的外延源极/漏极区76形成可通过掩膜住区域50P(例如p型金属氧化物半导体区)，然后蚀刻区域50N中的基底50的源极/漏极区，以形成凹槽于基底50中。接着在凹槽中外延成长区域50N的外延源极/漏极区76。外延源极/漏极区76可包括任何适当的材料，例如适用于n型金属氧化物半导体场效晶体管的材料。举例而言，若基底50是硅，则区域50N中的外延源极/漏极区76可包括在通道区中施加拉伸应变(tensile strain)的材料，例如硅、碳化硅、磷掺杂的碳化硅、磷化硅或其他类似材料。区域50N中的外延源极/漏极区76可具有从基底50的相应表面隆起的表面，并且可具有刻面。
在区域50P(例如p型金属氧化物半导体区)中的外延源极/漏极区76形成可通过掩膜住区域50N(例如n型金属氧化物半导体区)，然后蚀刻区域50P中的基底50的源极/漏极区，以形成凹槽于基底50中。接着在凹槽中外延成长区域50P的外延源极/漏极区76。外延源极/漏极区76可包括任何适当的材料，例如适用于p型金属氧化物半导体场效晶体管的材料。举例而言，若基底50是硅，则区域50P中的外延源极/漏极区76可包括在通道区中施加压缩应变(compressive strain)的材料，例如硅锗、硼掺杂的硅锗、锗、锗锡或其他类似材料。区域50P中的外延源极/漏极区76可具有从基底50的相应表面隆起的表面，并且可具有刻面。
可用掺杂注入外延源极/漏极区76及/或基底50，以形成源极/漏极区，与先前所讨论的形成轻掺杂源极/漏极区的工艺相似，随后进行退火。外延源极/漏极区76的杂质浓度为约1019atoms/cm3至约1021atoms/cm3。用于源极/漏极区的n型及/或p型杂质可为先前讨论的任何杂质。一些实施例中，可在成长期间原位(in situ)掺杂外延源极/漏极区76。
图8中，沉积第一层间电介质(ILD)于图7所示的结构上。第一层间电介质78可由介电材料形成，且可通过任何合适的方法沉积，例如：化学气相沉积、等离子体辅助化学气相沉积、流动式化学气相沉积或类似的方法。介电材料可包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)或类似的材料。可使用通过任何适当的方法所形成的其他绝缘材料。在一些实施例中，设置接触蚀刻停止层(CESL)77于第一层间电介质78与外延源极/漏极区76、第二掩膜70、栅极密封间隔物72、和栅极间隔物74之间。接触蚀刻停止层77可包括介电材料，例如：氮化硅、氧化硅、氮氧化硅或其他类似材料，其蚀刻速率与其上方的第一层间电介质78的材料的蚀刻速率不同。
图9中，可执行如化学机械研磨的平坦化工艺，使第一层间电介质78的顶表面与虚设栅极66、第一掩膜68或第二掩膜70的顶表面齐平。平坦化工艺可移除虚设栅极66上的第二掩膜70或第二掩膜70及第一掩膜68以及沿着第一掩膜68及第二掩膜70的侧壁的栅极密封间隔物72及栅极间隔物74的一部分。在平坦化工艺后，虚设栅极66、栅极密封间隔物72、栅极间隔物74及第一层间电介质78的顶表面是齐平的。因此，虚设栅极66的顶表面经由第一层间电介质78暴露。一些实施例中，可留下第一掩膜68或第一掩膜68及第二掩膜70，此情况下，平坦化工艺使第一层间电介质78的顶表面与第一掩膜68或第二掩膜70的顶表面齐平。
图10A及图10B中，执行蚀刻工艺将虚设栅极66移除，以形成凹槽80。如图10A所示，在移除虚设栅极66并通过凹槽80露出二维材料层54后，留下二维材料层54。相似地，如图10B所示，在包含第一界面层53a及第二界面层53b的实施例中，在移除虚设栅极66并通过凹槽80露出第二界面层53b后，留下第二界面层53b。在一些实施例中，虚设栅极66是通过各向异性干蚀刻工艺来移除。举例而言，蚀刻工艺可包括干蚀刻工艺，其使用反应气体选择性地蚀刻虚设栅极66，而不蚀刻第一层间电介质78、二维材料层54、第二界面层53b、栅极密封间隔物72或栅极间隔物74。每个凹槽80皆覆盖基底50的相应通道区。每个通道区皆设置在相邻成对的外延源极/漏极区76之间。在移除期间，当蚀刻虚设栅极66时，可使用二维材料层54或第二界面层53b作为蚀刻停止层。
图11A中，形成栅极电极82作为替换栅极。图11B示出了图11A的区域83的详细视图。栅极电极82沉积于二维材料层54上且填充凹槽80。栅极电极82可包括含金属的材料，例如：氮化钛、氧化钛、氮化钽、碳化钽、钴、钌、铝、钨、前述的组合或前述的多层材料。举例而言，虽然图11A示出的是单层栅极电极82，但栅极电极82可包括任何数量的衬层(linerlayer)82A、任何数量的功函数调整层82B及填充材料82C，如图11B所示。在填充凹槽80后，可执行如化学机械研磨的平坦化工艺，以移除栅极电极82的材料的多余部分，此多余部分位于第一层间电介质78的顶表面上。栅极电极82及二维材料层54的材料的剩余部分由此形成金属氧化物半导体场效晶体管的替换栅极。栅极电极82及二维材料层54可统称为“栅极堆叠(gate stack)”。栅极及栅极堆叠可延伸至基底50的通道区上方。
可同时在区域50N及区域50P中形成栅极电极82，使每个区域的栅极电极82由相同材料形成。一些实施例中，每个区域的栅极电极82可由相异的工艺来形成，使栅极电极82可为不同的材料。当使用相异的工艺时，可使用各种掩膜步骤，以掩膜并露出适当的区域。
图12中，沉积第二层间电介质86于第一层间电介质78上。一些实施例中，第二层间电介质86是由流动式化学气相沉积法所形成的可流动膜。在一些实施例中，第二层间电介质86是由介电材料形成，例如：磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、掺硼磷硅酸盐玻璃(BPSG)、未掺杂的硅酸盐玻璃(USG)或类似的材料，且可通过任何合适的方法沉积，例如：化学气相沉积、等离子体辅助化学气相沉积或类似方法。根据一些实施例，在形成第二层间电介质86之前，凹入栅极堆叠(例如栅极电极82)，使凹槽(未单独示出)直接形成于栅极堆叠上并位于栅极密封间隔物72的两部分之间，如图12所示。在凹槽中填充包括一或多层介电材料(例如氮化硅、氮氧化硅或类似材料)的栅极掩膜84，然后进行平坦化工艺，以移除延伸至第一层间电介质78上方的介电材料的多余部分。随后形成的栅极接触件(例如图13所示的栅极接触件88)可穿过栅极掩膜84，以接触凹入的栅极电极82的顶表面。
图13中，根据一些实施例，栅极接触件88穿过第二层间电介质86及栅极掩膜84而形成，且源极/漏极接触件90穿过第二层间电介质86及第一层间电介质78而形成。用于栅极接触件88的开口(未单独示出)是穿过第二层间电介质86及栅极掩膜84来形成，且用于源极/漏极接触件90的开口是穿过第二层间电介质86及第一层间电介质78来形成。可使用适当的光刻及蚀刻技术来形成前述开口。在开口中形成衬层(未单独示出)，例如：扩散阻挡层、粘着层或其他类似的层，以及导电材料(未单独示出)。衬层可包括：钛、氮化钛、钽、氮化钽或其他类似材料。导电材料可为：铜、铜合金、银、金、钨、钴、铝、镍或其他类似材料。可执行如化学机械研磨的平坦化工艺，从第二层间电介质86的表面移除多余的材料。剩余的衬层及导电材料在开口中形成栅极接触件88及源极/漏极接触件90。可执行退火工艺，以形成硅化物于外延源极/漏极区76与源极/漏极接触件90之间的界面处。源极/漏极接触件90物理及电性耦合至外延源极/漏极区76，且栅极接触件88物理及电性耦合至栅极电极82。栅极接触件88及源极/漏极接触件90可由不同的工艺来形成，或者可由相同的工艺来形成。虽然所示的栅极接触件88与源极/漏极接触件90是形成于相同的剖面中，应理解的是，每个栅极接触件88及源极/漏极接触件90可形成于不同的剖面中，如此可避免接触件短路。
形成包括单独二维材料层54的半导体装置或包括二维材料层54、第一界面层53a及第二界面层53b的组合的半导体装置，使基底50、第一界面层53a及第二界面层53b的正电容得以匹配二维材料层54的负电容。致使半导体装置的开关电流比(ION/IOFF)及栅极电压(VG)增加，并改善设备性能。
图14A及图14B示出包含二维材料层54的鳍式场效晶体管(FinFET)，图15A及图15B示出包括二维材料层54、第一界面层53a及第二界面层53b的鳍式场效晶体管。鳍式场效晶体管包括从基底50(例如半导体基底)延伸的鳍片92。隔离区52设置在基底50中，且鳍片92从相邻的隔离区52间突出于其上。虽然将隔离区52叙述/示出为与基底50分离，但文中的用语“基底”可仅指半导体基底或包括隔离区的半导体基底。此外，虽然将鳍片92示出为单个的、与基底50连续的材料，但鳍片92及/或基底50可包括单一材料或多个材料。在本文中，鳍片92是指相邻的隔离区52之间的延伸部分。
二维材料层54或二维材料层54、第一界面层53a及第二界面层53b是沿着鳍片92的侧壁设置并设置于鳍片92的顶表面上，且栅极电极82是设置于二维材料层54或第二界面层53b上。二维材料层54或第一界面层53a覆盖鳍片92的个别通道区94。源极/漏极区76设置于鳍片92相对栅极电极82的两侧。图14A及图15A所示出的剖面是沿着栅极电极82的纵轴，且在一方向上，举例而言，在垂直于鳍式场效晶体管的源极/漏极区76之间的电流方向上。图14B及图15B所示出的剖面垂直于图14A及图15A所示出的剖面，并沿着鳍片92的纵轴，且在一方向上，举例而言，在鳍式场效晶体管的源极/漏极区76之间的电流方向上。
在鳍式场效晶体管中包括单独的二维材料层54或二维材料层54、第一界面层53a及第二界面层53b的组合，使基底50、第一界面层53a及第二界面层53b的正电容得以匹配二维材料层54的负电容。致使半导体装置的开关电流比(ION/IOFF)及栅极电压(VG)增加，并改善设备性能。
根据一实施例，半导体装置包括：铁电介电层，设置于半导体基底上并与其接触，铁电介电层包括二维材料；栅极电极，设置于铁电介电层上；以及多个源极/漏极区，设置于栅极电极的两侧。一实施例中，铁电介电层包括In2Se3、CuInP2S6(CIPS)、SnTe、GeS、GeSe、SnS或SnSe。一实施例中，栅极电极与铁电介电层物理接触。一实施例中，还包括界面层，设置于铁电介电层与栅极电极之间，界面层包括氧化物。一实施例中，界面层的厚度为2nm至5nm。一实施例中，铁电介电层的厚度为1nm至3nm。一实施例中，铁电介电层的厚度为3nm至8nm。一实施例中，还包括鳍片延伸自半导体基底，铁电介电层及栅极电极设置于鳍片上。
根据另一实施例，半导体装置的形成方法包括：形成二维材料层于基底上，二维材料层包括铁电材料；形成虚设栅极电极于二维材料层上；蚀刻虚设栅极电极，以形成露出二维材料层的第一开口；以及形成一金属栅极电极于开口中。一实施例中，二维材料层是使用化学气相沉积或等离子体辅助化学气相沉积来形成。一实施例中，还包括在形成二维材料层之前，形成第一界面层于基底上。一实施例中，还包括在形成虚设栅极电极之前，形成第二界面层于二维材料层上。一实施例中，第一界面层的厚度为0.5nm至3nm且第二界面层的厚度为2nm至5nm。一实施例中，第一界面层及第二界面层是使用热氧化或原子层沉积来形成。
根据另外一实施例，半导体装置包括：栅极堆叠，包括：第一界面层，位于基底上；二维材料层，位于第一界面层上；第二界面层，位于二维材料层上；及栅极电极，位于第二界面层上；以及源极/漏极区，邻近于栅极堆叠。一实施例中，二维材料层包括一铁电材料。一实施例中，二维材料层包括In2Se3、CuInP2S6(CIPS)、SnTe、GeS、GeSe、SnS或SnSe。一实施例中，二维材料层的厚度为1nm至3nm。一实施例中，第一界面层及第二界面层包括氧化物。一实施例中，第一界面层的厚度为0.5nm至3nm且第二界面层的厚度为2nm至5nm。
以上概述数个实施例的特点，以便在本公开所属技术领域中技术人员可更好地了解本公开的各个方面。在本公开所属技术领域中技术人员，应理解其可轻易地利用本公开实为基础，设计或修改其他工艺及结构，以达到和此中介绍的实施例的相同的目的及/或优点。在本公开所属技术领域中技术人员，也应理解此类等效的结构并无背离本公开的精神与范围，且其可于此作各种的改变、取代、和替换而不背离本公开的精神与范围。

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1.一种半导体装置，包括：
一铁电介电层，设置于一半导体基底上并与其接触，该铁电介电层包括一二维材料；
一栅极电极，设置于该铁电介电层上；以及
多个源极/漏极区，设置于该栅极电极的两侧。
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