CN112420786A - Display panel and preparation method thereof - Google Patents
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- CN112420786A CN112420786A CN202011231409.6A CN202011231409A CN112420786A CN 112420786 A CN112420786 A CN 112420786A CN 202011231409 A CN202011231409 A CN 202011231409A CN 112420786 A CN112420786 A CN 112420786A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000009413 insulation Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 8
- 230000008569 process Effects 0.000 abstract description 6
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 14
- 239000004020 conductor Substances 0.000 description 12
- 238000002161 passivation Methods 0.000 description 9
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 7
- 239000000872 buffer Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 229910052733 gallium Inorganic materials 0.000 description 7
- 229910052738 indium Inorganic materials 0.000 description 7
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 7
- 239000011787 zinc oxide Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- 239000004698 Polyethylene Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 229910010272 inorganic material Inorganic materials 0.000 description 2
- 239000011147 inorganic material Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000008093 supporting effect Effects 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses a display panel and a preparation method thereof, wherein the display panel comprises: the display device comprises a substrate, a first active layer, a first functional structure layer, a second active layer, a first electrode layer, a second functional structure layer and a second electrode layer, wherein the first electrode layer is provided with a first electrode wire, and the second electrode layer is provided with a third electrode wire; the third electrode routing penetrates through the second functional structure layer and is respectively connected to the first electrode routing and the source electrode of the second active layer to form a bridging structure. The invention has the technical effects that the two active layers are overlapped without digging deep holes, thereby reducing the process difficulty.
Description
Technical Field
The invention relates to the field of display, in particular to a display panel and a preparation method thereof.
Background
In the field of display panels, the OLED technology has been developed in a large scale in order to form a high-response speed, high-contrast, and high-brightness screen display. However, with the development of wearable devices and wearable display fields and the background that the technology in the battery field has not been significantly broken through at present, people have higher and higher requirements for power consumption of display devices.
The low-temperature polysilicon LTPS technology used for driving TFTs and switching TFTs at present is a mainstream technical trend, and the power consumption is low. However, LTPS has a problem of high leakage current due to its high carrier mobility. Therefore, LTPO (Low Temperature Polycrystalline-Si Oxide) Low Temperature Polycrystalline Oxide technology is produced. The LTPO solution combines the advantages of LTPS and Oxide (such as IGZO indium gallium zinc Oxide), and is high in response speed and low in power consumption.
However, because two active layers are used in LTPO, deep hole process is difficult to perform in deep hole electrical connection, and it is difficult to form a small-sized deep hole, and it is difficult to increase pixel density (PPI).
Disclosure of Invention
The invention aims to solve the technical problems of high difficulty of deep hole lapping process and low pixel density between two active layers in the conventional LTPO display device.
To achieve the above object, the present invention provides a display panel including: a substrate; the first active layer is arranged on the surface of one side of the substrate; the first functional structure layer is arranged on the surface of one side, away from the substrate, of the first active layer; the second active layer is arranged on the surface of one side, away from the substrate, of the first functional structure layer, and the orthographic projection of the second active layer on the substrate is not overlapped with the orthographic projection of the first active layer on the substrate; the first electrode layer is arranged on the surface of one side, away from the substrate, of the first functional structure layer and provided with a first electrode wire, and the first electrode wire penetrates through the first functional structure layer and is connected to the drain electrode of the first active layer; a second functional structure layer covering the first electrode layer and the second active layer; the second electrode layer is arranged on the surface of one side, away from the substrate, of the second functional structure layer and is provided with a third electrode wire; the third electrode routing penetrates through the second functional structure layer and is respectively connected to the first electrode routing and the source electrode of the second active layer to form a bridging structure.
Furthermore, the first electrode layer is also provided with a second electrode routing; the second electrode routing penetrates through the first functional structure layer and is connected to the source electrode of the first active layer.
Furthermore, the second electrode layer is also provided with a fourth electrode wire, a fifth electrode wire and a sixth electrode wire; the fourth electrode wire penetrates through the second functional structure layer and is connected to the second electrode wire, and the second electrode wire and the fourth electrode wire form a source electrode wire of the first active layer; the fifth electrode wire penetrates through the second functional structure layer and is connected to the first electrode wire, and the first electrode wire and the fifth electrode wire form a drain electrode wire of the first active layer; the sixth electrode routing penetrates through the second functional structure layer and is connected to the drain electrode of the second active layer.
Further, the first functional structure layer comprises a first gate insulating layer which is arranged on the substrate and covers the first active layer; the second grid insulation layer is arranged on the first grid insulation layer; a first dielectric insulating layer disposed on the second gate insulating layer; the display panel further comprises a first gate layer which is arranged on the first gate insulating layer and corresponds to the first active layer; a second gate layer; the second gate insulating layer is disposed on the first active layer and corresponds to the first active layer.
Furthermore, the second functional structure layer comprises a third gate insulating layer arranged on the first dielectric insulating layer; a second dielectric insulating layer disposed on the third gate insulating layer; the display panel further comprises a third gate layer arranged on the third gate insulating layer, and the second dielectric insulating layer covers the third gate layer.
In order to achieve the above object, the present invention further provides a method for manufacturing a display panel, including the steps of: providing a substrate; preparing a first active layer on the upper surface of the substrate; preparing a first functional structure layer on the upper surface of the first active layer; forming a first through hole penetrating through the first functional structure layer and communicated to the source electrode and the drain electrode of the first active layer; forming a first electrode layer and the second active layer on the first functional structure layer, wherein a first electrode wire in the first electrode layer extends from the first through hole to a drain electrode of the first active layer; forming a second functional structure layer on the first functional structure layer and covering the first electrode layer and the second active layer; forming second through holes penetrating through the second functional structure layer, wherein one second through hole is communicated with the first electrode wiring, and the other second through hole is communicated with a source electrode on the second active layer; and forming a second electrode layer on the upper surface of the second functional structure layer, wherein a third electrode wire in the second electrode layer is connected to the first electrode wire and the source electrode of the second active layer through two second through holes to form a bridging structure.
Further, in the step of preparing a first functional structure layer on the upper surface of the first active layer, a first gate insulating layer is prepared on the upper surface of the first active layer; preparing a first gate layer on the upper surface of the first gate insulating layer, wherein the first gate layer is arranged opposite to the first active layer; preparing a second gate insulating layer on the upper surfaces of the first gate insulating layer and the first gate layer; preparing a second gate layer on the upper surface of the second gate insulating layer, wherein the second gate layer is arranged opposite to the first gate layer; and preparing a first dielectric insulating layer on the upper surfaces of the second gate insulating layer and the second gate layer.
Further, in the step of preparing the first electrode layer and the second active layer on the upper surface of the first functional structure layer and in the first through hole, a layer of semiconductor oxide material is coated on the upper surface of the first functional structure layer and in the first through hole, and the semiconductor oxide material in the first through hole is subjected to a conductor treatment to form the first electrode layer and the second active layer; the first electrode layer further comprises a second electrode trace; the second electrode routing penetrates through the first functional structure layer and is connected to the source electrode of the first active layer.
Further, in the step of preparing a second electrode layer on the upper surface of the second functional structure layer and in the second through hole, conducting treatment is performed on the first electrode layer at the bottom of the second through hole; preparing a second electrode layer on the upper surface of the second functional structure layer and in the second through hole, wherein the second electrode layer is also provided with a fourth electrode wire, a fifth electrode wire and a sixth electrode wire; the fourth electrode wire penetrates through the second functional structure layer and is connected to the second electrode wire, and the second electrode wire and the fourth electrode wire form a source electrode wire of the first active layer; the fifth electrode wire penetrates through the second functional structure layer and is connected to the first electrode wire, and the first electrode wire and the fifth electrode wire form a drain electrode wire of the first active layer; the sixth electrode routing penetrates through the second functional structure layer and is connected to the drain electrode of the second active layer.
Further, in the step of the second functional structure layer, a third gate insulating layer is prepared on the upper surfaces of the first dielectric insulating layer, the first electrode layer and the second active layer; preparing a third gate layer on the upper surface of the third gate insulating layer, wherein the third gate layer is arranged opposite to the second active layer; and preparing a second dielectric insulating layer on the upper surfaces of the third gate insulating layer and the third gate layer.
The invention has the technical effects that the electric signal of the first active layer is conducted to the film layer where the second active layer is located by the first electrode layer, so that the electric signals of the first active layer and the second active layer are arranged on the same layer, and a deep hole does not need to be dug downwards when the second electrode layer is connected in a cross-line mode, thereby ensuring the conduction of the electric signal, reducing the difficulty of the deep hole process, and simultaneously reducing the digging depth of the through hole can effectively improve the density of the dug hole, and further improving the pixel density of the display panel.
Drawings
FIG. 1 is a schematic view of a substrate according to an embodiment of the present invention;
fig. 2 is a schematic view of the display panel according to the embodiment of the invention after a first through hole is formed;
fig. 3 is a schematic view of the display panel according to the embodiment of the invention after a second through hole is formed;
fig. 4 is a schematic diagram of a display panel according to an embodiment of the invention after a first electrode layer and a second active layer are prepared;
FIG. 5 is a schematic structural diagram of a display panel according to an embodiment of the invention;
fig. 6 is a flowchart of a method for manufacturing a display panel according to an embodiment of the invention.
Some of the components are identified as follows:
1. a substrate; 2. a first active layer; 3. a second active layer; 4. a first functional structural layer; 5. a gate layer; 6. a first electrode layer; 7. a second functional structural layer; 8. a second electrode layer; 9. a passivation layer; 10. a planarization layer; 11. an anode layer; 12. a pixel defining layer; 13. a light emitting layer; 14. a spacer;
110. a first flexible base layer; 120. a barrier layer; 130. a second flexible base layer; 140. a buffer layer;
21. a semiconductor section; 22. a conductor part;
41. a first gate insulating layer; 42. a second gate insulating layer; 43. a first dielectric insulating layer;
51. a first gate layer; 52. a second gate layer;
61. a first electrode trace; 62. a second electrode trace;
71. a third gate insulating layer; 72; a second dielectric insulating layer; 70. a third gate layer;
81. a third electrode trace; 82. a fourth electrode trace; 83. a fifth electrode trace; 84. a sixth electrode trace;
100. a first through hole; 200. a second via.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Specifically, referring to fig. 1 to 5, an embodiment of the invention provides a display panel, which includes a substrate 1, a first active layer 2, a second active layer 3, a first functional structure layer 4, a gate layer 5, a first electrode layer 6, a second functional structure layer 7, a third gate layer 70, a second electrode layer 8, a passivation layer 9, a planarization layer 10, an anode layer 11, a pixel defining layer 12, a light emitting layer 13, and a spacer 14.
As shown in fig. 1, the substrate 1 is a flexible substrate, and includes a first flexible base layer 110, a barrier layer 120, a second flexible substrate 130 and a buffer layer 140, which are stacked, wherein the first flexible base layer 110 and the second flexible substrate 130 are made of polyimide materials, the barrier layer 120 and the buffer layer 140 are made of inorganic materials, and the substrate 1 functions as a substrate and has good buffer performance.
The first active layer 2 is disposed on the upper surface of the buffer layer 140, the material of the first active layer 2 is a semiconductor material, the first active layer 2 includes a semiconductor portion 21 and a conductor portion 22, the conductor portion 22 is disposed around the semiconductor portion 21, and the conductor portion 22 is a conductive active layer and has good conductivity.
The first functional structure layer 4 is disposed on the upper surface of the first active layer 2, and the first functional structure layer 4 includes a first gate insulating layer 41, a second gate insulating layer 42 and a first dielectric insulating layer 43, which have good insulating properties.
The gate layer 5 is disposed in the first functional structure layer 4, and the gate layer 5 includes a first gate layer 51 and a second gate layer 52, which can be used as signal lines such as scan lines of thin film transistors.
Specifically, the first gate insulating layer 41 is disposed on the upper surface of the first active layer 2, and the first gate layer 51 is disposed on the upper surface of the first gate insulating layer 41 and is disposed opposite to the semiconductor portion 21 of the first active layer 2. The second gate insulating layer 42 is disposed on the first gate layer 51 and the upper surface of the first gate insulating layer 41, and the second gate layer 51 is disposed on the upper surface of the second gate insulating layer 42 and above the first gate layer 41. The first dielectric insulating layer 43 is provided on the upper surfaces of the second gate electrode layer 52 and the second gate insulating layer 42.
The first through hole 100 penetrates through the first functional structure layer 4 and is disposed opposite to the conductor portion 22 of the first active layer 2, and a portion of the conductor portion 22 is exposed by the first through hole 100 to provide a passage for the subsequent electrical connection between the first electrode layer 6 and the first active layer 2 (see fig. 2).
The first electrode layer 6 is disposed on the upper surface of the first functional structure layer 4, specifically, on the upper surface of the first dielectric insulating layer 43, and extends into the first through hole 100. The material of the first electrode layer 6 is a semiconductor material, such as a semiconductor oxide material, in this embodiment, an indium gallium zinc oxide material is preferred, and the resistance of the indium gallium zinc oxide material is 500 to 1500 Ω, which is only one third of that of a general polyethylene material, and can be used as a preferred material of the active layer. The first electrode layer 6 in the first via hole 100 is a conductive layer after a conductive treatment, and has a small resistance to draw.
The first electrode layer 6 includes a first electrode trace 61 and a second electrode trace 62, the first electrode trace 61 penetrates through the first functional structure layer 4 and is connected to the drain electrode of the first active layer 2, and the second electrode trace 62 penetrates through the first functional structure layer 4 and is connected to the source electrode of the first active layer 2.
The second active layer 3 is disposed on the upper surface of the first functional structure layer 4, and an orthographic projection of the second active layer on the substrate 1 and an orthographic projection of the first active layer 2 on the substrate 1 are not overlapped with each other, specifically, the second active layer is disposed on the upper surface of the first dielectric insulating layer 43, and is disposed on the same surface as the first electrode layer 6, and the material of the second active layer is the same as that of the first electrode layer 6.
The second functional structure layer 7 is disposed on the upper surfaces of the second active layer 3, the first electrode layer 6 and the first functional structure layer 4, and plays an insulating role, and the second functional structure layer 7 includes a third gate insulating layer 71 and a second dielectric insulating layer 72. The third gate layer 70 is disposed on the upper surface of the third gate insulating layer 71 and is opposite to the second active layer 3.
The second via 200 penetrates the second functional structure layer 7 and is disposed opposite to the first electrode layer 6 and the second active layer 3 to provide a passage for the subsequent electrical connection of the second electrode layer 8 with the first electrode layer 6 and the second active layer 3 (see fig. 3).
The second electrode layer 8 is disposed on the upper surface of the second functional structure layer 7 and extends into the second through hole 200, and at least one second electrode layer 8 is connected to the first electrode layer 6 and the second active layer 3 (see fig. 4) through the second electrode layer in the second through hole 200.
The second electrode layer 8 includes a third electrode trace 81, a fourth electrode trace 82, a fifth electrode trace 83, and a sixth electrode trace 81.
The third electrode trace 81 penetrates through the second functional structure layer 7 and is connected to the first electrode trace 61 and the source of the second active layer 3, respectively, to form a bridge structure.
The fourth electrode trace 82 penetrates through the second functional structure layer 7 and is connected to the second electrode trace 62, and the second electrode trace 62 and the fourth electrode trace 82 form a source trace of the first active layer 2.
The fifth electrode trace 83 penetrates through the second functional structure layer 7 and is connected to the first electrode trace 61, and the first electrode trace 61 and the fifth electrode trace 83 form a drain trace of the first active layer 2.
The sixth electrode trace 84 penetrates the second functional structure layer 7 and is connected to the drain electrode of the second active layer 3.
The passivation layer 9 is arranged on the upper surfaces of the second electrode layer 8 and the second functional structure layer 7, and has a good technical effect of isolating external water and oxygen.
The flat layer 10 is disposed on the upper surface of the passivation layer 9, and has a function of smoothing the surface, so as to facilitate the deposition preparation of the subsequent film layer.
The anode layer 11 is disposed on the upper surface of the planarization layer 10, penetrates through the planarization layer 10 and the passivation layer 9, is electrically connected to a second electrode layer 8, and drives the light emitting layer 13 above the anode layer 9 to emit light through the thin film transistor.
The pixel defining layer 12 is disposed on the anode layer 11 and the upper surface of the flat layer 10, and the light emitting layer 13 is disposed in a through hole formed in the pixel defining layer 12, wherein the through hole is used for defining the size of the light emitting region.
The spacer 14 is disposed on the upper surface of the pixel defining layer 12, and has a good supporting effect.
The display panel in this embodiment is a Low Temperature Polycrystalline silicon Oxide (LTPO) display panel, and combines the advantages of the LTPS and Oxide display panels, and the Oxide in this embodiment is preferably Indium Gallium Zinc Oxide (IGZO), and has a good loudness speed and lower power consumption.
As shown in fig. 5, the display panel of this embodiment includes an LTPS tft 010 and an IGZO tft 020, the first active layer 2 belongs to the LTPS tft 010, the second active layer 3 belongs to the IGZO tft 020, the first electrode layer 6 is made of the same material as the first active layer 2 and is electrically connected to the first active layer 2, which is equivalent to disposing the first active layer 2 at the position of the first electrode layer 6, that is, at the same film layer as the second active layer 3, at this time, the third electrode routing 81 connects the first electrode layer 6 and the second active layer 3 in a cross-line manner, which is equivalent to electrically connecting the first active layer 2 and the second active layer 3, because the first active layer 2 is conducted to the same film layer as the second active layer 3 by the first electrode layer 6, the depth of the second through hole 200 of the second electrode layer 8 at the conducting position is the same, and there is no need to dig a deep hole for connection.
The display panel has the technical effects that the electric signals of the first active layer 2 are conducted to the film layer where the second active layer 3 is located by the aid of the first electrode layer 6, the electric signals of the first active layer 2 and the second active layer 3 are arranged on the same layer, deep holes do not need to be dug downwards when the second electrode layer 8 is connected in a cross-line mode, the electric signals are conducted, the deep hole technology difficulty is reduced, meanwhile, the hole digging density can be effectively improved by reducing the hole digging depth of the through holes, and the pixel density of the display panel is further improved.
As shown in fig. 6, the present embodiment further provides a method for manufacturing a display panel, including steps S1 to S8.
S1 provides a substrate 1, substrate 1 is the flexible substrate, and substrate 1 is the flexible substrate, including first flexible basic unit 110, barrier layer 120, second flexible substrate 130 and the buffer layer 140 of range upon range of setting, the material of first flexible basic unit 110 and second flexible substrate 130 is the polyimide material, and the material of barrier layer 120 and buffer layer 140 is inorganic material, and substrate 1 plays the substrate effect, has good shock-absorbing capacity (refer to fig. 1).
S2 is to form a first active layer 2 on the upper surface of the substrate 1, the first active layer 2 is disposed on the upper surface of the buffer layer 140, the first active layer 2 is made of a semiconductor material, the first active layer 2 includes a semiconductor portion 21 and a conductor portion 22, the conductor portion 22 is disposed around the semiconductor portion 21, and the conductor portion 22 is a conductive active layer and has good conductivity.
S3, a first functional structure layer 4 and a gate layer 5 are formed on the upper surface of the first active layer 2, specifically, a first gate insulating layer 41, a first gate layer 51, a second gate insulating layer 42, a second gate layer 52, and a first dielectric insulating layer 43 are sequentially formed.
Preparing a first gate insulating layer 41 on an upper surface of the first active layer 2; preparing a first gate layer 51 on the upper surface of the first gate insulating layer 41, the first gate layer 51 being disposed opposite to the first active layer 2; preparing a second gate insulating layer 42 on the upper surfaces of the first gate insulating layer 41 and the first gate layer 51; preparing a second gate layer 52 on the upper surface of the second gate insulating layer 42, wherein the second gate layer 52 is opposite to the first gate layer 51; a first dielectric insulating layer 43 is formed on the upper surfaces of the second gate insulating layer 42 and the second gate layer 52.
S4, a hole opening process is performed on the first functional structure layer 4 to form a first via 100, the first via 100 penetrates through the first functional structure layer 4 and is disposed opposite to the conductor portion 22 of the first active layer 2, and the first via 100 exposes a portion of the conductor portion 22 to provide a channel for electrical connection between the first electrode layer 6 and the first active layer 2 (see fig. 2).
S5 a layer of semiconductor material is deposited in the first functional structure layer 4 and the first via hole 100 to form the first electrode layer 6, specifically, the first electrode layer 6 is disposed on the upper surface of the first dielectric insulating layer 43 and extends into the first via hole 100. The semiconductor material is a semiconductor oxide material, in the embodiment, an indium gallium zinc oxide material is preferred, the resistance of the indium gallium zinc oxide material is 500-1500 Ω, and only one third of the resistance of a common polyethylene material can be used as a preferred material of the active layer. The first electrode layer 6 in the first via hole 100 is a conductive layer after a conductive treatment, and has a small resistance to draw.
The first electrode layer 6 includes a first electrode trace 61 and a second electrode trace 62, the first electrode trace 61 penetrates through the first functional structure layer 4 and is connected to the drain electrode of the first active layer 2, and the second electrode trace 62 penetrates through the first functional structure layer 4 and is connected to the source electrode of the first active layer 2.
The second active layer 3 is disposed on the upper surface of the first functional structure layer 4, and an orthographic projection of the second active layer on the substrate 1 and an orthographic projection of the first active layer 2 on the substrate 1 are not overlapped with each other, specifically, the second active layer is disposed on the upper surface of the first dielectric insulating layer 43, and is disposed on the same surface as the first electrode layer 6, and the material of the second active layer is the same as that of the first electrode layer 6.
S6 a second functional structure layer 7 is formed on the upper surfaces of the first electrode layer 6 and the second active layer 3, the second functional structure layer 7 is disposed on the upper surfaces of the second active layer 3, the first electrode layer 6 and the first functional structure layer 4 to perform an insulating function, and the second functional structure layer 7 includes a third gate insulating layer 71 and a second dielectric insulating layer 72.
Specifically, the third gate insulating layer 71 is prepared on the upper surfaces of the first dielectric insulating layer 43, the first electrode layer 6, and the second active layer 3; a third gate layer 70 is formed on the upper surface of the third gate insulating layer 71, and the third gate layer 70 is disposed opposite to the second active layer 3; a second dielectric insulating layer 72 is formed on the upper surfaces of the third gate insulating layer 71 and the third gate layer 70.
S7 is to open a hole on the second functional structure layer 7 to form a second via 200, where the second via 200 penetrates through the second functional structure layer 7 and is disposed opposite to the first electrode layer 6 and the second active layer 3 to provide a channel for the subsequent electrical connection between the second electrode layer 8 and the first electrode layer 6 and the second active layer 3 (see fig. 3).
S8 preparing a second electrode layer 8 in the second functional structure layer 7 and the second via 200, specifically, the second electrode layer 8 is disposed on the upper surface of the second functional structure layer 7 and extends into the second via 200, and at least one second electrode layer 8 is connected to the first electrode layer 6 and the second active layer 3 (see fig. 4) by crossing the second electrode layer in the second via 200.
The second electrode layer 8 includes a third electrode trace 81, a fourth electrode trace 82, a fifth electrode trace 83, and a sixth electrode trace 81.
The third electrode trace 81 penetrates through the second functional structure layer 7 and is connected to the first electrode trace 61 and the source of the second active layer 3, respectively, to form a bridge structure.
The fourth electrode trace 82 penetrates through the second functional structure layer 7 and is connected to the second electrode trace 62, and the second electrode trace 62 and the fourth electrode trace 82 form a source trace of the first active layer 2.
The fifth electrode trace 83 penetrates through the second functional structure layer 7 and is connected to the first electrode trace 61, and the first electrode trace 61 and the fifth electrode trace 83 form a drain trace of the first active layer 2.
The sixth electrode trace 84 penetrates the second functional structure layer 7 and is connected to the drain electrode of the second active layer 3.
The method for manufacturing a display panel according to this embodiment further includes a passivation layer manufacturing step, a planarization layer manufacturing step, an anode layer manufacturing step, a pixel definition layer manufacturing step, a light emitting layer manufacturing step, a spacer setting step, and the like.
The passivation layer 9 is arranged on the upper surfaces of the second electrode layer 8 and the second functional structure layer 7, and has a good technical effect of isolating external water and oxygen.
The flat layer 10 is disposed on the upper surface of the passivation layer 9, and has a function of smoothing the surface, so as to facilitate the deposition preparation of the subsequent film layer.
The anode layer 11 is disposed on the upper surface of the planarization layer 10, penetrates through the planarization layer 10 and the passivation layer 9, is electrically connected to a second electrode layer 8, and drives the light emitting layer 13 above the anode layer 9 to emit light through the thin film transistor.
The pixel defining layer 12 is disposed on the anode layer 11 and the upper surface of the flat layer 10, and the light emitting layer 13 is disposed in a through hole formed in the pixel defining layer 12, wherein the through hole is used for defining the size of the light emitting region.
The spacer 14 is disposed on the upper surface of the pixel defining layer 12, and has a good supporting effect.
The display panel prepared in this embodiment is a Low Temperature Polycrystalline silicon Oxide (LTPO) display panel, and combines the advantages of LTPS and Oxide display panels, and in this embodiment, the Oxide is preferably Indium Gallium Zinc Oxide (IGZO), and has a good loudness speed and lower power consumption.
The preparation method of the display panel has the technical effects that the first electrode layer 6 is used for conducting the electric signals of the first active layer 2 to the film layer where the second active layer 3 is located, the electric signals of the first active layer 2 and the second active layer 3 are arranged on the same layer, deep holes do not need to be dug downwards when the second electrode layer 8 is connected in a cross-line mode, the electric signals are conducted, the deep hole technology difficulty is reduced, meanwhile, the hole digging density can be effectively improved by reducing the hole digging depth of the through holes, and the pixel density of the display panel is further improved.
The embodiment can also provide a display device, which comprises the display panel as described above, and further comprises a backlight module and other devices, and can also achieve the technical effects of reducing the difficulty of the deep hole process, and simultaneously, reducing the downward digging depth of the through hole can effectively improve the density of the dug hole, and further improve the pixel density of the display panel.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display panel and the manufacturing method thereof provided by the embodiment of the invention are described in detail above, and the principle and the embodiment of the invention are explained by applying specific examples, and the description of the embodiment is only used for helping to understand the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A display panel, comprising:
a substrate;
the first active layer is arranged on the surface of one side of the substrate;
the first functional structure layer is arranged on the surface of one side, away from the substrate, of the first active layer;
the second active layer is arranged on the surface of one side, away from the substrate, of the first functional structure layer, and the orthographic projection of the second active layer on the substrate is not overlapped with the orthographic projection of the first active layer on the substrate;
the first electrode layer is arranged on the surface of one side, away from the substrate, of the first functional structure layer and provided with a first electrode wire, and the first electrode wire penetrates through the first functional structure layer and is connected to the drain electrode of the first active layer;
a second functional structure layer covering the first electrode layer and the second active layer; and
the second electrode layer is arranged on the surface of one side, away from the substrate, of the second functional structure layer and is provided with a third electrode wire; the third electrode routing penetrates through the second functional structure layer and is respectively connected to the first electrode routing and the source electrode of the second active layer to form a bridging structure.
2. The display panel of claim 1,
the first electrode layer is also provided with a second electrode routing;
the second electrode routing penetrates through the first functional structure layer and is connected to the source electrode of the first active layer.
3. The display panel of claim 2,
the second electrode layer is also provided with a fourth electrode wire, a fifth electrode wire and a sixth electrode wire;
the fourth electrode wire penetrates through the second functional structure layer and is connected to the second electrode wire, and the second electrode wire and the fourth electrode wire form a source electrode wire of the first active layer;
the fifth electrode wire penetrates through the second functional structure layer and is connected to the first electrode wire, and the first electrode wire and the fifth electrode wire form a drain electrode wire of the first active layer;
the sixth electrode routing penetrates through the second functional structure layer and is connected to the drain electrode of the second active layer.
4. The display panel of claim 1,
the first functional structure layer comprises
A first gate insulating layer disposed on the substrate and covering the first active layer;
the second grid insulation layer is arranged on the first grid insulation layer;
a first dielectric insulating layer disposed on the second gate insulating layer;
the display panel further comprises
A first gate layer disposed on the first gate insulating layer and corresponding to the first active layer;
a second gate layer; the second gate insulating layer is disposed on the first active layer and corresponds to the first active layer.
5. The display panel of claim 4,
the second functional structure layer comprises
A third gate insulating layer disposed on the first dielectric insulating layer;
a second dielectric insulating layer disposed on the third gate insulating layer;
the display panel further comprises
And the third gate layer is arranged on the third gate insulating layer, and the second dielectric insulating layer covers the third gate layer.
6. A preparation method of a display panel is characterized by comprising the following steps:
providing a substrate;
preparing a first active layer on the upper surface of the substrate;
preparing a first functional structure layer on the upper surface of the first active layer;
forming a first through hole penetrating through the first functional structure layer and communicated to the source electrode and the drain electrode of the first active layer;
forming a first electrode layer and the second active layer on the first functional structure layer, wherein a first electrode wire in the first electrode layer extends from the first through hole to a drain electrode of the first active layer;
forming a second functional structure layer on the first functional structure layer and covering the first electrode layer and the second active layer;
forming second through holes penetrating through the second functional structure layer, wherein one second through hole is communicated with the first electrode wiring, and the other second through hole is communicated with a source electrode on the second active layer; and
and forming a second electrode layer on the upper surface of the second functional structure layer, wherein a third electrode wire in the second electrode layer is connected to the first electrode wire and the source electrode of the second active layer through two second through holes to form a bridging structure.
7. The method of manufacturing a display panel according to claim 6, wherein in the step of manufacturing the first functional structure layer on the upper surface of the first active layer,
preparing a first gate insulating layer on the upper surface of the first active layer;
preparing a first gate layer on the upper surface of the first gate insulating layer, wherein the first gate layer is arranged opposite to the first active layer;
preparing a second gate insulating layer on the upper surfaces of the first gate insulating layer and the first gate layer;
preparing a second gate layer on the upper surface of the second gate insulating layer, wherein the second gate layer is arranged opposite to the first gate layer; and
and preparing a first dielectric insulating layer on the upper surfaces of the second gate insulating layer and the second gate layer.
8. The method according to claim 6, wherein in the step of forming the first electrode layer and the second active layer on the upper surface of the first functional structure layer and in the first via hole,
coating a layer of semiconductor oxide material on the upper surface of the first functional structure layer and in the first through hole, and conducting the semiconductor oxide material in the first through hole to form a first electrode layer and a second active layer;
the first electrode layer further comprises a second electrode trace; the second electrode routing penetrates through the first functional structure layer and is connected to the source electrode of the first active layer.
9. The method according to claim 6, wherein in the step of forming a second electrode layer on the upper surface of the second functional structure layer and in the second through hole,
conducting treatment on the first electrode layer at the bottom of the second through hole;
preparing a second electrode layer on the upper surface of the second functional structure layer and in the second through hole, wherein the second electrode layer is also provided with a fourth electrode wire, a fifth electrode wire and a sixth electrode wire;
the fourth electrode wire penetrates through the second functional structure layer and is connected to the second electrode wire, and the second electrode wire and the fourth electrode wire form a source electrode wire of the first active layer;
the fifth electrode wire penetrates through the second functional structure layer and is connected to the first electrode wire, and the first electrode wire and the fifth electrode wire form a drain electrode wire of the first active layer;
the sixth electrode routing penetrates through the second functional structure layer and is connected to the drain electrode of the second active layer.
10. The method according to claim 7, wherein in the step of forming the second functional structure layer,
preparing a third gate insulating layer on the upper surfaces of the first dielectric insulating layer, the first electrode layer and the second active layer;
preparing a third gate layer on the upper surface of the third gate insulating layer, wherein the third gate layer is arranged opposite to the second active layer;
and preparing a second dielectric insulating layer on the upper surfaces of the third gate insulating layer and the third gate layer.
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| WO2023159675A1 (en) * | 2022-02-22 | 2023-08-31 | 深圳市华星光电半导体显示技术有限公司 | Display panel and preparation method for display panel |
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| CN109964316A (en) * | 2019-04-19 | 2019-07-02 | 京东方科技集团股份有限公司 | Array substrate, preparation method and display device |
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