CN112397614A - Silicon wafer surface treatment method of HIT battery, HIT battery preparation method and HIT battery - Google Patents
Silicon wafer surface treatment method of HIT battery, HIT battery preparation method and HIT battery Download PDFInfo
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 90
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 90
- 239000010703 silicon Substances 0.000 title claims abstract description 90
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004381 surface treatment Methods 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 87
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 63
- 239000001257 hydrogen Substances 0.000 claims abstract description 63
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000007789 gas Substances 0.000 claims abstract description 43
- 238000010438 heat treatment Methods 0.000 claims abstract description 23
- 238000006243 chemical reaction Methods 0.000 claims abstract description 22
- 238000004140 cleaning Methods 0.000 claims abstract description 21
- 230000008021 deposition Effects 0.000 claims abstract description 19
- 239000003344 environmental pollutant Substances 0.000 claims abstract description 16
- 231100000719 pollutant Toxicity 0.000 claims abstract description 16
- 238000011065 in-situ storage Methods 0.000 claims abstract description 15
- 230000000694 effects Effects 0.000 claims abstract description 13
- 150000002431 hydrogen Chemical class 0.000 claims abstract description 12
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims description 49
- 238000012545 processing Methods 0.000 claims description 17
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- 229910004012 SiCx Inorganic materials 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000003672 processing method Methods 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 17
- 238000005516 engineering process Methods 0.000 abstract description 6
- 235000012431 wafers Nutrition 0.000 description 71
- 239000010408 film Substances 0.000 description 63
- 229910021419 crystalline silicon Inorganic materials 0.000 description 10
- 238000001035 drying Methods 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 8
- 230000009257 reactivity Effects 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 239000000356 contaminant Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 6
- 238000002156 mixing Methods 0.000 description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 5
- 239000002994 raw material Substances 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 4
- 239000003513 alkali Substances 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 238000001179 sorption measurement Methods 0.000 description 4
- 239000007888 film coating Substances 0.000 description 3
- 238000009501 film coating Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention relates to the technical field of solar cells, in particular to a silicon wafer surface treatment method of an HIT cell and a preparation method of the HIT cell, wherein the treatment method comprises the following treatment steps before an intrinsic amorphous silicon film layer and an impurity-doped amorphous silicon film layer are deposited on the surface of a silicon wafer: cleaning a crystal silicon wafer; sending the cleaned silicon wafer into a deposition system, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing pollutants physically or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma; the HIT battery is prepared by adopting the silicon wafer surface treatment technology, the surface of the silicon wafer is firstly subjected to hydrogen plasma in-situ cleaning before intrinsic amorphous silicon is deposited, the efficiency fluctuates within 23.5-23% and the EL black angle proportion fluctuates within 5-80% before the silicon wafer surface treatment technology is adopted; after the process is applied, the efficiency can be stabilized at about 23.5%, and the black angle proportion can be controlled within 3%.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a silicon wafer surface treatment method of an HIT cell, a HIT cell preparation method and the HIT cell.
Background
With the development of the photovoltaic market, people have an urgent need for high-efficiency crystalline silicon cells. Compared with a p-type crystalline silicon cell, the n-type crystalline silicon is not sensitive to metal impurities or has good endurance performance, so that minority carriers of the n-type crystalline silicon have larger diffusion length; in addition, the n-type crystalline silicon is doped with phosphorus, so that the formation of a B-O complex caused by illumination is avoided, and the light-induced degradation phenomenon in a p-type crystalline silicon cell is avoided. Therefore, n-type crystalline silicon cells are becoming the subject of much attention by research institutions and photovoltaic enterprises.
In all n-type crystalline silicon cells, the HIT cell innovatively adopts a structure of a monocrystalline silicon substrate and an amorphous silicon thin film heterojunction, and the method of depositing an amorphous silicon thin film on crystalline silicon enables the HIT cell to have the advantages of both the crystalline silicon cell and the thin film cell. The HIT battery has the characteristics of high power generation amount, low power consumption cost, simple structure, high stability, low battery cost, low process temperature, high photoelectric conversion efficiency, good temperature characteristic, double-sided power generation and the like, and is a final solution for future battery technology acknowledged by practitioners in the battery industry and is also known as the next air port of the photovoltaic battery industry.
The process of the industrialization of HIT batteries still faces a number of challenges in terms of the overall situation at present. The HIT battery has high requirement on the surface cleanliness of the silicon wafer, and the silicon wafer is dried by a drying groove or transferred from the drying groove to a CVD film coating process in the actual production process, and is easy to receive trace O in the environment in the turnover process of the CVD silicon wafer3、NOx、SOx、H2Due to the influence of S and the like, the surface of a silicon wafer is polluted or oxidized, so that the HIT battery is blackened at the corner of an EL image, and the conversion efficiency and the yield of the battery are influenced.
Disclosure of Invention
The purpose of the invention is: the processing method can overcome the problem that the corners of an EL image are blackened due to the fact that the HIT battery is easily affected by the environment from cleaning to a CVD transfer process in the preparation process, and therefore conversion efficiency and yield of the battery piece are improved.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a silicon wafer surface treatment method of an HIT battery comprises the following treatment steps before depositing an amorphous silicon film layer on the surface of a silicon wafer:
cleaning a crystal silicon wafer;
sending the cleaned silicon wafer into a deposition system, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing the pollutants physically or chemically adsorbed on the surface by utilizing the reactivity of the hydrogen plasma, wherein the pollutants comprise O3、NOx、SOx、H2S and the like.
Further, the hydrogen is pure hydrogen or a mixed gas containing hydrogen, and the mixed gas containing hydrogen is H2With Ar, He, NF3、CF4、SF6Any one or more of them, H in the mixed gas2The proportion is arbitrary; adding Ar, He and NF into the mixed gas3、CF4、SF6Ar He mainly plays a role in regulating plasma ion bombardment; the latter F-containing gas mainly enhances the chemical activity of the plasma, and can improve the performance of the battery to a certain extent, and how to select is selected according to the actual production needs.
Further, the heating temperature range is 0-250 ℃, the gas pressure is 0.1-10 mbar, and the power density of the power supply is 1-500 mW/cm2The processing time is 1-100 s.
Furthermore, the intrinsic amorphous silicon film layer is selected from one or a combination of a-Si: H, a-SiOx: H, a-SiCx: H, uc-Si: H, uc-SiOx: H, uc-SiCx: H.
Furthermore, the doped amorphous silicon film layer is a p-type doped amorphous silicon film layer or an n-type doped amorphous silicon film layer.
The invention further aims to provide the HIT battery preparation method which is high in battery conversion efficiency, high in yield and simple in preparation process.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a method of manufacturing a HIT battery, the method comprising the steps of:
s1, using a crystal silicon wafer as a substrate, and conventionally cleaning the substrate;
s2, feeding the cleaned silicon wafer into a PECVD deposition system, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing pollutants physically or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma;
s3, depositing a first intrinsic amorphous silicon film layer and a first doped amorphous silicon film layer on the first surface of the silicon wafer after hydrogen plasma in-situ treatment;
s4, turning over the silicon wafer, then entering the PECVD deposition system again, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing pollutants physically or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma; the contaminants include O3、NOx、SOx、H2S, and the like;
s5, depositing a second intrinsic amorphous silicon film layer and a second doped amorphous silicon film layer on the second surface of the silicon wafer after hydrogen plasma in-situ treatment;
s6, depositing a first transparent conducting layer on the first doped amorphous silicon film layer, and depositing a second transparent conducting layer on the second doped amorphous silicon film layer;
and S7, finally, arranging a first metal electrode layer on the first transparent conducting layer, and arranging a second metal electrode layer on the second transparent conducting layer.
Further, the hydrogen is pure hydrogen or a mixed gas containing hydrogen, and the mixed gas containing hydrogen is H2With Ar, He, NF3、CF4、SF6Any one or more of them, H in the mixed gas2The ratio is arbitrary.
Further, the heating temperature range is 0-250 ℃, the gas pressure is 0.1-10 mbar, and the power density of the power supply is 1-500 mW/cm2The processing time is 1-100 s.
Still another object of the present invention is to provide an HIT battery with high battery conversion efficiency, high yield and simple manufacturing process.
An HIT battery is prepared by adopting the method.
The technical scheme adopted by the invention has the beneficial effects that:
in the production process of the HIT battery, the silicon wafer is dried by a drying groove after being subjected to texturing and cleaning or is transferred to a CVD film coating process from the drying groove, and the CVD silicon wafer is easy to receive trace O in the environment in the overturning process3The effects of NOx, SOx, H2S, etc., cause contamination or oxidation of the silicon wafer surface, which results in the blackening of the HIT cell at the edges of the EL image, affecting cell conversion efficiency and yield. The HIT cell is prepared by adopting the silicon wafer surface treatment technology, and before the intrinsic amorphous silicon is deposited, the surface of the silicon wafer is subjected to hydrogen plasma in-situ cleaning, so that the adverse effects of pollutants physically or chemically adsorbed on the surface on the cell conversion efficiency and yield are avoided; before the silicon wafer surface treatment technology is adopted, the efficiency fluctuates between 23.5 and 23 percent, and the EL black angle proportion is between 5 and 80 percent; fluctuation within the range; after the process is applied, the efficiency can be stabilized at about 23.5%, and the black angle proportion can be controlled within 3%.
Detailed Description
The present invention will now be described in further detail with reference to specific examples. The following examples are intended to provide those skilled in the art with a more complete understanding of the present invention, and are not intended to limit the scope of the present invention. Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Example 1
A silicon wafer surface treatment method of an HIT battery adopts the following treatment steps before an intrinsic amorphous silicon film layer and a doped amorphous silicon film layer are deposited on the surface of a silicon wafer:
(1) conventionally cleaning a crystal silicon wafer;
(2) sending the cleaned silicon wafer into a PECVD deposition system, and introducing pure H2Setting the heating temperature at 50 ℃, the gas pressure at 10mbar and the power supply power at 30mW/cm2Processing time 100 s; removing surface physical adsorption or chemical adsorption pollutant, such as O, by using hydrogen plasma reaction activity3、NOx、SOx、H2S and the like.
The intrinsic amorphous silicon film layer in the embodiment can be one or a combination of a-Si H, a-SiOx H, a-SiCx H, uc-Si H, uc-SiOx H, uc-SiCx H; the doped amorphous silicon film layer can be a p-type doped amorphous silicon film layer or an n-type doped amorphous silicon film layer; the above treatment processes are all applicable.
Example 2
A silicon wafer surface treatment method of an HIT battery adopts the following treatment steps before an intrinsic amorphous silicon film layer and a doped amorphous silicon film layer are deposited on the surface of a silicon wafer:
(1) conventionally cleaning a crystal silicon wafer;
(2) feeding the cleaned silicon wafer into a PECVD deposition system, and introducing hydrogen gas containing H2The mixed gas of (1) is specifically H2A mixture obtained by mixing the raw materials with Ar according to any proportion; setting the heating temperature at 50 ℃, the gas pressure at 10mbar and the power supply power at 30mW/cm2Processing time 100 s; removing surface physisorbed or chemisorbed contaminants, such as O, by using the reactivity of hydrogen plasma3、NOx、SOx、H2S, and the like;
in the embodiment, the intrinsic amorphous silicon film layer can be one or a combination of a-Si H, a-SiOx H, a-SiCx H, uc-Si H, uc-SiOx H, uc-SiCx H; the doped amorphous silicon film layer can be a p-type doped amorphous silicon film layer or an n-type doped amorphous silicon film layer; the above treatment processes are all applicable.
Example 3
A silicon wafer surface treatment method of an HIT battery adopts the following treatment steps before an intrinsic amorphous silicon film layer and a doped amorphous silicon film layer are deposited on the surface of a silicon wafer:
(1) conventionally cleaning a crystal silicon wafer;
(2) feeding the cleaned silicon wafer into a PECVD deposition system, and introducing hydrogen gas containing H2The mixed gas of (1) is specifically H2A mixture obtained by mixing the raw materials with Ar according to any proportion; setting the heating temperature at 200 deg.C, gas pressure at 2mbar, and power supply power at 30mW/cm2Processing time 100 s; removing surface physisorbed or chemisorbed contaminants, such as O, by using the reactivity of hydrogen plasma3、NOx、SOx、H2S, and the like;
the intrinsic amorphous silicon film layer can be one or a combination of a-Si H, a-SiOx H, a-SiCx H, uc-Si H, uc-SiOx H, uc-SiCx H; the doped amorphous silicon film layer can be a p-type doped amorphous silicon film layer or an n-type doped amorphous silicon film layer; the above treatment processes are all applicable.
Example 4
A silicon wafer surface treatment method of an HIT battery adopts the following treatment steps before an intrinsic amorphous silicon film layer and a doped amorphous silicon film layer are deposited on the surface of a silicon wafer:
(1) conventionally cleaning a crystal silicon wafer;
(2) feeding the cleaned silicon wafer into a PECVD deposition system, and introducing hydrogen gas containing H2The mixed gas of (1) is specifically H2With Ar, He, NF3、CF4And SF6The mixture mixed according to any proportion is set with the heating temperature of 200 ℃, the gas pressure of 2mbar and the power supply power of 30mW/cm2Processing time 20 s; removing surface physisorbed or chemisorbed contaminants, such as O, by using the reactivity of hydrogen plasma3、 NOx、SOx、H2S and the like.
In the embodiment, the intrinsic amorphous silicon film layer can be one or a combination of a-Si H, a-SiOx H, a-SiCx H, uc-Si H, uc-SiOx H, uc-SiCx H; the doped amorphous silicon film layer can be a p-type doped amorphous silicon film layer or an n-type doped amorphous silicon film layer; the above treatment processes are all applicable.
Comparative examples 1 to 4
The conventional cleaning operation is only adopted before the intrinsic amorphous silicon film layer and the doped amorphous silicon film layer are deposited on the surface of the silicon wafer, and other operations are the same as those of the embodiments 1-4.
The numbers of EL black angles of the silicon wafers treated in the normal period and the abnormal period in examples 1 to 4 were counted in batches. The numbers of battery silicon wafers EL black corners in the normal period and the abnormal period in comparative examples 1 to 4 were counted in batches.
Specific data statistics are shown in table 1.
TABLE 1
The baseline process conditions in the table correspond to comparative examples 1-4.
Example 5
A silicon wafer surface treatment method of an HIT battery comprises the following steps:
s1, an N-type monocrystalline silicon wafer is used as a substrate, and alkali texturing and RCA cleaning are carried out on the substrate;
s2, feeding the cleaned silicon wafer into a PECVD deposition system, and introducing pure H2Setting the heating temperature at 50 ℃, the gas pressure at 10mbar and the power supply power at 30mW/cm2Processing time 100; removing O physically adsorbed or chemically adsorbed on the surface by using the reaction activity of hydrogen plasma3、NOx、SOx、H2S and other pollutants;
s3, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the front surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing an n-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s4, turning over the silicon wafer, then entering the PECVD deposition system again, and introducing pure H2Setting heating temperature at 50 deg.C,Gas pressure 10mbar, power supply power 30mW/cm2Processing time 100; removal of surface physisorbed or chemisorbed contaminants, such as O, by the reactivity of the hydrogen plasma3、NOx、SOx、 H2S, and the like;
s5, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the back surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing a p-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s6, respectively depositing ITO transparent conducting layers with the thickness of 80nm on the n-type heavily-doped amorphous silicon film layer and the p-type heavily-doped amorphous silicon film layer by adopting PVD (physical vapor deposition) equipment;
and S7, finally, respectively printing low-temperature silver paste on the front surface and the back surface by adopting a screen printing mode, and drying and curing to form the metal grid line electrode.
Example 6
A silicon wafer surface treatment method of an HIT battery comprises the following steps:
s1, an N-type monocrystalline silicon wafer is used as a substrate, and alkali texturing and RCA cleaning are carried out on the substrate;
s2, feeding the cleaned silicon wafer into a PECVD deposition system, and introducing hydrogen, wherein the hydrogen contains H2The mixed gas of (1) is specifically H2A mixture obtained by mixing the raw materials with Ar according to any proportion; setting the heating temperature at 50 ℃, the gas pressure at 10mbar and the power supply power at 30mW/cm2Processing time 100 s; removing O physically adsorbed or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma3、NOx、SOx、H2S and other pollutants;
s3, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the front surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing an n-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s4, turning over the silicon wafer, then entering the PECVD deposition system again, and introducing hydrogen, wherein the hydrogen contains H2The mixed gas of (1) is specifically H2A mixture obtained by mixing the raw materials with Ar according to any proportion; setting the heating temperature at 50 ℃, the gas pressure at 10mbar and the power supply power at 30mW/cm2Processing time 100 s; removing surface physical adsorption or chemical adsorption pollutant, such as O, by using hydrogen plasma reaction activity3、NOx、SOx、H2S, and the like;
s5, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the back surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing a p-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s6, respectively depositing ITO transparent conducting layers with the thickness of 80nm on the n-type heavily-doped amorphous silicon film layer and the p-type heavily-doped amorphous silicon film layer by adopting PVD (physical vapor deposition) equipment;
and S7, finally, respectively printing low-temperature silver paste on the front surface and the back surface by adopting a screen printing mode, and drying and curing to form the metal grid line electrode.
Example 7
A silicon wafer surface treatment method of an HIT battery comprises the following steps:
s1, an N-type monocrystalline silicon wafer is used as a substrate, and alkali texturing and RCA cleaning are carried out on the substrate;
s2, feeding the cleaned silicon wafer into a PECVD deposition system, and introducing hydrogen, wherein the hydrogen contains H2The mixed gas of (1) is specifically H2A mixture obtained by mixing the raw materials with Ar according to any proportion; setting the heating temperature at 200 deg.C, gas pressure at 2mbar, and power supply power at 30mW/cm2Processing time 100 s; removing O physically adsorbed or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma3、NOx、SOx、H2S and other pollutants;
s3, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the front surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing an n-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s4, turning over the silicon wafer, then entering the PECVD deposition system again, and introducing H2Setting the heating temperature at 200 deg.C, gas pressure at 2mbar, and power supply power at 30mW/cm2Processing time 20 s; removing surface physisorbed or chemisorbed contaminants, such as O, by using the reactivity of hydrogen plasma3、NOx、SOx、H2S, and the like;
s5, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the back surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing a p-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s6, respectively depositing ITO transparent conducting layers with the thickness of 80nm on the n-type heavily-doped amorphous silicon film layer and the p-type heavily-doped amorphous silicon film layer by adopting PVD (physical vapor deposition) equipment;
and S7, finally, respectively printing low-temperature silver paste on the front surface and the back surface by adopting a screen printing mode, and drying and curing to form the metal grid line electrode.
Example 8
A silicon wafer surface treatment method of an HIT battery comprises the following steps:
s1, an N-type monocrystalline silicon wafer is used as a substrate, and alkali texturing and RCA cleaning are carried out on the substrate;
s2, feeding the cleaned silicon wafer into a PECVD deposition system, and introducing H2Setting the heating temperature at 200 deg.C, gas pressure at 2mbar, and power supply power at 30mW/cm2Processing time 20 s; removing O physically adsorbed or chemically adsorbed on the surface by using the reactivity of hydrogen plasma3、NOx、SOx、H2S and other pollutants;
s3, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the front surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing an n-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s4, turning over the silicon wafer, then entering the PECVD deposition system again, and introducing H2Setting the heating temperature at 200 deg.C, gas pressure at 2mbar, and power supply power at 30mW/cm2Processing time 20 s; removing surface physisorbed or chemisorbed contaminants, such as O, by using the reactivity of hydrogen plasma3、NOx、SOx、H2S, and the like;
s5, depositing an intrinsic amorphous silicon film layer with the thickness of 5nm on the back surface of the silicon wafer after hydrogen plasma in-situ treatment, and then depositing a p-type heavily-doped amorphous silicon film layer with the thickness of 5 nm;
s6, respectively depositing ITO transparent conducting layers with the thickness of 80nm on the n-type heavily-doped amorphous silicon film layer and the p-type heavily-doped amorphous silicon film layer by adopting PVD (physical vapor deposition) equipment;
and S7, finally, respectively printing low-temperature silver paste on the front surface and the back surface by adopting a screen printing mode, and drying and curing to form the metal grid line electrode.
Comparative examples 5 to 8
In the production process of the battery pieces in comparative examples 5 to 8: the conventional cleaning operation is only adopted before the intrinsic amorphous silicon film layer and the doped amorphous silicon film layer are deposited on the surface of the silicon wafer, and other operations are the same as the examples 5-8.
The conversion efficiency of the silicon wafers processed in the normal period and the abnormal period in examples 5 to 8 was detected and counted. The conversion efficiencies of the battery silicon wafers in the normal period and the abnormal period in comparative examples 5 to 8 were examined and counted.
Specific data statistics are shown in table 2.
TABLE 2
The baseline process conditions in the table correspond to comparative examples 5-8.
In summary, the following steps: those skilled in the art will know or infer from the foregoing that: in the production process of the HIT battery, silicon wafers are dried by a drying groove or transferred from the drying groove to a CVD film coating process after being subjected to texturing and cleaning, and the CVD silicon wafers are easy to receive trace O in the environment in the overturning process3、NOx、SOx、H2The influence of S and the like causes the surface of the silicon wafer to be polluted or oxidized, so that the HIT battery is blackened at the corner of an EL image, and the conversion efficiency and the yield of the battery are influenced. The HIT cell is prepared by adopting the silicon wafer surface treatment technology, and before the intrinsic amorphous silicon is deposited, the surface of the silicon wafer is subjected to hydrogen plasma in-situ cleaning, so that the adverse effects of pollutants physically or chemically adsorbed on the surface on the cell conversion efficiency and yield are avoided; the requirement of plant service can be reduced, when the process is unstable, the efficiency can be reduced from 23.5% to about 23%, and the EL black angle ratio can be increased from within 5% to 70-90%; after the process is applied, the efficiency can be stabilized at 23.5%, the black angle proportion can be controlled within 3%, the black edge and black angle proportion of a battery EL test is obviously reduced, and the yield stability is obviously improved.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. The technical scope of the present invention is not limited to the contents of the specification, and must be determined according to the scope of the claims.
Claims (10)
1. A silicon wafer surface treatment method of an HIT battery is characterized by comprising the following steps: the processing method comprises the following processing steps before depositing the amorphous silicon film layer on the surface of the silicon wafer:
cleaning a crystal silicon wafer;
sending the cleaned silicon wafer into a deposition system, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing the pollutants physically or chemically adsorbed on the surface by utilizing the reaction activity of the hydrogen plasma.
2. The silicon wafer surface treatment method of the HIT cell as claimed in claim 1, wherein: the hydrogen is pure hydrogen or a mixed gas containing hydrogen.
3. The silicon wafer surface treatment method of the HIT cell as claimed in claim 2, wherein: the mixed gas containing hydrogen adopts H2With Ar, He, NF3、CF4、SF6Any one or more of them, H in the mixed gas2The ratio is arbitrary.
4. The silicon wafer surface treatment method of the HIT cell as claimed in claim 1, wherein: the heating temperature range is 0-250 ℃, the gas pressure is 0.1-10 mbar, and the power density is 1-500 mW/cm2The processing time is 1-100 s.
5. The silicon wafer surface treatment method of the HIT cell as claimed in claim 1, wherein: the intrinsic amorphous silicon film layer is selected from one or a combination of a-Si of H, a-SiOx of H, a-SiCx of H, uc-Si of H, uc-SiOx of H, uc-SiCx of H.
6. The silicon wafer surface treatment method of the HIT cell as claimed in claim 5, wherein: the doped amorphous silicon film layer is a p-type doped amorphous silicon film layer or an n-type doped amorphous silicon film layer.
7. A preparation method of an HIT battery is characterized by comprising the following steps: the preparation method comprises the following steps:
s1, using a crystal silicon wafer as a substrate, and conventionally cleaning the substrate;
s2, feeding the cleaned silicon wafer into a PECVD deposition system, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing pollutants physically or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma;
s3, depositing a first intrinsic amorphous silicon film layer and a first doped amorphous silicon film layer on the first surface of the silicon wafer after hydrogen plasma in-situ treatment;
s4, turning over the silicon wafer, then entering the PECVD deposition system again, introducing hydrogen, and setting the following parameters: heating temperature, gas pressure, power supply power and treatment time, and removing pollutants physically or chemically adsorbed on the surface by utilizing the reaction activity of hydrogen plasma;
s5, depositing a second intrinsic amorphous silicon film layer and a second doped amorphous silicon film layer on the second surface of the silicon wafer after hydrogen plasma in-situ treatment;
s6, depositing a first transparent conducting layer on the first doped amorphous silicon film layer, and depositing a second transparent conducting layer on the second doped amorphous silicon film layer;
and S7, finally, arranging a first metal electrode layer on the first transparent conducting layer, and arranging a second metal electrode layer on the second transparent conducting layer.
8. The method of claim 7, wherein the HIT cell is formed by: the hydrogen is pure hydrogen or mixed gas containing hydrogen; the mixed gas containing hydrogen adopts H2With Ar, He, NF3、CF4、SF6Any one or more of them, H in the mixed gas2The ratio is arbitrary.
9. The method of claim 7, wherein the HIT cell is formed by: the heating temperature range is 0-250 ℃, the gas pressure is 0.1-10 mbar, and the power density is 1-500 mW/cm2The processing time is 1-100 s.
10. An HIT battery, characterized in that: the HIT battery is prepared by the preparation method of any one of claims 7 to 9.
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