CN112397400A - Semiconductor packaging method - Google Patents
Semiconductor packaging method Download PDFInfo
- Publication number
- CN112397400A CN112397400A CN201910760729.1A CN201910760729A CN112397400A CN 112397400 A CN112397400 A CN 112397400A CN 201910760729 A CN201910760729 A CN 201910760729A CN 112397400 A CN112397400 A CN 112397400A
- Authority
- CN
- China
- Prior art keywords
- layer
- chip
- packaged
- positioning
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 71
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 239000010410 layer Substances 0.000 claims abstract description 147
- 239000012790 adhesive layer Substances 0.000 claims abstract description 28
- 230000002093 peripheral effect Effects 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 28
- 238000005538 encapsulation Methods 0.000 claims description 22
- 238000005520 cutting process Methods 0.000 claims description 8
- 238000000465 moulding Methods 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 27
- 230000000694 effects Effects 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 description 28
- 239000011241 protective layer Substances 0.000 description 24
- 239000000047 product Substances 0.000 description 8
- 239000004033 plastic Substances 0.000 description 6
- 229920003023 plastic Polymers 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000007639 printing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 238000000748 compression moulding Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000002372 labelling Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The application provides a semiconductor packaging method, which comprises the following steps: forming an adhesive layer on the carrier plate, and dividing the adhesive layer into a plurality of arrangement areas and blank areas, wherein the blank areas are arranged around the arrangement areas; positioning holes are formed in the blank area and are located in the outer peripheral edge area of the arrangement area; according to the position of the positioning hole, the chip to be packaged is attached in the arrangement area; and forming an encapsulating layer, wherein the encapsulating layer covers the bonding layer, at least one part of the encapsulating layer is filled in the positioning hole to form a positioning convex column, and the encapsulating layer is used for encapsulating the chip to be encapsulated. The application can ensure the mounting precision in the chip mounting process by arranging the positioning hole to position the accurate position of the to-be-packaged patch on the carrier plate; through the positioning convex column formed at the positioning hole, the arrangement position of each chip to be packaged can be accurately positioned and identified in the following rewiring process, and the accurate positioning effect is realized again.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor packaging method.
Background
In a panel-level packaging process flow, precise positioning of a die on a panel has always been a key factor in panel packaging. The precise positioning of the die on the panel can have a significant impact on the wiring process and can affect the yield of the product.
Particularly, in the large panel packaging process, the curing area of the plastic packaging resin is large in the plastic packaging process, the curing shrinkage degree is correspondingly large, and in the hot press molding process, due to the difference between the thermal expansion coefficients of the plastic packaging resin and the thermal expansion coefficients of the molding resin material, the bare chip and the rigid carrier plate, a large amount of stress is accumulated in the material in the temperature rising and reducing processes, so that the molded product after molding is warped. Both the curing shrinkage of the panel resin and the warping of the panel cause the position of the die to be changed on the panel.
The variation of the position of the bare chip on the panel makes it difficult to locate the precise position of the bare chip in the panel in the subsequent wiring process, which greatly affects the wiring process and even makes the wiring process difficult.
The problem of positioning the die becomes one of the keys of the whole process, and the problem of positioning the die even limits the development of the enlargement of the panel size, and becomes a technical barrier in the large-size panel package.
Disclosure of Invention
The invention provides a semiconductor packaging method which can realize multiple times of accurate positioning on a chip to be packaged.
To achieve the above object, an embodiment of the present invention provides a semiconductor packaging method, which includes:
forming an adhesive layer on a carrier plate, and dividing the adhesive layer into a plurality of arrangement areas and blank areas, wherein the blank areas are arranged around the arrangement areas;
positioning holes are formed in the blank area and are located in the outer peripheral edge area of the arrangement area;
according to the position of the positioning hole, a chip to be packaged is attached to the arrangement area;
and forming an encapsulating layer, wherein the encapsulating layer covers the bonding layer, at least one part of the encapsulating layer is filled in the positioning hole to form a positioning convex column, and the encapsulating layer is used for encapsulating the chip to be encapsulated.
Optionally, the arrangement area is rectangular, and the positioning holes are arranged along an extension line of a diagonal line of the arrangement area; or the like, or, alternatively,
the positioning holes are arranged corresponding to four corners of the arrangement area.
Optionally, the depth of the positioning hole is less than or equal to the thickness of the adhesive layer.
Optionally, the material forming the encapsulating layer is a liquid granular plastic package material.
Optionally, the working temperature used for forming the encapsulating layer and the positioning convex columns is 130-175 ℃.
Optionally, when forming the encapsulation layer and forming the positioning pillars, the material of the encapsulation layer enters the positioning holes by pressurization.
Optionally, the positioning hole is rectangular.
Optionally, after forming the encapsulation layer, the method comprises:
stripping the carrier plate to expose the front surfaces of the chips to be packaged;
and forming a rewiring structure on the front surface of the chip to be packaged according to the position of the positioning convex column, wherein the rewiring structure is used for leading out a welding pad on the front surface of the chip to be packaged.
Optionally, in forming a rewiring structure on the front surface of the chip to be packaged, the rewiring structure is located between the chip to be packaged and the positioning boss;
after a rewiring structure is formed on the front side of the chip to be packaged, the method comprises the following steps:
and cutting the whole packaging structure into a plurality of packaging bodies along one side of the positioning convex column close to the rewiring structure.
Optionally, after forming the encapsulating layer and before peeling off the carrier plate, the method comprises:
and a support layer is pasted on the first surface of the encapsulating layer far away from the carrier plate.
Optionally, after a rewiring structure is formed on the front surface of the chip to be packaged, the method includes:
and stripping the supporting layer.
According to the semiconductor packaging method provided by the embodiment of the application, the positioning hole is arranged to position the accurate position of the to-be-packaged patch on the carrier plate, so that the mounting precision in the chip mounting process can be ensured, the chip mounting precision can be detected according to the position of the positioning hole, the mounting position of the to-be-packaged patch can be adjusted in real time, and meanwhile, the precision production requirement of the subsequent process can be met, so that the success rate of later-stage packaging and the yield of products are ensured; furthermore, through the positioning convex column formed in the positioning hole, the arrangement position of each chip to be packaged can be accurately positioned and identified in the subsequent rewiring process, and the accurate positioning effect is realized again.
Drawings
Fig. 1 is a flowchart of a semiconductor packaging method according to an exemplary embodiment of the present application.
Fig. 2(a) -2 (o) are process flow diagrams of a method of semiconductor packaging according to an exemplary embodiment of the present application.
Fig. 3 is a schematic structural diagram of a semiconductor package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the terms "a" or "an" and the like in the description and in the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
According to various embodiments of the present disclosure, a semiconductor packaging method is provided. In the packaging process, forming an adhesive layer on a carrier plate, and dividing the adhesive layer into a plurality of arrangement areas and blank areas, wherein the blank areas are arranged around the arrangement areas; positioning holes are formed in the blank area and are located in the outer peripheral edge area of the arrangement area; according to the position of the positioning hole, a chip to be packaged is attached to the arrangement area; and forming an encapsulating layer, wherein the encapsulating layer covers the bonding layer, at least one part of the encapsulating layer is filled in the positioning hole to form a positioning convex column, and the encapsulating layer is used for encapsulating the chip to be encapsulated. The positioning hole is arranged to position the accurate position of the to-be-packaged patch on the carrier plate, so that the mounting precision in the chip mounting process can be ensured, the chip mounting precision can be detected according to the position of the positioning hole, the mounting position of the to-be-packaged patch can be adjusted in real time, and meanwhile, the precision production requirement of the subsequent process can be met, so that the success rate of later-period packaging and the yield of products are ensured; furthermore, through the positioning convex column formed in the positioning hole, the arrangement position of each chip to be packaged can be accurately positioned and identified in the subsequent rewiring process, and the accurate positioning effect is realized again.
As shown in fig. 1, 2(a) -2 (o), and 3, the present disclosure provides a semiconductor packaging method and a semiconductor packaging structure.
Fig. 1 is a flowchart of a proposed semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 1, the semiconductor packaging method includes the steps of:
step 101: forming an adhesive layer on a carrier plate, and dividing the adhesive layer into a plurality of arrangement areas and blank areas, wherein the blank areas are arranged around the arrangement areas;
step 102: positioning holes are formed in the blank area and are located in the outer peripheral edge area of the arrangement area;
step 103: according to the position of the positioning hole, a chip to be packaged is attached to the arrangement area;
step 104: and forming an encapsulating layer, wherein the encapsulating layer covers the bonding layer, at least one part of the encapsulating layer is filled in the positioning hole to form a positioning convex column, and the encapsulating layer is used for encapsulating the chip to be encapsulated.
In this embodiment, before step 101, that is, before the chip to be packaged is mounted on the carrier, a protection layer may be formed on the front surface of the chip to be packaged. The protective layer may be formed on the front surface of the semiconductor wafer before the semiconductor wafer is cut into a plurality of chips to be packaged, and then the semiconductor wafer is cut to obtain the chips to be packaged with the protective layer formed on the front surface. It is understood that, when the process allows, the protective layer may be formed on the front surface of each chip to be packaged after the semiconductor wafer is cut into the chips to be packaged, which is selected according to the actual situation.
As shown in fig. 2(a), a protection layer 202 is formed on the front surface of the semiconductor wafer 100, i.e. the surface corresponding to the front surface of the to-be-packaged chip 201, and then the semiconductor wafer 100 on which the protection layer 202 is formed is cut along the cutting streets to obtain a plurality of to-be-packaged chips 201 on which the protection layer is formed.
The protection layer 202 is made of an insulating material, such as polyimide, epoxy resin, abf (ajinomoto build film), pbo (polybenzoxazole), and the like. Alternatively, the material of the protective layer is selected to be insulating and capable of accommodating chemical cleaning, polishing, and the like. The protective layer may be formed on the semiconductor wafer by Lamination (Coating), Coating (Coating), Printing (Printing), and the like.
In step 101, as shown in fig. 2(b), an adhesive layer 203 is formed on the carrier 200 for bonding the chip 201 to be packaged. The adhesive layer 203 may be made of a material that is easily peeled off to peel off the carrier board 200 and the chip 201 to be packaged that is packaged on the back side, for example, a thermal release material that can be heated to lose its adhesiveness.
In other embodiments, the adhesive layer 203 may have a two-layer structure, i.e., a thermal separation material layer and a die attach layer, the thermal separation material layer is attached to the carrier 200 and loses its viscosity when heated, so as to be peeled off from the carrier 200, and the die attach layer has an adhesive material layer and can be used to attach the die 201 to be packaged. After the packaged chip 201 is peeled off from the carrier 200, the chip adhesion layer thereon may be removed by chemical cleaning. In one embodiment, the adhesive layer 203 may be formed on the carrier 200 by lamination, printing, or the like.
Next, as shown in fig. 2(c) and 2(d), a plurality of arrangement regions 2031 and blank regions 2032 are divided on the adhesive layer 203, the blank regions 2032 are disposed around the arrangement regions 2031, and fig. 2(d) is a schematic view of a structure at another angle in fig. 2 (c). The dashed lines in fig. 2(c) and 2(d) do not exist, and the labeling is only for convenience of understanding the technical solution in the embodiment.
In the present embodiment, the shape of the layout area 2031 is rectangular, because the shape and size of the layout area 2031 are determined according to the finally formed package, and the package in the prior art is substantially rectangular.
In step 102, as shown in fig. 2(e), a positioning hole 2033 is formed in the blank area 2032, and the positioning hole 2033 is located at an outer peripheral area of the arrangement area 2031. The outer peripheral area of the arrangement area 2031 is a part of the outer side of the edge line of the arrangement area 2031, and the positioning hole 2033 located at the outer peripheral area of the arrangement area 2031 means that the positioning hole 2033 can contact the edge line of the arrangement area 2031, and may have a certain distance from the edge line of the arrangement area 2031, and the distance is set according to actual needs. Therefore, the positioning holes are formed in the blank area of the carrier plate, and the positions of the to-be-packaged patches on the carrier plate are positioned through the positioning holes, so that the mounting precision in the chip mounting process can be ensured, and the to-be-packaged patches can be accurately mounted at the preset arrangement positions; furthermore, the chip mounting precision can be detected according to the position of the positioning hole, so that the mounting position of the to-be-packaged patch can be adjusted in real time.
In the embodiment, each arrangement region 2031 is provided with a positioning hole 2033, but the invention is not limited to this, and a part of the arrangement region 2031 may be provided with a positioning hole 2033.
The positioning hole 2033 may be formed in the adhesive layer 203 by patterning an opening, or may be formed in another manner, which is not limited herein. The depth of the positioning hole is smaller than or equal to the thickness of the bonding layer.
As shown in fig. 2(f), the positioning holes 2033 may be disposed outside two diagonal corners of the layout area 2031 along an extension line of the diagonal of the layout area 2031. Thus, when the chip 201 to be packaged is continuously mounted on the carrier 200, the precise position where the chip 201 to be packaged should be arranged can be calculated by using the diagonal line.
Alternatively, as shown in fig. 2(g), the positioning holes 2033 may be provided at the outer sides of the four corners corresponding to the four corners of the arrangement area. Thus, when the chip 201 to be packaged is continuously mounted on the carrier 200, the precise position where the chip 201 to be packaged should be arranged can be calculated by using the diagonal intersection.
It should be noted that the dashed lines in fig. 2(e), fig. 2(f), and fig. 2(g) do not exist, and the reference numerals are only used to facilitate understanding of the technical solutions in the embodiments.
Thus, by providing the positioning hole 2033, when the chip 201 to be packaged is attached to the carrier 200, the positioning hole 2033 can be used to position the predetermined arrangement position of the chip 201 to be packaged, so that the arrangement of the chip 201 to be packaged is more accurate.
Preferably, the positioning hole 2033 is rectangular in shape, so that in the subsequent step, the positioning boss formed in the positioning hole 2033 is also rectangular in shape; therefore, after the whole packaging structure is completed, the whole packaging structure is cut into a plurality of packaging bodies along one side of the positioning convex column, which is close to the rewiring structure, and the position of the cutting line can be more conveniently positioned.
In step 103, as shown in fig. 2(h), the chip 201 to be packaged is mounted in the arrangement area 2031 according to the position of the positioning hole 2033. A plurality of chips 201 to be packaged may be mounted in the arrangement area 2031, or only one chip 201 to be packaged may be mounted, and the number of the chips 201 to be packaged in one arrangement area 2031 is set according to actual needs, which is not limited herein. The chip 201 to be packaged is attached to the carrier 200 through the adhesive layer 203. A certain distance is left between the chip 201 to be packaged and the positioning hole 2033, and the distance is reserved for a rewiring structure formed on the front surface of the chip to be packaged in the subsequent step. The dashed lines in fig. 2(h) do not exist, and the labeling is only for convenience of understanding the technical solution in the embodiment.
In step 104, an encapsulating layer 204 is formed on the adhesive layer 203 and on the back surface of the chip 201 to be packaged, and at least a portion of the encapsulating layer 204 is filled in the positioning hole 2033 to form a positioning pillar 300. As shown in fig. 2(i), the encapsulating layer 204 is used to completely encapsulate the carrier 200 and the chip 201 to be packaged, so as to reconstruct a flat plate structure, so that after the carrier 200 is peeled off, the re-wiring and packaging can be continued on the reconstructed flat plate structure. Since the positioning hole 2033 is formed in the adhesive layer 203, during the molding process of the encapsulating layer 204, the material forming the encapsulating layer 204 enters the positioning hole 2033, and finally the positioning post 300 corresponding to the positioning hole 2033 is formed on the flat plate structure. The positioning convex columns 300 can play a role in secondary positioning of the chip 201 to be packaged in the subsequent step in the process of forming the rewiring structure on the front surface of the chip 201 to be packaged, that is, the positioning convex columns 300 can be used for accurately positioning and identifying the arrangement position of each chip 201 to be packaged on the flat plate structure in the subsequent rewiring process, so as to play a role in secondary positioning of the chip 201 to be packaged, the first positioning is to position the position of the chip 201 to be packaged on the carrier plate 200 through the positioning holes 2033, so that the mounting precision in the chip mounting process can be ensured, and the chip 201 to be packaged can be accurately mounted at the preset arrangement position.
In one embodiment, the encapsulating layer 204 may be formed by laminating an epoxy resin film or an abf (ajinomoto build film), or by Injection molding (Injection molding), Compression molding (Compression molding) or Transfer molding (Transfer molding) of an epoxy resin compound. In this embodiment, in order to better form the positioning convex pillar 300, a liquid granular plastic package material is used as the material of the encapsulating layer 204, so that the material of the encapsulating layer 204 can more easily enter the positioning hole 2033 and fill the whole positioning hole 2033 in the high-temperature and high-pressure plastic package process, thereby forming the positioning convex pillar 300 with a full shape.
The inventors have found through extensive experiments that, in some embodiments, the working temperature of 130 ℃ to 175 ℃ is better for forming the encapsulation layer 204 and the positioning pillars 300, so as to form the positioning pillars 300. The operating temperature is optionally 130 ℃, 145 ℃, 160 ℃ or 175 ℃. In this embodiment, the working temperature is 160 ℃, so as to facilitate the material of the encapsulating layer 204 to enter the positioning hole 2033 more easily at a high temperature, thereby better forming the positioning pillar 300.
The inventors have found, through extensive experiments, that in some embodiments, when forming the encapsulation layer 204 and forming the positioning studs 300, the positioning studs 300 can be better formed by pressing the material of the encapsulation layer into the positioning holes.
The encapsulating layer 204 includes a first surface 2041 opposite to the carrier 200, and is substantially flat and parallel to the surface of the carrier 200. The thickness of the encapsulating layer 204 may be reduced by grinding or polishing the first surface 2041, and in an alternative embodiment, the thickness of the encapsulating layer 204 may be reduced to the back side of the chip 201 to be packaged.
When the encapsulating layer 204 is used for encapsulating, since the encapsulating layer needs to be molded under high pressure during molding, the encapsulating material is easy to penetrate between the carrier 200 and the chip 201 to be encapsulated in the process. Through the embodiment of the disclosure, the protective layer 202 is formed outside the chip 201 to be packaged, the protective layer 202 can prevent the encapsulating material from penetrating into the surface of the chip 201 to be packaged, and even if the encapsulating material penetrates into the surface, the surface of the protective layer 202 can be directly processed through a chemical mode or a grinding mode after being peeled off from the carrier plate, so that the surface can not directly contact with the front surface of the chip 201 to be packaged, and further the circuit structure on the front surface of the chip 201 to be packaged can not be damaged.
Further, optionally, after step 104, the packaging method further includes attaching a support layer on the encapsulation layer away from the first surface of the carrier.
The support layer is attached to at least a portion of the first surface of the envelope layer. As shown in fig. 2(j), in an embodiment, a supporting layer 205 is attached on the first surface 2041 of the encapsulating layer 204 away from the carrier 200, and the supporting layer 205 covers the entire area of the first surface 2041 of the encapsulating layer 204.
The material strength of the supporting layer is greater than that of the encapsulating layer, so that the supporting layer can effectively improve and ensure the mechanical strength of the encapsulating structure in the encapsulating process, and effectively inhibit the adverse effect caused by the deformation of each structure, thereby improving the product encapsulating effect. In other embodiments, the supporting layer may also be formed on the first surface 2041 of the encapsulating layer 204 by Spraying (Spraying), Printing (Printing), Coating (Coating), or the like.
Further, in an embodiment, as shown in fig. 2(k), after the supporting layer 205 is attached, the packaging method further includes peeling off the carrier 200, and after the carrier 200 is peeled off, the exposed surfaces are the lower surfaces of the protective layer 202 and the encapsulating layer 204 on the front surface of the chip 201 to be packaged.
In an embodiment, since the adhesive layer 203 is disposed between the carrier 200 and the protective layer 202, the adhesive layer 203 can be reduced in viscosity after being heated by heating, so as to peel off the carrier 200. By peeling the carrier board 200 by heating the adhesive layer 203, damage to the chip 201 to be packaged during the peeling process can be minimized.
After the carrier 200 is peeled off, the lower surface of the encapsulating layer 204 and the passivation layer 202 facing the carrier 200 are exposed. After the carrier 200 is peeled off, a flat plate structure including the chip 201 to be packaged, the protection layer 202 covering the front surface of the chip 201 to be packaged, and the encapsulating layer 204 is obtained, and the flat plate structure is further provided with the positioning convex column 300. The flat plate structure thus formed can be subjected to rewiring or the like according to the actual situation. In other embodiments, the carrier board 200 can be peeled off directly and mechanically.
In the embodiment of the present disclosure, after the carrier board 200 is peeled off, the surface of the protection layer 202 is exposed, and at this time, the chip adhesion layer in the adhesive layer 202 is also present on the surface of the protection layer 202, and when the chip adhesion layer is removed by a chemical method, the protection layer 202 can also protect the surface of the chip to be packaged from being damaged; after the adhesive layer is completely removed, if the encapsulating material permeates in the adhesive layer, the surface can be flattened by adopting a chemical cleaning or grinding mode, so that the subsequent wiring is facilitated; if the protective layer is not provided, the surface of the chip to be packaged cannot be processed in a chemical mode or a grinding mode so as to avoid damaging a circuit on the front surface of the chip to be packaged.
For the embodiment without a supporting layer, the carrier sheet may be peeled off after step S104 to expose the passivation layer and the encapsulation layer. The specific stripping method can be referred to the above description, and is not repeated herein.
Next, as shown in fig. 2(l), a passivation opening 2021 is formed on the passivation layer at a position corresponding to the pads of the to-be-packaged chip, where each passivation opening 2021 is at least correspondingly located on a pad of the to-be-packaged chip 201 or a line led out from the pad, so that the pad on the front surface of the to-be-packaged chip 201 or the line led out from the pad is exposed from the passivation opening 2021. If the material of the protective layer is a laser-reactive material, the protective layer can be opened by forming one protective layer opening 2021 at a time by laser patterning; if the passivation layer is made of a photosensitive material, a plurality of passivation openings 2021 may be formed at a time by photolithography and patterning. The shape of the passivation opening 2021 may be round, but may also be other shapes such as oval, square, linear, etc.
Further, in some embodiments, according to the position of the positioning pillar, re-wiring is performed on the protection layer 202 of the chip 201 to be packaged, i.e., a re-wiring structure is formed. The front surface of the chip 201 to be packaged is provided with bonding pads of a circuit inside the chip, and the bonding pads can be led out by re-wiring on the front surface of the chip 201 to be packaged.
As shown in fig. 2(m), the rewiring structure includes: a first redistribution layer 206 formed on the passivation layer 202 and the exposed encapsulation layer 204 and electrically connected to the pads of the chip 201 through the passivation opening 2021; and a front-side first encapsulation layer 207 formed on the first redistribution layer 206 and the exposed passivation layer 202 and the exposed encapsulation layer 204 and having a first opening, wherein a first conductive pillar 208 electrically connected to the first redistribution layer 206 is disposed in the first opening of the front-side first encapsulation layer 207. The first conductive pillar 208 is preferably circular, but may be rectangular, square, or other shapes, and the conductive pillar 208 is electrically connected to the first redistribution layer 206.
Further, in an alternative embodiment, when forming the rewiring structure, if the surface is completely made of the same material, a passivation layer may be formed on the protection layer 202, and particularly, a passivation layer opening corresponding to the protection layer opening 2021 may be formed on the passivation layer for rewiring.
In an embodiment, since the passivation layer opening is already formed on the passivation layer 202, at least the passivation layer opening can be directly seen when the first redistribution layer 206 is formed, so that the first redistribution layer 206 can be aligned more accurately when formed.
Further, after forming the re-wiring structure, the packaging method further includes peeling off the support layer 205. As shown in fig. 2 (n). The supporting layer 205 can be peeled off directly mechanically, or by other methods, which is not limited in this application and can be set according to the specific application environment.
As described above, in the rewiring process, the arrangement position of each chip 201 to be packaged on the flat plate structure can be accurately identified through the positioning pillars 300, so that the rewiring structure can be accurately formed at the preset position. Thus, under the positioning action of the positioning convex column 300, the wiring precision is improved, and the product yield is improved.
Preferably, the rewiring structure is controlled to be located between the chip to be packaged and the positioning boss 300. In this way, after the rewiring structure is formed and the package of the rewiring structure is completed, when the whole package structure is cut into a plurality of packages by laser or mechanical cutting, the cutting line C is accurately positioned by the positioning boss 300, for example, the whole package structure can be cut into a plurality of packages along one side of the positioning boss 300 close to the rewiring structure, as shown in fig. 2(o), and the structure diagram of the formed package is shown in fig. 3. When cutting is performed along the side of the positioning convex column 300 close to the rewiring structure, the cutting line C can just remove the positioning convex column 300 without any influence on the subsequent packaging body.
Further, in an embodiment, the re-wiring may be repeated on the front side of the chip 201, for example, a second re-wiring layer or more re-wiring layers may be formed outside the front side encapsulation layer in the same manner to achieve multi-layer re-wiring of the product.
It should be noted that, in another embodiment, the protective layer opening 2021 is formed at a position on the protective layer corresponding to the pads of the to-be-packaged chips, and the pads on the front surface of the to-be-packaged chip 201 or the lines led out from the pads may be exposed from the protective layer opening 2021 before the wafer on which the protective layer is formed is cut into the to-be-packaged chips. The specific scheme for forming the opening of the passivation layer can be referred to the above description, and is not repeated herein.
After the chip to be packaged formed with the protective layer 202 is adhered to the adhesive layer 203 of the carrier 200, the plurality of protective layer openings 2021 are in a hollow state.
In another embodiment, after forming the passivation layer opening 2021 on the passivation layer at a position corresponding to the pads of the plurality of chips to be packaged, the method further includes: and filling a conductive medium in the opening of the protective layer, so that the conductive medium is electrically connected with the welding pad of the chip to be packaged. The conductive medium forms a vertical connecting structure in the opening of the protective layer, so that the welding pad on the surface of the chip is extended to the surface of the protective layer, and the protective layer can surround and form the periphery of the connecting structure.
Fig. 3 is a schematic structural diagram of a chip package structure obtained by using the semiconductor packaging method according to an exemplary embodiment of the present disclosure. As shown in fig. 3, the semiconductor package structure includes:
the encapsulating layer 204 is provided with an inwards concave cavity;
the chip 201 is arranged in the cavity, and the back surface of the chip 201 faces to the bottom of the cavity;
the passivation layer 202 is formed on the front surface of the chip 201, and a passivation layer opening 2021 is formed on the passivation layer 202, where the passivation layer opening 2021 is located at a position corresponding to the pad on the front surface of the chip 201;
and the rewiring structure is formed on the front surface of the chip 201 and is used for leading out the bonding pad on the front surface of the chip 201.
In some embodiments, the rewiring structure includes: a first redistribution layer 206 formed on the passivation layer 202 and the exposed encapsulation layer 204 and electrically connected to the pads of the chip 201 through the passivation opening 2021; and a front side first encapsulation layer 207 formed on the first redistribution layer 206 and the exposed passivation layer 202 and the exposed encapsulation layer 204 and having a first opening 2071, wherein a first conductive pillar 208 electrically connected to the first redistribution layer 206 is disposed in the first opening 2071 of the front side first encapsulation layer 207.
In another embodiment, the re-routing structure includes more re-routing layers to achieve multi-level re-routing of the product.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict.
In the present application, the apparatus embodiments and the method embodiments may be complementary to each other without conflict. The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (11)
1. A semiconductor packaging method, comprising:
forming an adhesive layer on a carrier plate, and dividing the adhesive layer into a plurality of arrangement areas and blank areas, wherein the blank areas are arranged around the arrangement areas;
positioning holes are formed in the blank area and are located in the outer peripheral edge area of the arrangement area;
according to the position of the positioning hole, a chip to be packaged is attached to the arrangement area;
and forming an encapsulating layer, wherein the encapsulating layer covers the bonding layer, at least one part of the encapsulating layer is filled in the positioning hole to form a positioning convex column, and the encapsulating layer is used for encapsulating the chip to be encapsulated.
2. The semiconductor packaging method according to claim 1, wherein the arrangement region is rectangular, and the positioning holes are provided along an extension line of a diagonal line of the arrangement region; or the like, or, alternatively,
the positioning holes are arranged corresponding to four corners of the arrangement area.
3. The semiconductor packaging method according to claim 1, wherein a depth of the positioning hole is less than or equal to a thickness of the adhesive layer.
4. The semiconductor packaging method according to claim 1, wherein a material forming the encapsulating layer is a liquid granular molding compound.
5. The semiconductor packaging method of claim 1, wherein the operating temperature used in forming the encapsulation layer and forming the positioning posts is 130 ℃ to 175 ℃.
6. The semiconductor packaging method of claim 1, wherein material of the encapsulation layer is forced into the positioning holes while forming the encapsulation layer and forming the positioning posts.
7. The semiconductor packaging method according to claim 1, wherein the positioning hole has a rectangular shape.
8. A semiconductor packaging method according to any one of claims 1-7, after forming an encapsulation layer, the method comprising:
stripping the carrier plate to expose the front surfaces of the chips to be packaged;
and forming a rewiring structure on the front surface of the chip to be packaged according to the position of the positioning convex column, wherein the rewiring structure is used for leading out a welding pad on the front surface of the chip to be packaged.
9. The semiconductor packaging method according to claim 8, wherein in forming a re-wiring structure on the front surface of the chip to be packaged, the re-wiring structure is located between the chip to be packaged and the positioning post;
after a rewiring structure is formed on the front side of the chip to be packaged, the method comprises the following steps:
and cutting the whole packaging structure into a plurality of packaging bodies along one side of the positioning convex column close to the rewiring structure.
10. The method of claim 8, wherein after forming the encapsulation layer and before peeling the carrier, the method comprises:
and a support layer is pasted on the first surface of the encapsulating layer far away from the carrier plate.
11. The semiconductor packaging method according to claim 10, wherein after forming a re-wiring structure on the front surface of the chip to be packaged, the method comprises:
and stripping the supporting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910760729.1A CN112397400B (en) | 2019-08-16 | 2019-08-16 | Semiconductor packaging method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910760729.1A CN112397400B (en) | 2019-08-16 | 2019-08-16 | Semiconductor packaging method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112397400A true CN112397400A (en) | 2021-02-23 |
| CN112397400B CN112397400B (en) | 2022-07-01 |
Family
ID=74603151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910760729.1A Active CN112397400B (en) | 2019-08-16 | 2019-08-16 | Semiconductor packaging method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112397400B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115635706A (en) * | 2022-12-26 | 2023-01-24 | 天津爱思达新材料科技有限公司 | Processing method of carbon fiber composite material part |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110084382A1 (en) * | 2009-10-07 | 2011-04-14 | Wei-Ming Chen | Chip package and fabrication method thereof |
| CN102157401A (en) * | 2011-01-30 | 2011-08-17 | 南通富士通微电子股份有限公司 | High-density SIP (system in package) method of chip |
| CN105374731A (en) * | 2015-11-05 | 2016-03-02 | 南通富士通微电子股份有限公司 | Packaging method |
| CN108172551A (en) * | 2016-11-29 | 2018-06-15 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| TWI630665B (en) * | 2017-06-20 | 2018-07-21 | 恆勁科技股份有限公司 | Method of making chip package structure |
| CN208767284U (en) * | 2016-11-29 | 2019-04-19 | Pep创新私人有限公司 | Chip-packaging structure |
-
2019
- 2019-08-16 CN CN201910760729.1A patent/CN112397400B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110084382A1 (en) * | 2009-10-07 | 2011-04-14 | Wei-Ming Chen | Chip package and fabrication method thereof |
| CN102157401A (en) * | 2011-01-30 | 2011-08-17 | 南通富士通微电子股份有限公司 | High-density SIP (system in package) method of chip |
| CN105374731A (en) * | 2015-11-05 | 2016-03-02 | 南通富士通微电子股份有限公司 | Packaging method |
| CN108172551A (en) * | 2016-11-29 | 2018-06-15 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN208767284U (en) * | 2016-11-29 | 2019-04-19 | Pep创新私人有限公司 | Chip-packaging structure |
| TWI630665B (en) * | 2017-06-20 | 2018-07-21 | 恆勁科技股份有限公司 | Method of making chip package structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115635706A (en) * | 2022-12-26 | 2023-01-24 | 天津爱思达新材料科技有限公司 | Processing method of carbon fiber composite material part |
| CN115635706B (en) * | 2022-12-26 | 2023-02-28 | 天津爱思达新材料科技有限公司 | Processing method of carbon fiber composite material part |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112397400B (en) | 2022-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108172551B (en) | Chip packaging method and packaging structure | |
| TWI756311B (en) | Chip packaging method and packaging structure | |
| TW201820565A (en) | Method of packaging chip and chip package structure | |
| CN111755348A (en) | Semiconductor device packaging method and semiconductor device | |
| CN111883521A (en) | Multi-chip 3D packaging structure and manufacturing method thereof | |
| US10163848B2 (en) | Semiconductor package | |
| CN112397400B (en) | Semiconductor packaging method | |
| CN111668116B (en) | Semiconductor packaging method | |
| US20190006223A1 (en) | Method and apparatus for wafer level packaging | |
| CN111916359B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668108B (en) | Semiconductor packaging method | |
| CN111933534B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN111668123B (en) | Semiconductor packaging method | |
| CN111668113A (en) | Semiconductor packaging method and semiconductor packaging assembly | |
| CN111668112A (en) | Semiconductor packaging method | |
| CN111668118B (en) | Semiconductor packaging method | |
| CN113725090A (en) | Semiconductor packaging method | |
| CN111668122B (en) | Semiconductor packaging method | |
| CN111668111B (en) | Semiconductor packaging method | |
| CN113725097B (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN112233987B (en) | Manufacturing method of chip packaging structure | |
| CN113725091A (en) | Semiconductor packaging method | |
| CN115483118A (en) | Semiconductor packaging method | |
| CN114975132A (en) | Semiconductor packaging method and semiconductor packaging structure | |
| CN115483119A (en) | Semiconductor packaging method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |