CN112394611B - Mask plate and manufacturing method of three-dimensional memory - Google Patents
Mask plate and manufacturing method of three-dimensional memory Download PDFInfo
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- CN112394611B CN112394611B CN202011282268.0A CN202011282268A CN112394611B CN 112394611 B CN112394611 B CN 112394611B CN 202011282268 A CN202011282268 A CN 202011282268A CN 112394611 B CN112394611 B CN 112394611B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 15
- 238000003860 storage Methods 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 9
- 239000004020 conductor Substances 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 5
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a mask plate and a manufacturing method of a three-dimensional memory. The alignment pattern in the mask plate comprises a plurality of alignment units, wherein the alignment units are arranged at intervals along a first direction, and the minimum distance between every two adjacent alignment units is H 1 Each alignment unit consists of a plurality of alignment areas which are arranged at intervals along the second direction, and the minimum spacing between the adjacent alignment areas is H 2 ，H 1 Greater than H 2 Each alignment region has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length being greater than 1, and an included angle is formed between the first direction and the second direction. On the premise of alignment patterns with the same size, the alignment areas which are positioned in the same row in the alignment unit in the traditional mask plate can be communicated, and the alignment holes formed by the mask plate can be ensured to be filled with enough conductive materials by expanding the size of the alignment areas, so that alignment signals in the subsequent photoetching process are ensured, and the alignment effect is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a mask plate and a manufacturing method of a three-dimensional memory.
Background
In the prior art, a main function of a Flash Memory (Flash Memory) is that stored information can be kept for a long time under the condition of no power-up, and the Flash Memory has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further increase the Bit Density (Bit Density) of the flash memory while reducing the Bit Cost (Bit Cost), a three-dimensional flash memory (3D NAND) has been further proposed.
In the 3D NAND flash memory structure, a stacked 3D NAND memory structure is implemented by vertically stacking multiple layers of data storage units. The stacked structure in a 3D NAND memory array typically includes a core array region and a step region in which a step structure and conductive contacts connected to the step structure are distributed, and the memory array is typically bonded to peripheral circuitry by covering the step structure with a dielectric layer having contact holes (TSVs) and forming an interconnect layer connected to the conductive contacts in the contact holes.
In the prior art, the SADP process is generally adopted to form the contact hole, the SADP process has higher requirement on alignment, in order to obtain better alignment effect, a mask plate adopted in the photoetching process can divide an alignment pattern (8 um or 8.8 um) during design, however, the alignment pattern is generally divided into a small hole array with smaller size, so that conductive material is less filled, thereby influencing an alignment signal of the mask plate for a conductive layer formed later, further causing poor alignment effect and even wafer reject (wafer alignment failure).
Disclosure of Invention
The invention mainly aims to provide a mask plate and a manufacturing method of a three-dimensional memory, so as to solve the problem that an alignment pattern of the mask plate in the prior art is easy to cause poor alignment signals of the mask plate adopted later.
In order to achieve the above object, according to one aspect of the present invention, there is provided a mask including an alignment pattern for passing an exposure light source, the alignment pattern including a plurality of alignment units, the alignment units being spaced apart along a first direction, a minimum pitch between adjacent alignment units being H 1 Each alignment unit consists of a plurality of alignment areas which are arranged at intervals along the second direction, and the minimum spacing between the adjacent alignment areas is H 2 ，H 1 Greater than H 2 Each alignment region has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length being greater than 1, and an included angle is formed between the first direction and the second direction.
Further, adjacent alignment units are arranged at intervals through first shading areas, adjacent alignment areas in the same alignment unit are arranged at intervals through second shading areas, and the first shading areas are communicated with the second shading areas.
Further, the methodSecond length and H 2 The ratio is 1:1 to 4:1.
further, adjacent alignment areas in the same alignment unit are arranged at equal intervals.
Further, the ratio of the first length to the second length is 3: 1-30: 1.
further, the area of each alignment region is 0.2-3 μm 2 。
Further, the first direction is perpendicular to the second direction.
Further, H 1 ：H 2 ≥3。
Further, adjacent alignment units are disposed at equal intervals.
According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional memory, including the steps of: providing a substrate, forming a stacking structure on the substrate, wherein the stacking structure comprises a core storage area, a step area and a cutting channel area, the core storage area comprises a connected storage unit and a first contact point, the first contact point is positioned on one side of the storage unit far away from the substrate, the step area comprises a connected step structure and a second contact point, and the second contact point is positioned on one side of the step structure far away from the substrate; covering an insulating layer on the stacked structure, and providing the mask plate, wherein the mask plate comprises a main body pattern and an alignment pattern; etching the insulating layer through the mask plate to form a plurality of contact holes communicated with the first contact point and/or the second contact point in the insulating layer, and simultaneously forming alignment holes in the cutting channel area, wherein a main pattern in the mask plate is used for forming the contact holes, and an alignment pattern in the mask plate is used for forming the alignment holes; an interconnection layer is formed in the contact hole in contact with the first contact point, and an alignment mark is formed in the alignment hole in contact with the second contact point.
The technical proposal of the invention provides a mask plate, which comprises a main body pattern and an alignment pattern, and is used for passing through an exposure light source, and is characterized in that the alignment pattern comprises a plurality of alignment units, the alignment units are arranged at intervals along a first direction, and the minimum distance between adjacent alignment units is H 1 Each alignment unit consists of a plurality of alignment areas which are arranged at intervals along the second direction, and adjacent alignment areasThe minimum spacing between domains is H 2 ，H 1 Greater than H 2 Each alignment region has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length being greater than 1, and an included angle is formed between the first direction and the second direction. Because each alignment unit is composed of a plurality of alignment areas which are arranged at intervals along the second direction, each alignment area has a first length in the first direction and a second length in the second direction, and the ratio of the first length to the second length is greater than 1, on the premise of alignment patterns with the same size, the alignment areas which are positioned in the same row in the alignment unit in the traditional mask plate can be communicated, and therefore, by expanding the size of the alignment areas, the alignment holes formed by the mask plate can be ensured to be filled with enough conductive materials, alignment signals in the subsequent photoetching process are ensured, and the alignment effect is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention. In the drawings:
FIG. 1 is a schematic top view of an alignment pattern provided in an embodiment of the present application;
FIG. 2 shows a schematic top view of the area A of the alignment pattern shown in FIG. 1;
FIG. 3 illustrates a schematic top view of another alignment pattern provided in an embodiment of the present application;
fig. 4 shows a schematic top view of the region a in the alignment pattern shown in fig. 3.
Wherein the above figures include the following reference numerals:
100. an alignment unit; 110. an alignment region; 120. a first light shielding region; 130. and a second light shielding region.
Detailed Description
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, in the prior art, the SADP process is generally used to form the contact hole, where the SADP process has a high requirement on alignment, in order to obtain a better alignment effect, a mask plate used in the photolithography process may divide an alignment pattern (8 um or 8.8 um) during design, however, the alignment pattern is generally divided into a small hole array with a smaller size, which results in less filling of conductive material, thereby affecting an alignment signal of a mask plate used for a conductive layer to be formed subsequently, and further resulting in poor alignment effect or even wafer reject phenomenon.
The present inventors studied the above problems and have proposed a mask plate, as shown in fig. 1 to 4, an alignment pattern includes a plurality of alignment units 100, the alignment units 100 along a first directionIs arranged at intervals in the direction, the minimum distance between the adjacent alignment units 100 is H 1 Each alignment unit 100 is composed of a plurality of alignment regions 110 arranged at intervals along the second direction, and the minimum spacing between adjacent alignment regions 110 is H 2 ，H 1 Greater than H 2 Each alignment region 110 has a first length in a first direction and a second length in a second direction, the ratio of the first length to the second length being greater than 1, and an included angle is formed between the first direction and the second direction.
On the premise of alignment patterns with the same size, the alignment areas which are positioned in the same row in the alignment unit in the traditional mask plate can be communicated, so that the alignment holes formed by the mask plate can be ensured to be filled with enough conductive materials by expanding the size of the alignment areas, alignment signals in the subsequent photoetching process are ensured, and the alignment effect is improved.
In the mask plate of the present invention, the adjacent alignment units 100 may be spaced apart by the first light shielding regions 120, and the adjacent alignment regions 110 in the same alignment unit 100 may be spaced apart by the second light shielding regions 130, where the first light shielding regions 120 are in communication with the second light shielding regions 130, as shown in fig. 1, 2 and 4. The first light shielding region 120 and the second light shielding region 130 are used to prevent light from passing through during an exposure process of a photolithography process.
In order to further improve the alignment signal, in the mask plate of the present invention, the minimum distance between the adjacent alignment areas 110 is H 2 Each alignment region 110 has a second length in a second direction, preferably the second length is equal to H 2 The ratio is 1:1 to 4:1.
in the above mask plate of the present invention, it is preferable that the adjacent alignment areas 110 in the same alignment unit 100 are disposed at equal intervals. The equally spaced alignment areas 110 can simplify the manufacturing process of the mask, and the equally spaced alignment areas 110 are beneficial to receiving alignment signals after forming alignment marks.
In a preferred embodiment, the alignment unit is rectangular, more preferably, the alignment areas are also rectangular, and the alignment areas are arranged in parallel, as shown in fig. 1 to 4. The adoption of the preferred implementation mode is convenient for layout design and process manufacture, and a person skilled in the art can reasonably select the aspect ratio of the alignment unit according to actual requirements.
In the mask plate of the present invention, each alignment region 110 has a first length in a first direction and a second length in a second direction, and in order to further improve the alignment signal, preferably, a ratio of the first length to the second length is 3: 1-30: 1, a step of; and, preferably, the area of each alignment region 110 is 0.2 to 3 μm 2 。
In order to facilitate layout design and process fabrication of the mask, in a preferred embodiment, the first direction is perpendicular to the second direction, as shown in fig. 1 to 4.
In order to further improve the alignment signal, in the mask plate of the present invention, the minimum distance between the adjacent alignment units 100 is H 1 The minimum spacing between adjacent alignment areas 110 is H 2 Preferably H 1 ：H 2 ≥3。
In the above mask plate of the present invention, it is preferable that the adjacent alignment units 100 are disposed at equal intervals. The equidistant alignment units 100 can simplify the manufacturing process of the mask plate, and the equidistant alignment units 100 are beneficial to receiving alignment signals after forming alignment marks.
In one embodiment of the present invention, as shown in fig. 1 and 2, a mask is provided, which includes a plurality of alignment units 100 and first light shielding regions 120 alternately arranged along a first direction, the alignment units 100 are equally spaced apart, each alignment unit 100 includes a plurality of alignment regions 110 and second light shielding regions 130 alternately arranged along a second direction, the alignment regions 110 are equally spaced apart, the first direction is perpendicular to the second direction, the alignment units 100 and the alignment regions 110 are rectangular, and a space between adjacent alignment units 100 is H 1 Is 2-3 μm, and the interval between adjacent alignment areas 110 is H 2 The alignment region 110 has a first length of 2 to 3 μm and a second length of 0.1 to 1 μm, which is 0.1 to 0.4 μm.
In another embodiment of the present invention, as shown in fig. 3 and 4, a mask is provided, which includes a plurality of alignment units 100 and first light shielding regions 120 alternately spaced apart along a first direction, the alignment units 100 are equally spaced apart, each alignment unit 100 includes a plurality of alignment regions 110 and second light shielding regions 130 alternately arranged along a second direction, the alignment regions 110 are equally spaced apart, the first direction is perpendicular to the second direction, the alignment units 100 and the alignment regions 110 are rectangular, and a space between adjacent alignment units 100 is H 1 1-2 μm, the spacing between adjacent alignment areas 110 is H 2 The alignment region 110 has a first length of 0.6 to 1 μm and a second length of 0.2 to 0.5 μm of 0.1 to 0.3 μm.
In another embodiment of the present invention, a mask is provided, the mask includes a plurality of alignment units 100 and first light shielding regions 120 alternately arranged along a first direction, the alignment units 100 are equally spaced apart, each alignment unit 100 includes a plurality of alignment regions 110 and second light shielding regions 130 alternately arranged along a second direction, the alignment regions 110 are equally spaced apart, the first direction is perpendicular to the second direction, the alignment units 100 and the alignment regions 110 are rectangular, and a space between adjacent alignment units 100 is H 1 0.3-1 μm, the spacing between adjacent alignment areas 110 is H 2 The alignment region 110 has a first length of 1 to 2 μm and a second length of 0.2 to 0.5 μm, which is 0.1 to 0.3 μm.
According to another aspect of the present invention, there is also provided a method for manufacturing a three-dimensional memory, including the steps of: providing a substrate, forming a stacked structure on the substrate, wherein the stacked structure comprises a core storage area, a step area and a cutting channel area, the core storage area comprises a storage unit and a first contact point, the first contact point is positioned on one side of the storage unit far away from the substrate and connected with the storage unit, the step area comprises a step structure and a second contact point, and the second contact point is positioned on one side of the step structure far away from the substrate and connected with the step structure; covering an insulating layer on the stacked structure, and providing the mask plate, wherein the mask plate comprises a main body pattern and an alignment pattern; etching the insulating layer through the mask plate to form a plurality of contact holes communicated with the first contact point and/or the second contact point in the insulating layer, and simultaneously forming alignment holes in the cutting channel area, wherein a main pattern in the mask plate is used for forming the contact holes, and an alignment pattern in the mask plate is used for forming the alignment holes; an interconnection layer is formed in the contact hole in contact with the first contact point, and an alignment mark is formed in the alignment hole in contact with the second contact point.
The stacked structure may include a gate structure and an inter-gate dielectric layer, the gate structure and the inter-gate dielectric layer being alternately stacked in a direction away from the substrate; etching the gate structure and the dielectric layer between the gates to form a step structure at one end of the stacked structure; an insulating dielectric material is deposited on the substrate to form an insulating layer, and the contact holes are located in the insulating dielectric layer and penetrate to a first contact point connected with the memory cells and/or a second contact point connected with the step structure.
The alignment mark can be used for aligning a mask plate used in a subsequent bonding part forming process, specifically, the mask plate for etching the step region is a first mask plate, the first mask plate comprises a first main body pattern and a first alignment pattern, and after the step of forming the interconnection layer, the manufacturing method of the invention can further comprise the following steps: providing a second mask plate, wherein the second mask plate is provided with a second alignment pattern corresponding to the alignment mark, aligning the second alignment pattern with the alignment mark, and forming a bonding groove communicated with the interconnection layer through the second mask plate; a first bonding portion is formed in the bonding groove.
The fabrication method of the present invention may further include a step of bonding the memory array to the CMOS circuit after the step of forming the first bonding portion, and in particular, the fabrication method of the present invention may further include the steps of: providing a second substrate with a CMOS circuit, and forming a second bonding part connected with the CMOS circuit; and bonding the first bonding part and the second bonding part.
From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:
because each alignment unit is composed of a plurality of alignment areas which are arranged at intervals along the second direction, each alignment area has a first length in the first direction and a second length in the second direction, and the ratio of the first length to the second length is greater than 1, on the premise of alignment patterns with the same size, the alignment areas which are positioned in the same row in the alignment unit in the traditional mask plate can be communicated, and therefore, by expanding the size of the alignment areas, the alignment holes formed by the mask plate can be ensured to be filled with enough conductive materials, alignment signals in the subsequent photoetching process are ensured, and the alignment effect is improved.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A manufacturing method of a three-dimensional memory adopts a mask plate, which comprises an alignment pattern for passing through an exposure light source, and is characterized in that the alignment pattern comprises a plurality of alignment units (100), the alignment units (100) are arranged at intervals along a first direction, and the minimum distance between every two adjacent alignment units (100) is H 1 Each alignment unit (100) is composed of a plurality of alignment areas (110) which are arranged at intervals along the second direction, and the minimum spacing between the adjacent alignment areas (110) is H 2 ，H 1 Greater than H 2 Each alignment region (110) has a first length in the first direction and a second length in the second direction, the ratio of the first length to the second length being greater than 1, the first direction and the second direction having an included angle therebetween;
the manufacturing method comprises the following steps:
providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a core storage area, a step area and a cutting channel area, the core storage area comprises a connected storage unit and a first contact point, the first contact point is positioned on one side of the storage unit far away from the substrate, the step area comprises a connected step structure and a second contact point, and the second contact point is positioned on one side of the step structure far away from the substrate;
covering an insulating layer on the stacked structure, and providing the mask plate, wherein the mask plate comprises a main body pattern and the alignment pattern;
etching the insulating layer through the mask plate to form a plurality of contact holes communicated with the first contact points and/or the second contact points in the insulating layer, and forming alignment holes in the cutting channel area at the same time, wherein a main pattern in the mask plate is used for forming the contact holes, and an alignment pattern in the mask plate is used for forming the alignment holes;
and forming an interconnection layer in the contact hole, which is in contact with the first contact point, and forming an alignment mark in the alignment hole, which is in contact with the second contact point.
2. The manufacturing method according to claim 1, wherein adjacent alignment units (100) are arranged at intervals by first light shielding areas (120), adjacent alignment areas (110) in the same alignment unit (100) are arranged at intervals by second light shielding areas (130), and the first light shielding areas (120) are communicated with the second light shielding areas (130).
3. The method of claim 1, wherein the second length is equal to the H 2 The ratio is 1: 1-4: 1.
4. the method of manufacturing according to claim 1, wherein adjacent alignment areas (110) in the same alignment unit (100) are arranged at equal intervals.
5. The method of claim 1, wherein the ratio of the first length to the second length is 3: 1-30: 1.
6. the method according to claim 1 or 5, wherein each of the alignment regions (110) has an area of 0.2-3 μm 2 。
7. The method of any one of claims 1 to 5, wherein the first direction is perpendicular to the second direction.
8. The method according to any one of claims 1 to 5, wherein H 1 ：H 2 ≥3。
9. The method of manufacturing according to any one of claims 1 to 5, wherein adjacent alignment units (100) are arranged at equal intervals.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011282268.0A CN112394611B (en) | 2020-11-16 | 2020-11-16 | Mask plate and manufacturing method of three-dimensional memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011282268.0A CN112394611B (en) | 2020-11-16 | 2020-11-16 | Mask plate and manufacturing method of three-dimensional memory |
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| CN112394611B true CN112394611B (en) | 2024-02-23 |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000231185A (en) * | 1999-02-12 | 2000-08-22 | Asahi Kasei Microsystems Kk | Reticle and its positioning method |
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| JP2009251455A (en) * | 2008-04-09 | 2009-10-29 | Panasonic Corp | Alignment mark and alignment method |
| CN109901359A (en) * | 2017-12-11 | 2019-06-18 | 长鑫存储技术有限公司 | For the alignment patterns of exposure mask, exposure mask and wafer |
| CN110488578A (en) * | 2019-09-20 | 2019-11-22 | 上海华力微电子有限公司 | The manufacturing method and mask plate of mask plate |
| CN111443570A (en) * | 2020-04-14 | 2020-07-24 | 长江存储科技有限责任公司 | Photomask, semiconductor device and method for designing photomask |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002260997A (en) * | 2000-12-26 | 2002-09-13 | Nikon Corp | Alignment mark |
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- 2020-11-16 CN CN202011282268.0A patent/CN112394611B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000231185A (en) * | 1999-02-12 | 2000-08-22 | Asahi Kasei Microsystems Kk | Reticle and its positioning method |
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| JP2009251455A (en) * | 2008-04-09 | 2009-10-29 | Panasonic Corp | Alignment mark and alignment method |
| CN109901359A (en) * | 2017-12-11 | 2019-06-18 | 长鑫存储技术有限公司 | For the alignment patterns of exposure mask, exposure mask and wafer |
| CN110488578A (en) * | 2019-09-20 | 2019-11-22 | 上海华力微电子有限公司 | The manufacturing method and mask plate of mask plate |
| CN111443570A (en) * | 2020-04-14 | 2020-07-24 | 长江存储科技有限责任公司 | Photomask, semiconductor device and method for designing photomask |
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| CN112394611A (en) | 2021-02-23 |
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