CN112394611A - Mask plate and manufacturing method of three-dimensional memory - Google Patents
Mask plate and manufacturing method of three-dimensional memory Download PDFInfo
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- CN112394611A CN112394611A CN202011282268.0A CN202011282268A CN112394611A CN 112394611 A CN112394611 A CN 112394611A CN 202011282268 A CN202011282268 A CN 202011282268A CN 112394611 A CN112394611 A CN 112394611A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 15
- 238000003860 storage Methods 0.000 claims description 14
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 9
- 239000004020 conductor Substances 0.000 abstract description 6
- 238000001259 photo etching Methods 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a mask plate and a manufacturing method of a three-dimensional memory. The alignment pattern in the mask plate comprises a plurality of alignment units which are arranged at intervals along a first direction, and the minimum distance between every two adjacent alignment units is H1Each alignment unit is composed of a plurality of alignment regions arranged at intervals along the second direction, and the minimum distance between adjacent alignment regions is H2，H1Greater than H2Each alignment area has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length is greater than 1, and the first direction and the second direction areAn included angle is formed between the two directions. On the premise of aligning patterns with the same size, the aligning areas in the same line in the aligning unit in the traditional mask plate can be communicated, and the size of the aligning areas is expanded, so that the aligning holes formed by the mask plate can be filled with enough conductive materials, aligning signals in the subsequent photoetching process are ensured, and the aligning effect is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a mask plate and a manufacturing method of a three-dimensional memory.
Background
In the prior art, a Flash Memory (Flash Memory) has a main function of maintaining stored information for a long time without power up, and has the advantages of high integration level, high access speed, easy erasing and rewriting and the like, so that the Flash Memory is widely applied to electronic products. In order to further increase the Bit Density (Bit Density) of the flash memory and reduce the Bit Cost (Bit Cost), a three-dimensional flash memory (3D NAND) is further proposed.
In the 3D NAND flash memory structure, a stacked 3DNAND memory structure is realized by vertically stacking a plurality of layers of data storage units. A stacked structure in a 3D NAND memory array typically includes a core array region and a step region having a step structure and conductive contacts connected to the step structure distributed therein, and the memory array is typically bonded to peripheral circuitry by covering the step structure with a dielectric layer having contact holes (TSVs) and forming an interconnect layer in the contact holes that is connected to the conductive contacts.
In the prior art, the contact hole is usually formed by using an SADP process, which has a high requirement on alignment, and in order to obtain a better alignment effect, a mask used in a photolithography process is designed by dividing an alignment pattern (8um or 8.8um), however, the alignment pattern is usually divided into an array of small holes with a small size, so that the conductive material is filled less, and an alignment signal of the mask used for forming a conductive layer subsequently is affected, and thus the alignment effect is poor, and even a wafer reject (wafer alignment failure) phenomenon occurs.
Disclosure of Invention
The invention mainly aims to provide a mask plate and a manufacturing method of a three-dimensional memory, and aims to solve the problem that alignment patterns of the mask plate in the prior art are easy to cause poor alignment signals of the subsequently adopted mask plate.
To achieve the above object, according to the present inventionIn one aspect of the present invention, there is provided a mask including an alignment pattern for passing an exposure light source, the alignment pattern including a plurality of alignment units, the alignment units being spaced apart in a first direction, a minimum distance between adjacent alignment units being H1Each alignment unit is composed of a plurality of alignment regions arranged at intervals along the second direction, and the minimum distance between adjacent alignment regions is H2，H1Greater than H2Each alignment area has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length is greater than 1, and the first direction and the second direction have an included angle therebetween.
Furthermore, adjacent alignment units are arranged at intervals through first shading areas, adjacent alignment areas in the same alignment unit are arranged at intervals through second shading areas, and the first shading areas are communicated with the second shading areas.
Further, the second length is equal to H2The ratio of 1: 1-4: 1.
further, adjacent alignment regions in the same alignment unit are arranged at equal intervals.
Further, the ratio of the first length to the second length is 3: 1-30: 1.
further, the area of each alignment region is 0.2 to 3 μm2。
Further, the first direction is perpendicular to the second direction.
Further, H1：H2≥3。
Further, adjacent alignment units are disposed at equal intervals.
According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional memory, including the steps of: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a core storage area, a step area and a cutting path area, the core storage area comprises a connected storage unit and a first contact point, the first contact point is positioned on one side of the storage unit, which is far away from the substrate, the step area comprises a connected step structure and a second contact point, and the second contact point is positioned on one side of the step structure, which is far away from the substrate; covering an insulating layer on the stacked structure, and providing the mask plate, wherein the mask plate comprises a main body pattern and an alignment pattern; etching the insulating layer through a mask plate to form a plurality of contact holes communicated with the first contact points and/or the second contact points in the insulating layer and form alignment holes in the cutting channel area, wherein main body patterns in the mask plate are used for forming the contact holes, and alignment patterns in the mask plate are used for forming the alignment holes; an interconnection layer in contact with the first contact point is formed in the contact hole, and an alignment mark in contact with the second contact point is formed in the alignment hole.
The technical scheme of the invention is applied to provide a mask plate which comprises a main body graph and an alignment graph used for passing through an exposure light source and is characterized in that the alignment graph comprises a plurality of alignment units, the alignment units are arranged at intervals along a first direction, and the minimum distance between every two adjacent alignment units is H1Each alignment unit is composed of a plurality of alignment regions arranged at intervals along the second direction, and the minimum distance between adjacent alignment regions is H2，H1Greater than H2Each alignment area has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length is greater than 1, and the first direction and the second direction have an included angle therebetween. Because each alignment unit is composed of a plurality of alignment areas arranged at intervals along the second direction, each alignment area has a first length in the first direction and a second length in the second direction, and the ratio of the first length to the second length is greater than 1, on the premise of aligning patterns with the same size, the alignment areas in the same row in the alignment units in the traditional mask plate can be communicated, so that the alignment holes formed by the mask plate can be ensured to be filled with enough conductive materials by expanding the size of the alignment areas in the alignment areas, alignment signals in the subsequent photoetching process are ensured, and the alignment effect is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating a top view of an alignment pattern provided in an embodiment of the present application;
FIG. 2 is a schematic top view of the region A in the alignment pattern shown in FIG. 1;
FIG. 3 is a schematic top view of another alignment pattern provided in an embodiment of the present application;
fig. 4 is a schematic top view illustrating a structure of a region a in the alignment pattern shown in fig. 3.
Wherein the figures include the following reference numerals:
100. an alignment unit; 110. an alignment area; 120. a first light-shielding region; 130. a second light-shielding region.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged under appropriate circumstances in order to facilitate the description of the embodiments of the invention herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, the contact hole is usually formed by using an SADP process in the prior art, which has a high requirement on alignment, and in order to obtain a better alignment effect, a mask used in a photolithography process is designed to split an alignment pattern (8um or 8.8um), however, the alignment pattern is usually split into an array of small holes with a smaller size, which results in less filling of a conductive material, thereby affecting an alignment signal of the mask used for forming a conductive layer subsequently, and further resulting in poor alignment effect, even wafer reject.
The inventors of the present invention have studied the above problems and proposed a mask plate, as shown in fig. 1 to 4, in which an alignment pattern includes a plurality of alignment units 100, the alignment units 100 are spaced apart in a first direction, and a minimum pitch between adjacent alignment units 100 is H1Each alignment unit 100 is composed of a plurality of alignment regions 110 spaced apart in the second direction, and a minimum distance between adjacent alignment regions 110 is H2，H1Greater than H2Each alignment area 110 has a first length in a first direction and a second length in a second direction, a ratio of the first length to the second length is greater than 1, and the first direction and the second direction have an angle therebetween.
On the premise of aligning patterns with the same size, the aligning areas in the same line in the aligning unit in the traditional mask plate can be communicated, so that the size of the aligning areas is expanded, the aligning holes formed by the mask plate can be filled with enough conductive materials, aligning signals in the subsequent photoetching process are guaranteed, and the aligning effect is improved.
In the mask of the present invention, adjacent alignment units 100 may be spaced apart by a first light-shielding region 120, adjacent alignment regions 110 in the same alignment unit 100 may be spaced apart by a second light-shielding region 130, and the first light-shielding region 120 is communicated with the second light-shielding region 130, as shown in fig. 1, 2 and 4. The first light-shielding region 120 and the second light-shielding region 130 are used to prevent light from passing through during an exposure process of a photolithography process.
In order to further improve the alignment signal, in the mask of the present invention, the minimum distance between adjacent alignment regions 110 is H2Each alignment area 110 has a second length in a second direction, preferably the second length and H2The ratio of 1: 1-4: 1.
in the mask plate of the present invention, it is preferable that adjacent alignment regions 110 in the same alignment unit 100 are disposed at equal intervals. The alignment regions 110 disposed at equal intervals can make the manufacturing process of the mask plate simpler, and the alignment regions 110 disposed at equal intervals are beneficial to receiving alignment signals after alignment marks are formed.
In a preferred embodiment, the alignment unit is rectangular, and more preferably, the alignment regions are also rectangular, and the alignment regions are arranged in parallel, as shown in fig. 1 to 4. The adoption of the preferred embodiment facilitates layout design and process manufacturing, and technicians in the field can reasonably select the length-width ratio of the alignment unit according to actual requirements.
In the mask of the present invention, each alignment region 110 has a first length in a first direction and a second length in a second direction, and in order to further improve an alignment signal, it is preferable that a ratio of the first length to the second length is 3: 1-30: 1; also, preferably, each of the alignment regions 110 has an area of 0.2 to 3 μm2。
In order to facilitate layout design and process manufacturing of the mask, in a preferred embodiment, the first direction is perpendicular to the second direction, as shown in fig. 1 to 4.
In order to further improve the alignment signal, in the mask of the present invention, the minimum distance between adjacent alignment cells 100 is H1The minimum distance between adjacent alignment regions 110 is H2Preferably, H1：H2≥3。
In the mask of the present invention, it is preferable that adjacent alignment units 100 are disposed at equal intervals. The alignment units 100 arranged at equal intervals can make the manufacturing process of the mask plate simpler, and the alignment units 100 arranged at equal intervals are beneficial to receiving alignment signals after alignment marks are formed.
In an embodiment of the present invention, as shown in fig. 1 and 2, a mask is provided, which includes a plurality of alignment units 100 and first light-shielding regions 120 alternately spaced along a first direction, the alignment units 100 are equally spaced, each alignment unit 100 includes a plurality of alignment regions 110 and second light-shielding regions 130 alternately disposed along a second direction, the alignment regions 110 are equally spaced, the first direction is perpendicular to the second direction, the alignment units 100 and the alignment regions 110 are rectangular, and a distance between adjacent alignment units 100 is H12-3 μm, and the interval between adjacent alignment regions 110 is H20.1 to 0.4 μm, a first length of the alignment region 110 is 2 to 3 μm, and a second length is 0.1 to 1 μm.
In another embodiment of the present invention, as shown in fig. 3 and 4, a mask is provided, which includes a plurality of alignment units 100 and first light-shielding regions 120 alternately spaced along a first direction, the alignment units 100 are equally spaced, each alignment unit 100 includes a plurality of alignment regions 110 and second light-shielding regions 130 alternately disposed along a second direction, the alignment regions 110 are equally spaced, the first direction is perpendicular to the second direction, the alignment units 100 and the alignment regions 110 are rectangular, and a distance between adjacent alignment units 100 is H11-2 μm, and the interval between adjacent alignment regions 110 is H20.1 to 0.3 μm, a first length of the alignment region 110 is 0.6 to 1 μm, and a second length is 0.2 to 0.5 μm.
In another embodiment of the present invention, a mask is provided, which includes a plurality of alignment units 100 and first light-shielding regions 120 alternately spaced along a first direction, the alignment units 100 are equally spaced, each alignment unit 100 includes a plurality of alignment regions 110 and second light-shielding regions 130 alternately disposed along a second direction, the alignment regions 110 are equally spaced, the first direction is perpendicular to the second direction, the alignment units 100 and the alignment regions 110 are rectangular, and a distance between adjacent alignment units 100 is equal toH10.3 to 1 μm, and a distance H between adjacent alignment regions 11020.1 to 0.3 μm, a first length of the alignment region 110 is 1 to 2 μm, and a second length is 0.2 to 0.5 μm.
According to another aspect of the present invention, there is also provided a method for manufacturing a three-dimensional memory, including the steps of: providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a core storage area, a step area and a cutting channel area, the core storage area comprises a storage unit and a first contact point, the first contact point is positioned on one side of the storage unit, which is far away from the substrate, and is connected with the storage unit, the step area comprises a step structure and a second contact point, and the second contact point is positioned on one side of the step structure, which is far away from the substrate, and is connected with the step structure; covering an insulating layer on the stacked structure, and providing the mask plate, wherein the mask plate comprises a main body pattern and an alignment pattern; etching the insulating layer through a mask plate to form a plurality of contact holes communicated with the first contact points and/or the second contact points in the insulating layer and form alignment holes in the cutting channel area, wherein main body patterns in the mask plate are used for forming the contact holes, and alignment patterns in the mask plate are used for forming the alignment holes; an interconnection layer in contact with the first contact point is formed in the contact hole, and an alignment mark in contact with the second contact point is formed in the alignment hole.
The stacked structure can comprise a grid structure and inter-grid dielectric layers, wherein the grid structure and the inter-grid dielectric layers are alternately stacked along the direction far away from the substrate; etching the grid structure and the dielectric layer between the grids to form a step structure at one end of the stacked structure; and depositing an insulating medium material on the substrate to form an insulating layer, wherein the contact hole is positioned in the insulating medium layer and penetrates through to a first contact point connected with the storage unit and/or a second contact point connected with the step structure.
The alignment mark may be used for alignment of a mask used in a process of subsequently forming a bonding portion, specifically, the mask for etching the step region is a first mask, the first mask includes a first main body pattern and a first alignment pattern, and after the step of forming the interconnection layer, the manufacturing method of the present invention may further include the steps of: providing a second mask plate, wherein the second mask plate is provided with a second alignment pattern corresponding to the alignment mark, aligning the second alignment pattern with the alignment mark, and forming a bonding groove communicated with the interconnection layer through the second mask plate; a first bonding portion is formed in the bonding groove.
After the step of forming the first bonding portion, the manufacturing method of the present invention may further include a step of bonding the memory array and the CMOS circuit, and specifically, the manufacturing method of the present invention may further include: providing a second substrate with a CMOS circuit, and forming a second bonding part connected with the CMOS circuit; and bonding the first bonding portion and the second bonding portion.
From the above description, it can be seen that the above-described embodiments of the present invention achieve the following technical effects:
because each alignment unit is composed of a plurality of alignment areas arranged at intervals along the second direction, each alignment area has a first length in the first direction and a second length in the second direction, and the ratio of the first length to the second length is greater than 1, on the premise of aligning patterns with the same size, the alignment areas in the same row in the alignment units in the traditional mask plate can be communicated, so that the alignment holes formed by the mask plate can be ensured to be filled with enough conductive materials by expanding the size of the alignment areas in the alignment areas, alignment signals in the subsequent photoetching process are ensured, and the alignment effect is improved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A mask plate comprises an alignment pattern used for passing through an exposure light source, and is characterized in that the alignment pattern comprises a plurality of alignment units (100), the alignment units (100) are arranged at intervals along a first direction, and the minimum distance between every two adjacent alignment units (100)Is H1Each alignment unit (100) is composed of a plurality of alignment regions (110) arranged at intervals along the second direction, and the minimum distance between the adjacent alignment regions (110) is H2，H1Greater than H2Each alignment area (110) has a first length in the first direction and a second length in the second direction, a ratio of the first length to the second length being greater than 1, the first direction and the second direction having an included angle therebetween.
2. A mask according to claim 1, wherein adjacent alignment cells (100) are spaced apart by a first light-shielding region (120), and adjacent alignment regions (110) in the same alignment cell (100) are spaced apart by a second light-shielding region (130), the first light-shielding region (120) being in communication with the second light-shielding region (130).
3. A mask according to claim 1 or 2, wherein the second length is equal to the H2The ratio of 1: 1-4: 1.
4. a mask according to claim 1, wherein adjacent alignment regions (110) in the same alignment unit (100) are arranged at equal intervals.
5. A mask according to claim 1, wherein the ratio of the first length to the second length is 3: 1-30: 1.
6. a mask according to claim 1 or 5, wherein the area of each alignment region (110) is 0.2-3 μm2。
7. A mask according to any one of claims 1 to 6, wherein the first direction is perpendicular to the second direction.
8. According to any one of claims 1 to 6The mask plate is characterized in that H1：H2≥3。
9. A mask according to any one of claims 1 to 6, wherein adjacent alignment units (100) are arranged at equal intervals.
10. A method for manufacturing a three-dimensional memory is characterized by comprising the following steps:
providing a substrate, and forming a stacked structure on the substrate, wherein the stacked structure comprises a core storage area, a step area and a cutting path area, the core storage area comprises a connected storage unit and a first contact point, the first contact point is positioned on one side of the storage unit far away from the substrate, the step area comprises a connected step structure and a second contact point, and the second contact point is positioned on one side of the step structure far away from the substrate;
covering an insulating layer on the stacked structure and providing a mask as claimed in any one of claims 1 to 9, the mask including a body pattern and the alignment pattern;
etching the insulating layer through the mask plate to form a plurality of contact holes communicated with the first contact points and/or the second contact points in the insulating layer and form alignment holes in the cutting path region, wherein main patterns in the mask plate are used for forming the contact holes, and alignment patterns in the mask plate are used for forming the alignment holes;
forming an interconnection layer in contact with the first contact point in the contact hole, and forming an alignment mark in contact with the second contact point in the alignment hole.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011282268.0A CN112394611B (en) | 2020-11-16 | 2020-11-16 | Mask plate and manufacturing method of three-dimensional memory |
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| CN202011282268.0A CN112394611B (en) | 2020-11-16 | 2020-11-16 | Mask plate and manufacturing method of three-dimensional memory |
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| JP2000231185A (en) * | 1999-02-12 | 2000-08-22 | Asahi Kasei Microsystems Kk | Reticle and its positioning method |
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| US20020079467A1 (en) * | 2000-12-26 | 2002-06-27 | Nikon Corporation | Alignment-mark patterns defined on a stencil reticle and detectable, after lithographic transfer to a substrate, using an optical-based detector |
| JP2009251455A (en) * | 2008-04-09 | 2009-10-29 | Panasonic Corp | Alignment mark and alignment method |
| CN109901359A (en) * | 2017-12-11 | 2019-06-18 | 长鑫存储技术有限公司 | For the alignment patterns of exposure mask, exposure mask and wafer |
| CN110488578A (en) * | 2019-09-20 | 2019-11-22 | 上海华力微电子有限公司 | The manufacturing method and mask plate of mask plate |
| CN111443570A (en) * | 2020-04-14 | 2020-07-24 | 长江存储科技有限责任公司 | Photomask, semiconductor device and method for designing photomask |
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2020
- 2020-11-16 CN CN202011282268.0A patent/CN112394611B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000231185A (en) * | 1999-02-12 | 2000-08-22 | Asahi Kasei Microsystems Kk | Reticle and its positioning method |
| CN1329357A (en) * | 2000-06-08 | 2002-01-02 | 株式会社东芝 | Aligning method, alignment checking method and photomask |
| US20020079467A1 (en) * | 2000-12-26 | 2002-06-27 | Nikon Corporation | Alignment-mark patterns defined on a stencil reticle and detectable, after lithographic transfer to a substrate, using an optical-based detector |
| JP2009251455A (en) * | 2008-04-09 | 2009-10-29 | Panasonic Corp | Alignment mark and alignment method |
| CN109901359A (en) * | 2017-12-11 | 2019-06-18 | 长鑫存储技术有限公司 | For the alignment patterns of exposure mask, exposure mask and wafer |
| CN110488578A (en) * | 2019-09-20 | 2019-11-22 | 上海华力微电子有限公司 | The manufacturing method and mask plate of mask plate |
| CN111443570A (en) * | 2020-04-14 | 2020-07-24 | 长江存储科技有限责任公司 | Photomask, semiconductor device and method for designing photomask |
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