KR101099513B1 - Method of forming a contact plug in flash memory device - Google Patents

Method of forming a contact plug in flash memory device Download PDF

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KR101099513B1
KR101099513B1 KR1020050058013A KR20050058013A KR101099513B1 KR 101099513 B1 KR101099513 B1 KR 101099513B1 KR 1020050058013 A KR1020050058013 A KR 1020050058013A KR 20050058013 A KR20050058013 A KR 20050058013A KR 101099513 B1 KR101099513 B1 KR 101099513B1
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contact plug
forming
interlayer insulating
contact
memory device
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KR1020050058013A
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Korean (ko)
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KR20070002464A (en
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김충배
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 플래쉬 메모리소자의 콘택플러그 형성방법에 관한 것으로, 본 발명의 사상은 일렬로 나열된 복수 개의 도전영역이 구비된 반도체 기판을 제공하는 단계, 상기 반도체 기판 상에 제1 층간 절연막을 형성한 후 상기 제1 층간 절연막에 관통 형성되어, 제1 영역에 형성된 상기 도전영역을 노출하는 제1 콘택플러그를 형성하는 단계, 상기 제1 콘택플러그 상에 도전물질인 패드막을 형성하는 단계 및 상기 결과물 상에 제2 층간절연막을 형성한 후 상기 제2 층간절연막에 관통 형성되어, 상기 패드막과 접촉하는 제2 콘택플러그를 형성하면서 동시에 상기 제2 및 제1 층간절연막에 관통 형성되어, 상기 제1 영역과 이웃한 제2 영역에 형성된 상기 도전영역을 노출하는 제3 콘택플러그를 형성하는 단계를 포함한다.The present invention relates to a method of forming a contact plug of a flash memory device, and an object of the present invention is to provide a semiconductor substrate having a plurality of conductive regions arranged in a line, and after forming a first interlayer insulating layer on the semiconductor substrate. Forming a first contact plug penetrating through the first interlayer insulating layer to expose the conductive region formed in the first region, forming a pad film as a conductive material on the first contact plug, and on the resulting product A second interlayer insulating film is formed through the second interlayer insulating film, and a second contact plug in contact with the pad film is formed and at the same time, the second interlayer insulating film is formed through the second interlayer insulating film. And forming a third contact plug exposing the conductive region formed in the neighboring second region.

콘택플러그 Contact Plug

Description

플래쉬 메모리소자의 콘택플러그 형성방법{Method of forming a contact plug in flash memory device}Method of forming a contact plug in flash memory device

도 1 내지 도 4는 본 발명에 따른 플래쉬 메모리소자의 콘택플러그 형성방법을 설명하기 위한 레이 아웃도들이다. 1 to 4 are layout views illustrating a method for forming a contact plug of a flash memory device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

AC: 활성영역 DSL: DSL용 게이트패턴AC: active area DSL: gate pattern for DSL

14, 20, 22: 드레인 콘택플러그 16: 패드막14, 20, 22: drain contact plug 16: pad film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 플래쉬 메모리소자의 콘택플러그 형성방법에 관한 것이다. The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact plug of a flash memory device.

플래쉬 메모리소자의 제조방법에 있어서, 최근 디자인 룰이 감소됨에 따라 활성영역과 금속배선을 연결시키는 콘택플러그가 형성될 면적이 감소되고 있다. In the method of manufacturing a flash memory device, as the design rule is recently reduced, the area in which a contact plug connecting the active region and the metal wiring is formed is reduced.

또한 일렬로 연결되어 있는 콘택플러그간의 공간이 좁아져 이웃한 콘택플러그는 후속 공정을 거치면서 콘택플러그들간에 단락이 발생될 수 있게 되는 문제가 발생한다. In addition, the space between the contact plugs connected in a row is narrowed, so that the adjacent contact plugs may have a short circuit between the contact plugs during the subsequent process.

따라서 플래쉬 메모리소자의 제조방법에 있어서, 서로 이웃한 콘택 플러그들간에 발생될 수 있는 단락을 방지하기 위한 기술들이 요구되고 있다.Therefore, in the method of manufacturing a flash memory device, a technique for preventing a short circuit that may occur between adjacent contact plugs is required.

상술한 문제점을 해결하기 위한 본 발명의 사상은 서로 이웃한 콘택플러그들간에 발생될 수 있는 단락을 방지하는 플래쉬 메모리소자의 콘택플러그 형성방법을 제공함에 있다.An object of the present invention for solving the above problems is to provide a method for forming a contact plug of a flash memory device which prevents a short circuit that may occur between adjacent contact plugs.

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이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

도 1 내지 도 4는 본 발명에 따른 플래쉬 메모리소자의 콘택플러그 형성방법을 설명하기 위한 레이 아웃도들이다. 1 to 4 are layout views illustrating a method for forming a contact plug of a flash memory device according to the present invention.

도 1을 참조하면, 소자분리영역(F)과 활성영역(AC)으로 구분 정의된 반도체 기판상의 셀영역에는 메모리 셀(미도시) 및 SSL용 게이트 전극 패턴(미도시), DSL용 게이트 전극 패턴(DSL)이 형성된다. Referring to FIG. 1, a cell region on a semiconductor substrate defined as an isolation region F and an active region AC includes a memory cell (not shown), a gate electrode pattern for SSL (not shown), and a gate electrode pattern for DSL. (DSL) is formed.

상기 메모리 셀(MC)에는 터널 산화막용 절연막, 플로팅 게이트 전극용 제1 폴리 실리콘막, ONO막, 콘트롤 게이트 전극용 제2 폴리 실리콘막, 텅스텐 실리사이드막 및 하드마스크용 절연막이 적층 형성되어 있고, 상기 SSL용 게이트 전극 패턴, DSL용 게이트 전극 패턴(DSL), 터널 산화막용 절연막, 제1 폴리 실리콘막, 제2 폴리 실리콘막, 텅스텐 실리사이드막 및 하드마스크용 절연막이 적층 형성되어 있다. An insulating film for a tunnel oxide film, a first polysilicon film for a floating gate electrode, an ONO film, a second polysilicon film for a control gate electrode, a tungsten silicide film, and an insulating film for a hard mask are formed in the memory cell MC. An SSL gate electrode pattern, a DSL gate electrode pattern (DSL), a tunnel oxide film insulating film, a first polysilicon film, a second polysilicon film, a tungsten silicide film, and an insulating film for a hard mask are laminated.

상기 메모리 셀 및 SSL용 게이트 전극 패턴, DSL용 게이트 전극 패턴(DSL)을 이온주입마스크로 이온주입공정을 수행하여, SSL용 게이트전극패턴과 오버랩되는 반도체 기판 내부 및 DSL용 게이트전극 패턴과 오버랩되는 반도체 기판 내부에 접합영역(미도시)들을 형성한다. An ion implantation process is performed on the memory cell, the SSL gate electrode pattern, and the DSL gate electrode pattern (DSL) using an ion implantation mask to overlap the inside of the semiconductor substrate overlapping with the SSL gate electrode pattern and the DSL gate electrode pattern. Bonding regions (not shown) are formed in the semiconductor substrate.

도 2를 참조하면, 상기 DSL용 게이트 전극 패턴(DSL)이 형성된 결과물 전면에 제1 층간 절연막(12)을 형성한다. Referring to FIG. 2, a first interlayer insulating layer 12 is formed on the entire surface of the resultant product on which the DSL gate electrode pattern DSL is formed.

이어서, 상기 DSL용 게이트전극 패턴들(DSL) 사이의 제1 층간 절연막(12) 소정 영역을 패터닝하여, 제1 드레인 콘택홀을 형성한다. 이어서, 상기 드레인 콘택 홀내부에만 도전막이 매립되도록 하여, 제1 드레인 콘택 플러그(14)를 형성한다. Subsequently, a predetermined region of the first interlayer insulating layer 12 between the DSL gate electrode patterns DSL is patterned to form a first drain contact hole. Subsequently, the first drain contact plug 14 is formed by filling the conductive film only in the drain contact hole.

상기 제1 드레인 콘택플러그는 상기 DSL용 게이트전극 패턴들(DSL) 사이에 형성된 접합영역(미도시)을 노출하는 다수 개의 드레인 콘택플러그 중 짝수 번째의 드레인 콘택플러그이다. The first drain contact plug is an even-numbered drain contact plug among a plurality of drain contact plugs exposing a junction region (not shown) formed between the DSL gate electrode patterns DSL.

도 3을 참조하면, 상기 결과물 전면에 패드용 폴리 실리콘막을 형성한 후 패터닝하여, 상기 제1 드레인 콘택플러그(14)가 형성된 활성영역 상의 소정 영역에 패드막(16)을 형성한다.Referring to FIG. 3, a pad polysilicon film is formed on the entire surface of the resultant and then patterned to form a pad film 16 on a predetermined region on an active region in which the first drain contact plug 14 is formed.

상기 패드막(16)은 상기 제1 드레인 콘택플러그(14)와 연결되도록 한다. The pad layer 16 may be connected to the first drain contact plug 14.

도 4를 참조하면, 상기 결과물 전면에 제2 층간 절연막을 형성하고, 상기 DSL용 게이트전극 패턴들(DSL) 사이의 제2 층간 절연막(12) 소정 영역을 패터닝하여, 제2 드레인 콘택홀을 형성한다. 이어서, 상기 드레인 콘택홀 내부에만 도전막이 매립되도록 하여, 상기 패드막(16)과 연결되는 제2 드레인 콘택 플러그(20)를 형성한다. Referring to FIG. 4, a second interlayer insulating layer is formed on the entire surface of the resultant, and a predetermined region of the second interlayer insulating layer 12 between the DSL gate electrode patterns DSL is patterned to form a second drain contact hole. do. Subsequently, a conductive film is embedded only in the drain contact hole, thereby forming a second drain contact plug 20 connected to the pad layer 16.

상기 제2 드레인 콘택플러그(20)는 상기 패드막(16)을 통해, 상기 제1 드레인 콘택플러그(14)와 연결됨으로써, 상기 다수 개의 드레인 콘택플러그 중 짝수 번째의 드레인 콘택플러그의 형성을 완료한다. The second drain contact plug 20 is connected to the first drain contact plug 14 through the pad layer 16 to complete formation of even-numbered drain contact plugs among the plurality of drain contact plugs. .

상기 제2 드레인 콘택플러그(20)가 형성되면서 동시에, 상기 제2 층간 절연막이 형성된 결과물에 상기 DSL용 게이트전극 패턴들(DSL) 사이의 제2 및 제1 층간 절연막(12, 18) 소정 영역을 패터닝하여, 제2 드레인 콘택홀을 형성한다. 이어서, 상기 드레인 콘택홀 내부에만 도전막이 매립되도록 하여, 제3 드레인 콘택 플러그 (22)를 형성한다.At the same time as the second drain contact plug 20 is formed, a predetermined region of the second and first interlayer insulating layers 12 and 18 between the DSL gate electrode patterns DSL is formed on the resultant formed with the second interlayer insulating layer. By patterning, a second drain contact hole is formed. Subsequently, the third drain contact plug 22 is formed by filling the conductive film only in the drain contact hole.

상기 제3 드레인 콘택 플러그(22)는 상기 다수 개의 드레인 콘택플러그 중 홀수 번째의 드레인 콘택플러그이다. The third drain contact plug 22 is an odd-numbered drain contact plug among the plurality of drain contact plugs.

상기 제1 드레인 콘택 플러그(14)와 제3 드레인 콘택플러그(22)는 서로 이웃한 활성영역(AC1과 AC2) 상에 각각 위치하게 되지만, 제2 층간 절연막(18)만큼의 단차를 갖고 있게 되어, 상기 콘택 플러그들간에 단락될 우려는 방지될 수 있다.The first drain contact plug 14 and the third drain contact plug 22 are positioned on the active regions AC1 and AC2 that are adjacent to each other, but have a step equivalent to that of the second interlayer insulating layer 18. The possibility of a short circuit between the contact plugs can be prevented.

또한, 상기 제2 드레인 콘택 플러그(20)와 제3 드레인 콘택플러그(22)는 제2 층간 절연막(18)상에 각각 위치되지만, 서로 지그재그 형상으로 위치되어, 상기 콘택 플러그들간에 단락될 우려는 방지될 수 있다.In addition, although the second drain contact plug 20 and the third drain contact plug 22 are respectively positioned on the second interlayer insulating film 18, they are positioned in a zigzag shape with each other, so that there is a fear of shorting between the contact plugs. Can be prevented.

본 발명에 의하면, 패드막(16)으로 연결된 제1 및 제2 드레인 콘택 플러그(14, 20)를 통해 다수 개의 드레인 콘택플러그 중 짝수 번째의 드레인 콘택플러그를 형성하고, 제3 드레인 콘택 플러그(22)를 통해 다수 개의 드레인 콘택플러그 중 홀수 번째의 드레인 콘택플러그를 형성함으로써, 드레인 콘택 플러그의 형성을완료하게 된다. 따라서, 콘택 플러그들 간에 단락이 유발되는 것을 방지할 수 있다.According to the present invention, even-numbered drain contact plugs of the plurality of drain contact plugs are formed through the first and second drain contact plugs 14 and 20 connected to the pad layer 16, and the third drain contact plug 22 is formed. By forming an odd-numbered drain contact plug among the plurality of drain contact plugs), the formation of the drain contact plug is completed. Thus, short circuiting can be prevented between contact plugs.

상기 본 발명의 실시 예에서는 짝수 번째 드레인 콘택플러그의 형성 공정시 드레인콘택플러그/패드막/드레인콘택플러그 형성공정을 적용하여 형성하는 것만 기재되어 있지만, 홀수 번째 드레인콘택플러그에도 적용되어 형성될 수 있다. In the embodiment of the present invention, only the drain contact plug / pad film / drain contact plug forming process is described in the process of forming the even-numbered drain contact plug, but it may be applied to the odd-numbered drain contact plug. .

또한, 본 발명의 실시예에서는 드레인 콘택플러그 형성방법만이 기재되었지만, 서로 이웃한 영역에 일렬로 형성되는 콘택플러그 모두에 적용되어 형성될 수 있다.Further, in the embodiment of the present invention, only the method for forming the drain contact plug is described. However, the method may be applied to all of the contact plugs formed in a line in adjacent areas.

본 발명에 의하면, 서로 이웃한 드레인 콘택플러그가 지그재그 형태로 형성됨으로써, 서로 이웃한 콘택플러그들이 접촉되는 것을 방지할 수 있어 소자특성이 향상된다. According to the present invention, since the drain contact plugs adjacent to each other are formed in a zigzag form, the contact plugs adjacent to each other can be prevented from contacting each other, thereby improving device characteristics.

이상에서 살펴본 바와 같이 본 발명에 의하면, 서로 이웃한 드레인 콘택플러그가 지그재그 형태로 형성됨으로써, 서로 이웃한 콘택플러그들이 접촉되는 것을 방지할 수 있어 소자특성이 향상되는 효과가 있다. As described above, according to the present invention, since the drain contact plugs adjacent to each other are formed in a zigzag form, the contact plugs adjacent to each other can be prevented from contacting each other, thereby improving device characteristics.

본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다. Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.

Claims (6)

교대로 배열된 복수의 제1 활성영역들 및 복수의 제2 활성영역들이 정의된 반도체 기판 상에 제1 층간절연막을 형성하는 단계;Forming a first interlayer insulating film on a semiconductor substrate in which a plurality of first active regions and a plurality of second active regions that are alternately arranged are defined; 상기 제1 층간 절연막을 관통하여 상기 복수의 제1 활성영역들과 각각 접하는 복수의 제1 콘택플러그들을 형성하는 단계;Forming a plurality of first contact plugs penetrating the first interlayer insulating layer, the plurality of first contact plugs respectively contacting the plurality of first active regions; 상기 제1 층간 절연막 상에 상기 복수의 제1 콘택플러그들과 각각 연결된 복수의 패드막들을 형성하는 단계;Forming a plurality of pad layers respectively connected to the plurality of first contact plugs on the first interlayer insulating layer; 상기 복수의 패드막들이 형성된 결과물 상에 제2 층간절연막을 형성하는 단계; 및Forming a second interlayer insulating film on a resultant product on which the plurality of pad films are formed; And 상기 제2 층간절연막을 관통하여 상기 제1 콘택플러그와 이격된 위치에서 상기 복수의 패드막들과 각각 연결된 복수의 제2 콘택플러그들을 형성하면서 동시에 상기 제2 및 제1 층간절연막을 관통하여 상기 복수의 제2 활성영역들과 각각 접하는 복수의 제3 콘택플러그들을 형성하는 단계The plurality of second contact plugs respectively connected to the plurality of pad layers are formed at positions spaced apart from the first contact plug through the second interlayer insulating layer, and simultaneously pass through the second and first interlayer insulating layers. Forming a plurality of third contact plugs respectively in contact with the second active regions of the substrate 를 포함하는 플래쉬 메모리소자의 콘택플러그 형성방법.Contact plug forming method of a flash memory device comprising a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 제1 항에 있어서, The method according to claim 1, 상기 제1 콘택플러그, 상기 패드막 및 상기 제2 콘택플러그는 하나의 드레인 콘택플러그를 형성하는 The first contact plug, the pad layer and the second contact plug form a drain contact plug. 플래쉬 메모리소자의 콘택플러그 형성방법. Method for forming contact plug of flash memory device. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 was abandoned when the setup registration fee was paid. 제1 항에 있어서, The method according to claim 1, 상기 제3 콘택플러그는 드레인 콘택플러그인The third contact plug is a drain contact plug. 플래쉬 메모리소자의 콘택플러그 형성방법. Method for forming contact plug of flash memory device. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제1 항에 있어서, The method according to claim 1, 상기 복수의 제1 콘택플러그들과 상기 복수의 제2 콘택플러그들은 일렬로 배열되는 The plurality of first contact plugs and the plurality of second contact plugs are arranged in a line. 플래쉬 메모리소자의 콘택플러그 형성방법. Method for forming contact plug of flash memory device. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제1 항에 있어서, The method according to claim 1, 상기 복수의 제2 콘택 플러그들과 상기 복수의 제3 콘택 플러그들은 지그재그 형태로 엇갈려 배열되는 The plurality of second contact plugs and the plurality of third contact plugs are alternately arranged in a zigzag form. 플래쉬 메모리소자의 콘택플러그 형성방법.  Method for forming contact plug of flash memory device. 삭제delete
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