CN112382564B - Method for manufacturing grid electrode - Google Patents

Abstract

The invention discloses a method for manufacturing a gate electrode, which includes the following steps: Step 1: forming a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate; Step 2: forming a hard mask on the surface of the amorphous silicon layer layer, the material of the hard mask layer is selected according to the lateral position shrinkage of each side of the subsequent amorphous silicon gate, so that the hardness of the hard mask layer becomes softer and ensures that the hard mask layer becomes softer after subsequent gate etching. The side is located inside or flush with the side of the corresponding amorphous silicon gate; Step 3: Photolithography defines the formation area of the gate; Step 4: Etch the hard mask layer and amorphous silicon layer in sequence to achieve gate etching eclipse. The present invention can control the morphology of the hard mask layer on the top of the amorphous silicon gate, so that the side surfaces of the hard mask layer are located inside or parallel to the side surfaces of the corresponding amorphous silicon gate, thereby facilitating the key points of the amorphous silicon gate. Measure the dimensions and improve the measurement accuracy and stability of the critical dimensions of the amorphous silicon gate.

Description

Gate manufacturing method

Technical field

The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to a gate manufacturing method.

Background technique

A dummy gate structure is required in high voltage (HV) or high dielectric constant metal gate (HKMG) products. In the HKMG process, the gate-back process is often used. In the gate-back process, a dummy gate structure needs to be formed first, and then the sidewalls and source-drain regions are formed by self-alignment of the dummy gate structure. After forming the first interlayer film, The dummy gate structure will be removed and a metal gate (MG) will be formed in the removed area of the dummy gate structure. The high dielectric constant layer (HK) in the gate dielectric layer can be formed when the dummy gate structure is formed, so that when the dummy gate structure is removed When using the dummy gate structure, there is no need to additionally remove the gate dielectric layer and form another gate dielectric layer including a high dielectric constant layer.

Different from the gate structure using polysilicon gate, the pseudo gate structure usually uses amorphous silicon gate. The amorphous silicon gate is formed by etching amorphous silicon. Compared with polycrystalline silicon, amorphous silicon material is not resistant to etching. In this way, the side surfaces of the amorphous silicon gate are easily etched during the etching process of the amorphous silicon gate. In the formation process of the pseudo gate structure, a hard mask layer is required. In the gate etching process, the hard mask layer will be etched first, and then the amorphous silicon layer will be etched. Since the amorphous silicon layer is not resistant to etching, Therefore, after the gate etching is completed, the side of the amorphous silicon gate will be recessed inside the side of the hard mask layer, which will affect the measurement of the critical dimensions of the amorphous silicon gate.

As shown in Figure 1, it is an ideal morphological structural diagram of a gate structure with an amorphous silicon gate formed by the existing gate manufacturing method; the gate structure formed on the surface of a semiconductor substrate such as a silicon substrate 101 is made of The gate dielectric layer including the high dielectric constant layer 102 and the bottom barrier layer 103 is superimposed on the amorphous silicon gate 104 and the hard mask layer 105. The high dielectric constant layer 2 is usually hafnium dioxide (HfO ₂ ). , the bottom barrier layer 103 is usually TiN. The hard mask layer 105 is usually a stacked layer of a silicon nitride layer 105a and a silicon oxide layer 105b. Ideally, after the hard mask layer 105 is etched, the amorphous silicon gate 104 will be etched down along the side of the hard mask layer 105, and finally the amorphous silicon gate 104 and the hard mask layer will be formed. The sides of the 105 are completely flat.

However, in fact, in the existing process, the side surfaces of the amorphous silicon gate 104 will be recessed, while the side surfaces of the hard mask layer 105 will be in a convex structure. As shown in Figure 2, it is an actual morphological structure diagram of a gate structure with an amorphous silicon gate formed by the existing gate manufacturing method; the gate structure formed on the surface of a semiconductor substrate such as a silicon substrate 201 is made of A gate dielectric layer including a high dielectric constant layer 202 and a bottom barrier layer 203 is superimposed on an amorphous silicon gate 204 and a hard mask layer 205. The high dielectric constant layer 202 is usually hafnium dioxide, and the bottom barrier layer 203 is usually made of hafnium dioxide. Layer 203 is typically TiN. The hard mask layer 205 is usually a stacked layer of a silicon nitride layer 205a and a silicon oxide layer 205b. Generally, the silicon nitride layer 205a is usually formed using a plasma enhanced (PE) chemical vapor deposition process (CVD), so it is also called PE SiN; the silicon oxide layer 205b usually uses tetraethyl orthosilicate (TEOS) as the silicon source. The silicon oxide formed is also called TEOS Oxide. As shown in FIG. 2 , the side surfaces of the silicon oxide layer 205 b protrude outside the side surfaces of the amorphous silicon gate 204 , that is, the width of the silicon oxide layer 205 b is larger. When viewed from the gate When the top of the structure is viewed downward, the amorphous silicon gate 204 will be hidden at the bottom of the hard mask layer 205, which will affect the measurement of the critical dimensions of the amorphous silicon gate 204. Here, the amorphous silicon gate 204 will be hidden at the bottom of the hard mask layer 205. The critical dimension of the gate 204 is the width, and measurement of the critical dimension of the amorphous silicon gate is prone to measurement inaccuracies and instability. As shown in FIG. 5A , it is a photo of the gate structure corresponding to FIG. 2 ; it can be seen that the side surfaces of the silicon oxide layer 205 b protrude outside the side surfaces of the amorphous silicon gate 204 . In the subsequent process, the silicon oxide layer 205b using TEOS Oxide in different areas has different degrees of loss, which is prone to different area load effects, and the uniformity of the film quality within the wafer surface is poor.

Contents of the invention

The technical problem to be solved by the present invention is to provide a gate manufacturing method that can control the morphology of the hard mask layer on the top of the amorphous silicon gate so that the side surfaces of the hard mask layer are located on the corresponding amorphous silicon gate. The side surfaces are inward or flat, which facilitates the measurement of critical dimensions of the amorphous silicon gate and improves the measurement accuracy and stability of the critical dimensions of the amorphous silicon gate.

In order to solve the above technical problems, the manufacturing method of the gate electrode provided by the present invention includes the following steps:

Step 1: Form a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate; compared to polysilicon materials, the amorphous silicon layer has reduced lateral etching resistance during subsequent gate etching and will cause subsequent non-crystalline silicon. The lateral positions of the sides of the crystalline silicon gate shrink toward the center of the amorphous silicon gate.

Step 2: Form a hard mask layer on the surface of the amorphous silicon layer, and select the material of the hard mask layer according to the subsequent lateral position shrinkage of each side of the amorphous silicon gate, so that the hard mask layer The hardness of the hard mask layer becomes softer and ensures that after subsequent gate etching, the side surfaces of the hard mask layer are located inside or flush with the corresponding side surfaces of the amorphous silicon gate.

Step 3: Use photolithography to define the formation area of the gate.

Step 4: Etch the hard mask layer and the amorphous silicon layer in sequence to achieve the gate etching. The amorphous silicon layer after the gate etching is composed of the amorphous silicon layer. A silicon gate, a first gate structure is formed by stacking the first gate dielectric layer, the amorphous silicon gate and the hard mask layer after the gate is etched.

A further improvement is that the subsequent step also includes the step of measuring the critical dimensions of the first gate structure, and the side surfaces of the hard mask layer are located inside or parallel to the corresponding side surfaces of the amorphous silicon gate. The measurement value of the critical dimension of the first gate structure is made accurate and stable.

A further improvement is that the hard mask layer includes a second nitrogen-free dielectric anti-reflective coating (NFDARC).

A further improvement is that the hard mask layer also includes a first hexachlorodisilane (HCD) silicon nitride layer, and the hexachlorodisilane silicon nitride layer is silicon nitride formed using hexachlorodisilane, so The first HCD silicon nitride layer is formed on the surface of the amorphous silicon layer, and the second nitrogen-free dielectric anti-reflective coating is formed on the inner surface of the first HCD silicon nitride layer.

A further improvement is that the first gate structure serves as a dummy gate structure, and the amorphous silicon gate is a dummy amorphous silicon gate. The dummy amorphous silicon gate will be removed and replaced with a metal gate in subsequent processes. .

A further improvement is that the first gate dielectric layer includes a high dielectric constant layer, the first gate dielectric layer and the metal gate are superimposed to form a second gate structure, and the second gate structure is a high dielectric constant layer. Constant metal grid.

A further improvement is that after step four, there are also steps:

Step 5: Form spacers on the side of the first gate structure.

Step 6: Form source regions and drain regions on the semiconductor substrate on both sides of the first gate structure.

Step 7: Form a contact etching stop layer.

Step 8: Form the first interlayer film.

Step 9: Remove the hard mask layer, grind the surfaces of the first interlayer film and the contact etching stop layer until they are flush with the top surface of the amorphous silicon gate, and make the amorphous silicon gate The top surface of the crystalline silicon gate is exposed.

Step 10: Remove the amorphous silicon gate.

Step 11: Form the metal gate in the amorphous silicon gate removal area.

A further improvement is that before forming the spacers, a step of self-aligning to form a lightly doped drain region in the semiconductor substrate on the side of the first gate structure is also included.

A further improvement is that the semiconductor substrate includes a silicon substrate.

A further improvement is that the material of the sidewalls includes silicon oxide or silicon nitride.

A further improvement is that the material of the contact etching stop layer includes silicon nitride.

A further improvement is that the first gate dielectric layer further includes an interface layer located between the high dielectric constant layer and the semiconductor substrate.

A further improvement is that the material of the interface layer includes silicon oxide.

A further improvement is that the material of the high dielectric constant layer includes hafnium dioxide.

A further improvement is that the gate dielectric layer further includes a bottom barrier layer, and the bottom barrier layer is located between the high dielectric constant layer and the metal gate.

A further improvement is that the bottom barrier layer composition material includes titanium nitride.

A further improvement is that the metal gate includes a work function layer and a metal conductive material layer.

According to the characteristics of the amorphous silicon material, which is more sparse than polycrystalline silicon material and is not resistant to etching, and will eventually cause the sides of the amorphous silicon gate to shrink toward the center of the gate, the present invention also makes corresponding changes to the material of the hard mask layer. The setting makes the material of the hard mask layer softer, so that the hard mask layer will also produce a certain lateral etching during the gate etching and ensures that the hard mask layer will be softened after the gate etching. The side surfaces of the amorphous silicon gate are located inside or flush with the side surfaces of the corresponding amorphous silicon gate. Therefore, the present invention can overcome the key problem of the amorphous silicon gate when the side surfaces of the hard mask layer protrude outside the side surfaces of the amorphous silicon gate in the prior art. The size is difficult to measure accurately and stably. Therefore, the present invention is beneficial to the measurement of the critical dimensions of the amorphous silicon gate and improves the measurement accuracy and stability of the critical dimensions of the amorphous silicon gate.

In a preferred embodiment, the hard mask layer of the present invention can be realized by using a superimposed layer of the first HCD silicon nitride layer and the second nitrogen-free dielectric anti-reflective coating, which can make the hard mask layer after the gate etching The cross-sectional structure of the quality mask layer is a trapezoidal structure that is narrow at the top and wide at the bottom, so that the critical dimensions of the amorphous silicon gate can be measured with high accuracy and stability.

In addition, compared with the TEOS oxide layer used as the oxide layer of the hard mask layer in the prior art, the second nitrogen-free dielectric anti-reflective coating has better acid etching resistance, and the film quality of different structures will be lost in the subsequent process. The load effect brought about is also improved accordingly.

Description of the drawings

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments:

Figure 1 is an ideal morphological structure diagram of a gate structure with an amorphous silicon gate formed by the existing gate manufacturing method;

Figure 2 is an actual morphological structure diagram of a gate structure with an amorphous silicon gate formed by an existing gate manufacturing method;

Figure 3 is a flow chart of a gate manufacturing method according to an embodiment of the present invention;

Figure 4 is an actual morphological structure diagram of a gate structure with an amorphous silicon gate formed by the method of the embodiment of the present invention;

Figure 5A is a photo of the gate structure corresponding to Figure 2;

FIG. 5B is a photograph of the gate structure corresponding to FIG. 4 .

Detailed ways

As shown in Figure 3, it is a flow chart of the manufacturing method of the gate electrode according to the embodiment of the present invention; as shown in Figure 4, it is the actual morphological structural diagram of the gate electrode structure with the amorphous silicon gate 4 formed by the method according to the embodiment of the present invention. ; The manufacturing method of the gate electrode according to the embodiment of the present invention includes the following steps:

Step 1: Form a first gate dielectric layer and an amorphous silicon layer on the semiconductor substrate 1; compared with polysilicon material, the lateral etching resistance of the amorphous silicon layer decreases during subsequent gate etching and will cause subsequent gate etching. The lateral position of each side surface of the amorphous silicon gate 4 shrinks toward the center of the amorphous silicon gate 4 .

Step 2: Form a hard mask layer 5 on the surface of the amorphous silicon layer, and select the material of the hard mask layer 5 according to the subsequent lateral position shrinkage of each side of the amorphous silicon gate 4, so that The hardness of the hard mask layer 5 becomes softer and ensures that after the subsequent gate etching, the side surfaces of the hard mask layer 5 are located inside or flush with the corresponding side surfaces of the amorphous silicon gate 4 .

In this embodiment of the present invention, the hard mask layer 5 includes a second nitrogen-free dielectric anti-reflective coating 5b.

The hard mask layer 5 also includes a first HCD silicon nitride layer 5a, the first HCD silicon nitride layer 5a is formed on the surface of the amorphous silicon layer, and the second nitrogen-free dielectric anti-reflective coating Layer 5b is formed on the inner surface of the first HCD silicon nitride layer 5a.

Step 3: Use photolithography to define the formation area of the gate.

Step 4: Etch the hard mask layer 5 and the amorphous silicon layer in sequence to achieve the gate etching. The amorphous silicon layer after the gate etching is composed of the amorphous silicon layer. The crystalline silicon gate 4 is formed by superposing the first gate dielectric layer after the gate electrode is etched, the amorphous silicon gate 4 and the hard mask layer 5 to form a first gate structure.

The subsequent step also includes the step of measuring the critical dimensions of the first gate structure. The side surfaces of the hard mask layer 5 are located inside or parallel to the corresponding side surfaces of the amorphous silicon gate 4 so that the Measurements of critical dimensions of the first gate structure are accurate and stable.

In the embodiment of the present invention, the first gate structure serves as a dummy gate structure, and the amorphous silicon gate 4 is a dummy amorphous silicon gate 4. The dummy amorphous silicon gate 4 will be removed and replaced in the subsequent process. Replaced with metal grating.

The first gate dielectric layer includes a high dielectric constant layer 2. The first gate dielectric layer and the metal gate are superimposed to form a second gate structure. The second gate structure is a high dielectric constant metal gate.

The semiconductor substrate 1 includes a silicon substrate.

The first gate dielectric layer also includes an interface layer, which is located between the high dielectric constant layer 2 and the semiconductor substrate 1 . Preferably, the material of the interface layer includes silicon oxide.

The material of the high dielectric constant layer 2 includes hafnium dioxide.

The gate dielectric layer also includes a bottom barrier layer 3, which is located between the high dielectric constant layer 2 and the metal gate. The bottom barrier layer 3 is made of titanium nitride.

The metal gate includes a work function layer and a metal conductive material layer. For PMOS, the material of the work function layer usually uses TiN; for NMOS, the material of the work function layer usually uses TiAl. The metal conductive material layer usually uses an Al layer, but can also use a tungsten layer. A top barrier layer is also typically included between the work function layer and the metal conductive material layer.

After step four, there are also steps:

Step 5: Form spacers on the side of the first gate structure.

The sidewall material includes silicon oxide or silicon nitride.

Preferably, before forming the spacers, the step further includes the step of self-aligning to form a lightly doped drain region in the semiconductor substrate 1 on the side of the first gate structure.

Step 6: Form source regions and drain regions on the semiconductor substrate 1 on both sides of the first gate structure.

Step 7: Form a contact etching stop layer.

The material of the contact etching stop layer includes silicon nitride.

Step 8: Form the first interlayer film.

Step 9: Remove the hard mask layer 5, grind the surfaces of the first interlayer film and the contact etching stop layer until they are flush with the top surface of the amorphous silicon gate 4, and make the The top surface of the amorphous silicon gate 4 is exposed.

Step 10: Remove the amorphous silicon gate 4 .

Step 11: Form the metal gate in the removed area of the amorphous silicon gate 4 .

According to the characteristics of the amorphous silicon material, which is more sparse than the polycrystalline silicon material and is not resistant to etching, and will eventually cause the side surfaces of the amorphous silicon gate 4 to shrink toward the center of the gate, the embodiment of the present invention treats the hard mask layer 5 The material of the hard mask layer 5 has also been set accordingly, so that the material of the hard mask layer 5 also becomes softer, so that the hard mask layer 5 will also produce a certain lateral etching during the gate etching and ensure the gate etching. After etching, the side surfaces of the hard mask layer 5 are located inside or flush with the corresponding side surfaces of the amorphous silicon gate 4. Therefore, the embodiment of the present invention can overcome the problem in the prior art that the side surfaces of the hard mask layer 5 protrude beyond the amorphous silicon gate. The defects on the side surfaces of the silicon gate make it difficult to accurately and stably measure the critical dimensions of the amorphous silicon gate. Therefore, embodiments of the present invention are beneficial to the measurement of the critical dimensions of the amorphous silicon gate and improve the measurement of the critical dimensions of the amorphous silicon gate. Accuracy and stability.

In the embodiment of the present invention, the hard mask layer 5 can be realized by using a superimposed layer of the first HCD silicon nitride layer 5a and the second nitrogen-free dielectric anti-reflective coating 5b, which can make the hard mask layer after the gate etching The cross-sectional structure of the mask layer 5 is a trapezoidal structure that is narrow at the top and wide at the bottom, so that the critical dimensions of the amorphous silicon gate can be measured with high accuracy and stability.

In addition, compared with the TEOS oxide layer used as the oxide layer of the hard mask layer in the prior art, the second nitrogen-free dielectric anti-reflective coating 5b has better acid etching resistance, and the film quality of different structures will be lost in subsequent processes. The load effect brought about by it is also improved accordingly.

As shown in Figure 5B, it is a photo of the gate structure corresponding to Figure 4; compared with the gate structure formed by the existing method corresponding to Figure 5A, the side of the hard mask layer 5 in Figure 5B does not have lateral The structure protruding out of the side surface of the amorphous silicon gate 4 enables accurate and stable measurement of the critical dimension, that is, the width of the amorphous silicon gate 4 .

The present invention has been described in detail through specific embodiments, but these do not constitute limitations to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (15)

1. A method of manufacturing a gate electrode, comprising the steps of:

step one, forming a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate; compared with the polysilicon material, the transverse etching resistance of the amorphous silicon layer in the subsequent gate etching is reduced, and the transverse positions of the lateral sides of the subsequent amorphous silicon gate shrink towards the center of the amorphous silicon gate;

secondly, forming a hard mask layer on the surface of the amorphous silicon layer, and selecting the material of the hard mask layer according to the transverse position shrinkage of each side surface of the subsequent amorphous silicon gate, so that the hardness of the hard mask layer becomes soft, and the side surface of the hard mask layer is positioned on the inner side or the flattening side surface of the corresponding amorphous silicon gate after the subsequent gate etching;

the hard mask layer comprises a second nitrogen-free dielectric antireflective coating and a first HCD silicon nitride layer, the first HCD silicon nitride layer is formed on the surface of the amorphous silicon layer, and the second nitrogen-free dielectric antireflective coating is formed on the inner surface of the first HCD silicon nitride layer;

step three, photoetching and defining a forming area of the grid electrode;

and step four, sequentially etching the hard mask layer and the amorphous silicon layer to realize the gate etching, forming an amorphous silicon gate by the amorphous silicon layer after the gate etching, and stacking the first gate dielectric layer, the amorphous silicon gate and the hard mask layer after the gate etching to form a first gate structure.

2. The method of manufacturing a gate electrode according to claim 1, wherein: and the step of measuring the critical dimension of the first gate structure is further included, and the structure that the side surface of the hard mask layer is positioned on the inner side of the side surface of the corresponding amorphous silicon gate or is flat enables the measurement value of the critical dimension of the first gate structure to be accurate and stable.

3. The method of manufacturing a gate electrode according to claim 1, wherein: the first gate structure is used as a pseudo gate structure, the amorphous silicon gate is a pseudo amorphous silicon gate, and the pseudo amorphous silicon gate can be removed and replaced by a metal gate in a subsequent process.

4. A method of manufacturing a gate electrode according to claim 3, wherein: the first gate dielectric layer comprises a high dielectric constant layer, the first gate dielectric layer and the metal gate are overlapped to form a second gate structure, and the second gate structure is a high dielectric constant metal gate.

5. The method of manufacturing a gate electrode according to claim 4, wherein: the fourth step further comprises the steps of:

forming a side wall on the side surface of the first grid structure;

step six, forming a source region and a drain region on the semiconductor substrate at two sides of the first grid structure;

step seven, forming a contact etching stop layer;

step eight, forming a first interlayer film;

step nine, removing the hard mask layer, and grinding the surfaces of the first interlayer film and the contact etching stop layer to be level with the top surface of the amorphous silicon gate and exposing the top surface of the amorphous silicon gate;

step ten, removing the amorphous silicon gate;

and step eleven, forming the metal gate in the amorphous silicon gate removing area.

6. The method of manufacturing a gate electrode according to claim 5, wherein: the method further comprises the step of forming a lightly doped drain region in the semiconductor substrate on the side face of the first grid electrode structure in a self-aligned mode before forming the side wall.

7. The method of manufacturing a gate electrode according to claim 5, wherein: the semiconductor substrate includes a silicon substrate.

8. The method of manufacturing a gate electrode according to claim 7, wherein: the material of the side wall comprises silicon oxide or silicon nitride.

9. The method of manufacturing a gate electrode according to claim 7, wherein: the material of the contact etch stop layer comprises silicon nitride.

10. The method of manufacturing a gate electrode according to claim 7, wherein: the first gate dielectric layer further comprises an interface layer, and the interface layer is located between the high dielectric constant layer and the semiconductor substrate.

11. The method of manufacturing a gate electrode according to claim 10, wherein: the material of the interface layer comprises silicon oxide.

12. The method of manufacturing a gate electrode according to claim 4, wherein: the material of the high dielectric constant layer comprises hafnium oxide.

13. The method of manufacturing a gate electrode according to claim 10, wherein: the gate dielectric layer also includes a bottom barrier layer between the high dielectric constant layer and the metal gate.

14. The method of manufacturing a gate electrode of claim 13, wherein: the bottom barrier layer composition material comprises titanium nitride.

15. The method of manufacturing a gate electrode according to claim 4, wherein: the metal gate includes a work function layer and a metal conductive material layer.