CN112382564B - Method for manufacturing grid electrode - Google Patents
Method for manufacturing grid electrode Download PDFInfo
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- CN112382564B CN112382564B CN202011201919.9A CN202011201919A CN112382564B CN 112382564 B CN112382564 B CN 112382564B CN 202011201919 A CN202011201919 A CN 202011201919A CN 112382564 B CN112382564 B CN 112382564B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims description 24
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 113
- 238000005530 etching Methods 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 238000005259 measurement Methods 0.000 claims abstract description 10
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 191
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 14
- 230000004888 barrier function Effects 0.000 claims description 13
- 239000006117 anti-reflective coating Substances 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- LXEXBJXDGVGRAR-UHFFFAOYSA-N trichloro(trichlorosilyl)silane Chemical compound Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl LXEXBJXDGVGRAR-UHFFFAOYSA-N 0.000 description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- FAQXXMTVCNQJPT-UHFFFAOYSA-N [Si].Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl Chemical compound [Si].Cl[Si](Cl)(Cl)[Si](Cl)(Cl)Cl FAQXXMTVCNQJPT-UHFFFAOYSA-N 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Composite Materials (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method of a grid electrode, which comprises the following steps: step one, forming a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate; secondly, forming a hard mask layer on the surface of the amorphous silicon layer, and shrinking and selecting the material of the hard mask layer according to the transverse position of each side surface of the subsequent amorphous silicon gate, so that the hardness of the hard mask layer becomes soft, and the side surface of the hard mask layer is positioned on the inner side or the same level as the side surface of the corresponding amorphous silicon gate after the subsequent gate is etched; step three, photoetching and defining a forming area of the grid electrode; and step four, etching the hard mask layer and the amorphous silicon layer in sequence to realize gate etching. The invention can control the appearance of the hard mask layer at the top of the amorphous silicon gate, and the side surface of the hard mask layer is positioned at the inner side or the flat side surface of the corresponding amorphous silicon gate, thereby being beneficial to the measurement of the critical dimension of the amorphous silicon gate and improving the measurement precision and the stability of the critical dimension of the amorphous silicon gate.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a gate electrode.
Background
A dummy gate structure is required in the production of High Voltage (HV) or high dielectric constant metal gates (HKMG). In the HKMG process, a post-gate process is often adopted, in which a dummy gate structure is required to be formed first, then a sidewall and a source drain region are formed by self-alignment of the dummy gate structure, after a first interlayer film is formed, the dummy gate structure is removed, a Metal Gate (MG) is formed in a removed region of the dummy gate structure, and a high dielectric constant layer (HK) in the gate dielectric layer can be formed when the dummy gate structure is formed, so that the gate dielectric layer is not required to be removed additionally and a gate dielectric layer including a high dielectric constant layer is formed again when the dummy gate structure is removed.
Unlike the gate structure using polysilicon gate, the dummy gate structure usually uses amorphous silicon gate, which is formed by etching amorphous silicon, and compared with polysilicon, amorphous silicon material is not resistant to etching, so that the side surface of amorphous silicon gate is easily etched in the etching process of amorphous silicon gate. In the forming process of the pseudo gate structure, a hard mask layer is needed, the hard mask layer is etched in the gate etching process, and then the amorphous silicon layer is etched, and the side face of the amorphous silicon gate is recessed inside the side face of the hard mask layer after the gate etching is completed because the amorphous silicon layer is not resistant to etching, so that the measurement of the critical dimension of the amorphous silicon gate is affected.
As shown in fig. 1, the structure is an ideal morphology structure diagram of a gate structure with an amorphous silicon gate formed by the prior gate manufacturing method; the gate structure formed on the surface of a semiconductor substrate such as silicon substrate 101 is formed by stacking a gate dielectric layer including a high dielectric constant layer 102 and a bottom barrier layer 103, an amorphous silicon gate 104, and a hard mask layer 105, the high dielectric constant layer 2 is typically hafnium oxide (HfO 2 ) The bottom barrier layer 103 is typically TiN. The hard mask layer 105 is typically an overlying layer of silicon nitride layer 105a and silicon oxide layer 105 b. Ideally, after the hard mask layer 105 is etched, the amorphous silicon gate 104 will be etched down along the side of the hard mask layer 105, and finally a completely flat structure is formed between the amorphous silicon gate 104 and the side of the hard mask layer 105.
In practice, however, in the prior art, the side of the amorphous silicon gate 104 is concave, and the side of the hard mask layer 105 is convex. As shown in fig. 2, the actual morphology structure diagram of the gate structure with the amorphous silicon gate formed by the prior gate manufacturing method is shown; the gate structure formed on the surface of a semiconductor substrate such as a silicon substrate 201 is formed by stacking a gate dielectric layer including a high dielectric constant layer 202 and a bottom barrier layer 203, an amorphous silicon gate 204, and a hard mask layer 205, wherein the high dielectric constant layer 202 is typically hafnium dioxide, and the bottom barrier layer 203 is typically TiN. The hard mask layer 205 is typically an overlying layer of silicon nitride 205a and silicon oxide 205 b. Typically, the silicon nitride layer 205a is typically formed using a Plasma Enhanced (PE) chemical vapor deposition process (CVD), and is also referred to as PE SiN; the silicon Oxide layer 205b is typically silicon Oxide formed using tetraethyl orthosilicate (TEOS) as a silicon source, and is also referred to as TEOS Oxide. As shown in fig. 2, the side surface of the silicon oxide layer 205b protrudes outside the side surface of the amorphous silicon gate 204, that is, the width of the silicon oxide layer 205b is larger, when the top of the gate structure is viewed from the top down, the amorphous silicon gate 204 is hidden at the bottom of the hard mask layer 205, which affects the measurement of the critical dimension of the amorphous silicon gate 204, where the critical dimension of the amorphous silicon gate 204 is the width, and the measurement of the critical dimension of the amorphous silicon gate is prone to inaccurate and unstable measurement. As shown in fig. 5A, a photo of the corresponding gate structure of fig. 2; it can be seen that the sides of the silicon oxide layer 205b protrude outside the sides of the amorphous silicon gate 204. In the subsequent process, the loss degree of the silicon Oxide layer 205b using TEOS Oxide in different regions is different, so that the loading effect of different regions is easy to occur, and the uniformity of the film quality in the wafer surface is poor.
Disclosure of Invention
The invention aims to provide a manufacturing method of a grid, which can control the shape of a hard mask layer at the top of an amorphous silicon grid, and enable the side surface of the hard mask layer to be positioned at the inner side or the flat side surface of the corresponding amorphous silicon grid, thereby being beneficial to measuring the critical dimension of the amorphous silicon grid and improving the measuring precision and the stability of the critical dimension of the amorphous silicon grid.
In order to solve the technical problems, the manufacturing method of the grid electrode provided by the invention comprises the following steps:
step one, forming a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate; compared with the polysilicon material, the transverse etching resistance of the amorphous silicon layer in the subsequent gate etching is reduced, and the transverse positions of the lateral sides of the subsequent amorphous silicon gate can shrink towards the center of the amorphous silicon gate.
And secondly, forming a hard mask layer on the surface of the amorphous silicon layer, and selecting the material of the hard mask layer according to the transverse position shrinkage of each side surface of the subsequent amorphous silicon gate, so that the hardness of the hard mask layer is softened, and the side surface of the hard mask layer is positioned on the inner side or the leveling side surface of the corresponding amorphous silicon gate after the subsequent gate etching.
And step three, photoetching and defining a forming area of the grid electrode.
And step four, sequentially etching the hard mask layer and the amorphous silicon layer to realize the gate etching, forming an amorphous silicon gate by the amorphous silicon layer after the gate etching, and stacking the first gate dielectric layer, the amorphous silicon gate and the hard mask layer after the gate etching to form a first gate structure.
The method is further improved, and the method further comprises the step of measuring the critical dimension of the first gate structure, wherein the side face of the hard mask layer is located on the inner side of the side face of the corresponding amorphous silicon gate or on the flat structure, so that the measured value of the critical dimension of the first gate structure is accurate and stable.
A further improvement is that the hard mask layer includes a second nitrogen-free dielectric antireflective coating (NFDARC).
The hard mask layer further comprises a first Hexachlorodisilane (HCD) silicon nitride layer, wherein the hexachlorodisilane silicon nitride layer is silicon nitride formed by hexachlorodisilane, the first HCD silicon nitride layer is formed on the surface of the amorphous silicon layer, and the second nitrogen-free dielectric anti-reflection coating is formed on the inner surface of the first HCD silicon nitride layer.
In a further improvement, the first gate structure is used as a dummy gate structure, the amorphous silicon gate is a dummy amorphous silicon gate, and the dummy amorphous silicon gate is removed and replaced with a metal gate in a subsequent process.
The first gate dielectric layer comprises a high dielectric constant layer, the first gate dielectric layer and the metal gate are overlapped to form a second gate structure, and the second gate structure is a high dielectric constant metal gate.
The further improvement is that the step four further comprises the steps of:
and fifthly, forming a side wall on the side surface of the first grid structure.
And step six, forming a source region and a drain region on the semiconductor substrate at two sides of the first grid structure.
And step seven, forming a contact etching stop layer.
And step eight, forming a first interlayer film.
And step nine, removing the hard mask layer, and grinding the surfaces of the first interlayer film and the contact etching stop layer to be level with the top surface of the amorphous silicon gate and exposing the top surface of the amorphous silicon gate.
And step ten, removing the amorphous silicon gate.
And step eleven, forming the metal gate in the amorphous silicon gate removing area.
In a further improvement, the method further comprises the step of forming a lightly doped drain region in the semiconductor substrate at the side surface of the first grid electrode structure in a self-aligned mode before forming the side wall.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
The material of the side wall comprises silicon oxide or silicon nitride.
A further improvement is that the material of the contact etch stop layer comprises silicon nitride.
The first gate dielectric layer further comprises an interface layer between the high dielectric constant layer and the semiconductor substrate
A further improvement is that the material of the interface layer comprises silicon oxide.
A further improvement is that the material of the high dielectric constant layer comprises hafnium oxide.
In a further improvement, the gate dielectric layer further comprises a bottom barrier layer, the bottom barrier layer being located between the high dielectric constant layer and the metal gate.
In a further improvement, the bottom barrier layer composition material comprises titanium nitride.
A further improvement is that the metal gate includes a work function layer and a layer of metal conductive material.
According to the invention, according to the characteristics that the amorphous silicon material is more loose and not resistant to etching and finally the side surface of the amorphous silicon gate can shrink towards the center of the gate, the material of the hard mask layer is correspondingly arranged, so that the material of the hard mask layer is softened, and the hard mask layer can generate certain transverse etching in the gate etching and ensure that the side surface of the hard mask layer is positioned at the inner side or the flat side of the side surface of the corresponding amorphous silicon gate after the gate etching.
In the preferred embodiment, the hard mask layer of the invention is realized by adopting the superimposed layer of the first HCD silicon nitride layer and the second nitrogen-free dielectric antireflective coating, so that the cross-section structure of the hard mask layer after the grid electrode etching is in a trapezoid structure with narrow top and wide bottom, thereby ensuring that the measurement of the critical dimension of the amorphous silicon gate has higher precision and stability.
In addition, compared with the prior art that the oxide layer of the hard mask layer adopts a TEOS oxide layer, the second nitrogen-free dielectric anti-reflection coating has better acid etching resistance, and the loading effect caused by the film quality loss of different structures in the subsequent process is correspondingly improved.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is an ideal morphology structure diagram of a gate structure with an amorphous silicon gate formed by a conventional gate manufacturing method;
fig. 2 is a diagram showing the actual morphology structure of a gate structure with an amorphous silicon gate formed by the conventional gate manufacturing method;
FIG. 3 is a flow chart of a method of fabricating a gate according to an embodiment of the present invention;
FIG. 4 is a diagram of an actual morphology structure of a gate structure with amorphous silicon gate formed by the method of an embodiment of the present invention;
FIG. 5A is a photograph of the corresponding gate structure of FIG. 2;
fig. 5B is a photograph of the corresponding gate structure of fig. 4.
Detailed Description
FIG. 3 is a flow chart of a method for manufacturing a gate according to an embodiment of the invention; as shown in fig. 4, the actual morphology structure diagram of the gate structure with the amorphous silicon gate 4 formed by the method of the embodiment of the invention is shown; the manufacturing method of the grid electrode comprises the following steps:
step one, forming a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate 1; the lateral etch resistance of the amorphous silicon layer in a subsequent gate etch is reduced and the lateral position of each side of the subsequent amorphous silicon gate 4 is shrunk towards the center of the amorphous silicon gate 4 with respect to the polysilicon material.
And secondly, forming a hard mask layer 5 on the surface of the amorphous silicon layer, and selecting the material of the hard mask layer 5 according to the transverse position shrinkage of each side surface of the subsequent amorphous silicon gate 4, so that the hardness of the hard mask layer 5 is softened, and the side surface of the hard mask layer 5 is positioned on the inner side or the flattening side surface of the corresponding amorphous silicon gate 4 after the subsequent gate etching.
In the embodiment of the present invention, the hard mask layer 5 includes a second nitrogen-free dielectric antireflective coating 5b.
The hard mask layer 5 further comprises a first HCD silicon nitride layer 5a, the first HCD silicon nitride layer 5a is formed on the surface of the amorphous silicon layer, and the second nitrogen-free dielectric antireflective coating 5b is formed on the inner surface of the first HCD silicon nitride layer 5 a.
And step three, photoetching and defining a forming area of the grid electrode.
And step four, sequentially etching the hard mask layer 5 and the amorphous silicon layer to realize the gate etching, forming an amorphous silicon gate 4 by the amorphous silicon layer after the gate etching, and superposing the first gate dielectric layer, the amorphous silicon gate 4 and the hard mask layer 5 after the gate etching to form a first gate structure.
The following step further includes a step of measuring the critical dimension of the first gate structure, where the side surface of the hard mask layer 5 is located inside the corresponding side surface of the amorphous silicon gate 4 or in a flat structure, so that the measured value of the critical dimension of the first gate structure is accurate and stable.
In the embodiment of the present invention, the first gate structure is used as a dummy gate structure, the amorphous silicon gate 4 is a dummy amorphous silicon gate 4, and the dummy amorphous silicon gate 4 is removed and replaced with a metal gate in a subsequent process.
The first gate dielectric layer comprises a high dielectric constant layer 2, the first gate dielectric layer and the metal gate are overlapped to form a second gate structure, and the second gate structure is a high dielectric constant metal gate.
The semiconductor substrate 1 includes a silicon substrate.
The first gate dielectric layer further comprises an interface layer, and the interface layer is located between the high dielectric constant layer 2 and the semiconductor substrate 1. Preferably, the material of the interface layer comprises silicon oxide.
The material of the high dielectric constant layer 2 comprises hafnium oxide.
The gate dielectric layer further comprises a bottom barrier layer 3, and the bottom barrier layer 3 is located between the high dielectric constant layer 2 and the metal gate. The bottom barrier layer 3 comprises a material including titanium nitride.
The metal gate includes a work function layer and a metal conductive material layer. For PMOS, tiN is typically used as the material of the work function layer; for NMOS, tiAl is typically used as the material for the work function layer. The metal conductive material layer is usually an Al layer, and can also be a tungsten layer. A top barrier layer is also typically included between the work function layer and the metal conductive material layer.
The fourth step further comprises the steps of:
and fifthly, forming a side wall on the side surface of the first grid structure.
The material of the side wall comprises silicon oxide or silicon nitride.
Preferably, before forming the side wall, the method further comprises a step of forming a lightly doped drain region in the semiconductor substrate 1 at the side surface of the first gate structure in a self-aligned manner.
And step six, forming a source region and a drain region on the semiconductor substrate 1 at two sides of the first gate structure.
And step seven, forming a contact etching stop layer.
The material of the contact etch stop layer comprises silicon nitride.
And step eight, forming a first interlayer film.
And step nine, removing the hard mask layer 5, and grinding the surfaces of the first interlayer film and the contact etching stop layer to be level with the top surface of the amorphous silicon gate 4 and exposing the top surface of the amorphous silicon gate 4.
And step ten, removing the amorphous silicon gate 4.
And step eleven, forming the metal gate in the amorphous silicon gate 4 removing area.
According to the embodiment of the invention, according to the characteristics that the amorphous silicon material is more loose and not resistant to etching and finally the side surface of the amorphous silicon gate 4 can shrink towards the center of the gate, the embodiment of the invention also correspondingly sets the material of the hard mask layer 5, so that the material of the hard mask layer 5 is softened, and the hard mask layer 5 can generate certain transverse etching in gate etching and ensure that the side surface of the hard mask layer 5 is positioned at the inner side or the flattening side surface of the corresponding amorphous silicon gate 4 after the gate etching, therefore, the embodiment of the invention can overcome the defect that the critical dimension of the amorphous silicon gate is not easy to accurately and stably measure when the side surface of the hard mask layer 5 protrudes out of the side surface of the amorphous silicon gate in the prior art, and is beneficial to measuring the critical dimension of the amorphous silicon gate and improving the measuring precision and the stability of the critical dimension of the amorphous silicon gate.
In the embodiment of the invention, the hard mask layer 5 is realized by adopting the superimposed layer of the first HCD silicon nitride layer 5a and the second nitrogen-free dielectric reactance reflection coating layer 5b, so that the cross-section structure of the hard mask layer 5 after grid etching is in a trapezoid structure with narrow top and wide bottom, and the measurement of the critical dimension of the amorphous silicon gate is enabled to have higher precision and stability.
In addition, compared with the oxide layer of the hard mask layer in the prior art, the TEOS oxide layer is adopted for the second nitrogen-free dielectric antireflective coating 5b, so that the acid etching resistance is better, and the loading effect caused by the loss of different structure films in the subsequent process is correspondingly improved.
As shown in fig. 5B, a photograph of the corresponding gate structure of fig. 4; compared with the gate structure formed by the conventional method corresponding to fig. 5A, the side surface of the hard mask layer 5 in fig. 5B does not laterally protrude beyond the side surface of the amorphous silicon gate 4, so that accurate and stable measurement of the critical dimension, i.e., the width, of the amorphous silicon gate 4 can be realized.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. A method of manufacturing a gate electrode, comprising the steps of:
step one, forming a first gate dielectric layer and an amorphous silicon layer on a semiconductor substrate; compared with the polysilicon material, the transverse etching resistance of the amorphous silicon layer in the subsequent gate etching is reduced, and the transverse positions of the lateral sides of the subsequent amorphous silicon gate shrink towards the center of the amorphous silicon gate;
secondly, forming a hard mask layer on the surface of the amorphous silicon layer, and selecting the material of the hard mask layer according to the transverse position shrinkage of each side surface of the subsequent amorphous silicon gate, so that the hardness of the hard mask layer becomes soft, and the side surface of the hard mask layer is positioned on the inner side or the flattening side surface of the corresponding amorphous silicon gate after the subsequent gate etching;
the hard mask layer comprises a second nitrogen-free dielectric antireflective coating and a first HCD silicon nitride layer, the first HCD silicon nitride layer is formed on the surface of the amorphous silicon layer, and the second nitrogen-free dielectric antireflective coating is formed on the inner surface of the first HCD silicon nitride layer;
step three, photoetching and defining a forming area of the grid electrode;
and step four, sequentially etching the hard mask layer and the amorphous silicon layer to realize the gate etching, forming an amorphous silicon gate by the amorphous silicon layer after the gate etching, and stacking the first gate dielectric layer, the amorphous silicon gate and the hard mask layer after the gate etching to form a first gate structure.
2. The method of manufacturing a gate electrode according to claim 1, wherein: and the step of measuring the critical dimension of the first gate structure is further included, and the structure that the side surface of the hard mask layer is positioned on the inner side of the side surface of the corresponding amorphous silicon gate or is flat enables the measurement value of the critical dimension of the first gate structure to be accurate and stable.
3. The method of manufacturing a gate electrode according to claim 1, wherein: the first gate structure is used as a pseudo gate structure, the amorphous silicon gate is a pseudo amorphous silicon gate, and the pseudo amorphous silicon gate can be removed and replaced by a metal gate in a subsequent process.
4. A method of manufacturing a gate electrode according to claim 3, wherein: the first gate dielectric layer comprises a high dielectric constant layer, the first gate dielectric layer and the metal gate are overlapped to form a second gate structure, and the second gate structure is a high dielectric constant metal gate.
5. The method of manufacturing a gate electrode according to claim 4, wherein: the fourth step further comprises the steps of:
forming a side wall on the side surface of the first grid structure;
step six, forming a source region and a drain region on the semiconductor substrate at two sides of the first grid structure;
step seven, forming a contact etching stop layer;
step eight, forming a first interlayer film;
step nine, removing the hard mask layer, and grinding the surfaces of the first interlayer film and the contact etching stop layer to be level with the top surface of the amorphous silicon gate and exposing the top surface of the amorphous silicon gate;
step ten, removing the amorphous silicon gate;
and step eleven, forming the metal gate in the amorphous silicon gate removing area.
6. The method of manufacturing a gate electrode according to claim 5, wherein: the method further comprises the step of forming a lightly doped drain region in the semiconductor substrate on the side face of the first grid electrode structure in a self-aligned mode before forming the side wall.
7. The method of manufacturing a gate electrode according to claim 5, wherein: the semiconductor substrate includes a silicon substrate.
8. The method of manufacturing a gate electrode according to claim 7, wherein: the material of the side wall comprises silicon oxide or silicon nitride.
9. The method of manufacturing a gate electrode according to claim 7, wherein: the material of the contact etch stop layer comprises silicon nitride.
10. The method of manufacturing a gate electrode according to claim 7, wherein: the first gate dielectric layer further comprises an interface layer, and the interface layer is located between the high dielectric constant layer and the semiconductor substrate.
11. The method of manufacturing a gate electrode according to claim 10, wherein: the material of the interface layer comprises silicon oxide.
12. The method of manufacturing a gate electrode according to claim 4, wherein: the material of the high dielectric constant layer comprises hafnium oxide.
13. The method of manufacturing a gate electrode according to claim 10, wherein: the gate dielectric layer also includes a bottom barrier layer between the high dielectric constant layer and the metal gate.
14. The method of manufacturing a gate electrode of claim 13, wherein: the bottom barrier layer composition material comprises titanium nitride.
15. The method of manufacturing a gate electrode according to claim 4, wherein: the metal gate includes a work function layer and a metal conductive material layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011201919.9A CN112382564B (en) | 2020-11-02 | 2020-11-02 | Method for manufacturing grid electrode |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011201919.9A CN112382564B (en) | 2020-11-02 | 2020-11-02 | Method for manufacturing grid electrode |
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| Publication Number | Publication Date |
|---|---|
| CN112382564A CN112382564A (en) | 2021-02-19 |
| CN112382564B true CN112382564B (en) | 2024-01-19 |
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| KR20060064890A (en) * | 2004-12-09 | 2006-06-14 | 주식회사 하이닉스반도체 | Method for forming semiconductor devices |
| CN103681274A (en) * | 2012-09-12 | 2014-03-26 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103854984A (en) * | 2012-12-03 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of back gate process dummy gate and back gate process dummy gate |
| CN104103505A (en) * | 2013-04-10 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming gate electrode |
| CN109065445A (en) * | 2018-07-13 | 2018-12-21 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate structure |
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| JP2009302116A (en) * | 2008-06-10 | 2009-12-24 | Toshiba Corp | Semiconductor device and method of fabricating it |
| DE102009006801B4 (en) * | 2009-01-30 | 2011-05-19 | Amd Fab 36 Limited Liability Company & Co. Kg | A method of fabricating a field effect short channel transistor having less length fluctuation by using an amorphous electrode material during implantation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20060064890A (en) * | 2004-12-09 | 2006-06-14 | 주식회사 하이닉스반도체 | Method for forming semiconductor devices |
| CN103681274A (en) * | 2012-09-12 | 2014-03-26 | 中国科学院微电子研究所 | Semiconductor device manufacturing method |
| CN103854984A (en) * | 2012-12-03 | 2014-06-11 | 中国科学院微电子研究所 | Manufacturing method of back gate process dummy gate and back gate process dummy gate |
| CN104103505A (en) * | 2013-04-10 | 2014-10-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming gate electrode |
| CN109065445A (en) * | 2018-07-13 | 2018-12-21 | 上海华力集成电路制造有限公司 | The manufacturing method of metal gate structure |
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