CN112380801B - Online FPGA (field programmable gate array) experimental platform using multiple FPGA chips in hybrid mode and application method thereof - Google Patents
Online FPGA (field programmable gate array) experimental platform using multiple FPGA chips in hybrid mode and application method thereof Download PDFInfo
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- 238000013461 design Methods 0.000 claims abstract description 18
- 230000002093 peripheral effect Effects 0.000 claims description 44
- 238000004364 calculation method Methods 0.000 claims description 23
- 238000004088 simulation Methods 0.000 claims description 16
- 238000012544 monitoring process Methods 0.000 claims description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/61—Installation
Abstract
The invention discloses an online FPGA experiment platform using a plurality of FPGA chips in a mixed mode and an application method thereof. Therefore, when an online FPGA experiment platform hardware system is built, various types of FPGA chips can be utilized to a great extent, and the acquisition cost is reduced; when the hardware system of the online FPGA experiment platform is upgraded, the novel FPGA chip can be conveniently expanded. When the FPGA chip is used by a user, the differences of interface pins and the like of various FPGA chips and development boards are not required to be known in detail, and the FPGA development environment and tool chain software are not required to be installed locally, so that the use threshold is reduced; the computing server completes the comprehensive task of circuit design, and compared with the personal computer, the comprehensive speed is obviously improved.
Description
Technical Field
The invention relates to the technical field of online experimental platforms, in particular to an online FPGA experimental platform using a plurality of FPGA chips in a mixed mode and an application method thereof.
Background
The FPGA chip and the development board are mainly applied to the field of digital circuit design. The usual FPGA development needs to install a circuit comprehensive software eda tool of a chip manufacturer on a personal computer of a developer, simulate the circuit comprehensive software eda tool on the personal computer, and download a line burning writing throttling file to an FPGA development board for an adjustable experiment.
The general process of FPGA development requires each developer to have an FPGA development board, downloading lines, requiring the developers to be familiar with the chip model in advance, and connecting the peripheral of the development board; the eda tool requires higher hardware configuration of the personal computer, and the setting process of the installation tool environment is also complicated.
Disclosure of Invention
The invention aims to provide an online FPGA experiment platform using a plurality of FPGA chips in a mixed manner and an application method thereof, wherein the plurality of FPGA chips and development boards are used in a mixed manner when a platform system is constructed, so that the construction cost of newly purchased FPGA chips and development boards is saved; meanwhile, when the FPGA chip is used, a user does not need to know differences of interface pins of various FPGA chips, development boards and the like in detail; the FPGA development environment and tool chain software are not required to be installed locally, and the use and the debugging are convenient and flexible.
The invention aims at realizing the following technical scheme:
an online FPGA experiment platform application method for mixed use of a plurality of FPGA chips comprises the following steps:
receiving relevant circuit design program codes edited by a user aiming at FPGA experimental equipment and relevant virtual peripherals selected by the user;
simulating the circuit design program code, if the simulation result meets the expected requirement, comprehensively compiling the circuit design program code, and obtaining and storing a corresponding byte stream file when the comprehensive compiling is successful;
when a user uses a real download experiment function, FPGA experiment equipment is distributed to the user, corresponding byte stream files are programmed into an FPGA chip through a singlechip of the FPGA experiment equipment, and the singlechip is controlled by combining with virtual peripherals selected by the user to complete signal read-write direction configuration; and then, receiving signals generated when the user operates the virtual peripheral, converting the signals through the singlechip, generating corresponding output signals through the FPGA chip, and feeding back the corresponding output signals to the user.
An on-line FPGA experiment platform using a plurality of FPGA chips in combination, comprising: the system comprises a front-end server, a management server, a storage server, a calculation server and a plurality of FPGA experimental devices; wherein:
the front-end server is used for providing website services of an online FPGA experiment platform, and comprises: providing an editing area of circuit design program codes and a virtual peripheral selection area for a user, transmitting the received information to a calculation server, and receiving and displaying a simulation result and a comprehensive compiling result fed back by the calculation server; the device is also used for displaying output signals generated by the FPGA chip when a user uses a real download experiment function;
the management server is used for detecting and monitoring the states of all the FPGA experimental devices and distributing or recycling the FPGA experimental devices for users;
the calculation server is used for simulating the circuit design program codes, if the simulation result meets the expected requirement, the circuit design program codes are compiled comprehensively, and when the comprehensive compilation is successful, a corresponding byte stream file is obtained; the method is also used for distributing FPGA experimental equipment for a user when the user uses a real download experimental function, programming a corresponding byte stream file to an FPGA chip through a singlechip of the FPGA experimental equipment, and controlling the singlechip to complete signal read-write direction configuration by combining with a virtual peripheral selected by the user;
the storage server is used for storing the related information of each FPGA experimental device and the byte stream file;
each FPGA experimental apparatus includes: the singlechip and the FPGA chip; the singlechip burns the byte stream file to the FPGA chip under the control of the calculation server, collects signals generated when a user operates the virtual peripheral, converts the signals and sends the converted signals to the FPGA chip, and collects output signals generated by the FPGA chip.
According to the technical scheme provided by the invention, the on-line FPGA experiment platform can be built by mixing a plurality of FPGA chips and development boards, and the types of the FPGA chips can be different from the types of the input and output wires. Therefore, when an online FPGA experiment platform hardware system is built, various types of FPGA chips can be utilized to a great extent, and the acquisition cost is reduced; when the hardware system of the online FPGA experiment platform is upgraded, the novel FPGA chip can be conveniently expanded. When the FPGA chip is used by a user, the differences of interface pins and the like of various FPGA chips and development boards are not required to be known in detail, and the FPGA development environment and tool chain software are not required to be installed locally, so that the use threshold is reduced; the computing server completes the comprehensive task of circuit design, and compared with the personal computer, the comprehensive speed is obviously improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of an online FPGA experiment platform application method using multiple FPGA chips in a mixed manner, which is provided by an embodiment of the invention;
fig. 2 is a schematic diagram of a front-end server display interface according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an online FPGA experimental platform using multiple FPGA chips in a hybrid manner according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides an online FPGA experiment platform application method for mixed use of a plurality of FPGA chips, which mainly comprises the following steps as shown in figure 1:
1. and receiving relevant circuit design program codes edited by a user aiming at the FPGA experimental equipment and relevant virtual peripherals selected by the user.
In the embodiment of the invention, the FPGA experimental equipment can be selected by a user or can be allocated by a system at will.
In the embodiment of the invention, a user edits related circuit design codes in a code editing area displayed by a front-end server of an experiment platform, and selects related virtual peripheral equipment in an area for peripheral equipment displayed by the front-end server to complete a connection design; fig. 2 is a schematic diagram of a front-end server presentation interface (web page interface).
It will be appreciated by those skilled in the art that various editing areas involved in the web interface, as well as various information presentation areas mentioned later, may be provided in the same or different pages for presentation to the user at various stages according to the relevant signals; in addition, the location area and the size of the related function buttons in the web interface can be set by themselves, different functions can be triggered by different buttons, and also can be integrated in the same button, for example, the integrated compiling and the burning are integrated in one button (for example, the integrated burning button in fig. 2).
Those skilled in the art will understand that selecting a relevant virtual peripheral to complete the connection design refers to completing the connection between the FPGA chip and the experimental peripheral, and specifically, the connection design may be completed in a page in a drawing manner.
2. And simulating the circuit design program code, if the simulation result meets the expected requirement, comprehensively compiling the circuit design program code, and obtaining and storing a corresponding byte stream file when the comprehensive compiling is successful.
In the embodiment of the invention, the simulation is realized on the calculation server of the experiment platform, the simulation mode can be realized by a conventional technology, the simulation result can comprise a waveform chart and the like, and the simulation result is presented to the user through the display interface of the front-end server. If the simulation result does not meet the expected requirement, the program code is described as having a problem, and therefore the code needs to be modified until the simulation result meets the expected requirement, and then comprehensive compiling is performed.
In the embodiment of the invention, the comprehensive compiling is realized in the computing server of the experimental platform, the computing server carries out the comprehensive compiling according to the circuit design program codes transmitted by the front-end server, and the comprehensive compiling mode can be realized by a conventional technology. The information received by the computing server at this stage includes: the user information, the chip model of the FPGA experimental equipment, the circuit design program code and the virtual peripheral equipment adopt the wiring data. The information format may be expressed as:
< user information >
< chip model of FPGA Experimental device >
< Circuit design program code >
< virtual peripheral device selected wire data >
If the circuit design program code has errors, the information of compiling failure is fed back to a user, wherein the information comprises the following steps: error information 1, code line number causing error 1, error information 2, code line number causing error 2, …; alarm information 1, code line number to cause alarm 1, alarm information 2, code line number to cause alarm 2, …. The ellipses herein refer to that the number of error messages and alarm messages is uncertain, and the following expression forms also express the same meaning according to actual situations.
The information format of the user compiling failure can be expressed as:
< compilation failure >
< error message 1>
< code line number causing error 1>
< error message 2>
< code line number causing error 2>
……
< warning information 1>
< code line number to cause Warning 1>
< warning message 2>
< code line number to cause Warning 2>
The user modifies the errors in the circuit design program code and then performs comprehensive compiling.
If the circuit design program code has no error, the comprehensive compiling is successful, and the corresponding byte stream file can be obtained at the moment.
Of course, if the compiling is successful, an alarm may be generated to prompt potential design problems, such as that some wires are not used, some designs are relatively costly in resources, some signals are truncated, etc.; the information fed back to the user at this time includes: alarm information 1, code line number to cause alarm 1, alarm information 2, code line number to cause alarm 2, ….
The relevant information format can be expressed as:
< success of compilation >
< warning information 1>
< code line number to cause Warning 1>
< warning message 2>
< code line number to cause Warning 2>
At this time, the user can adjust the circuit design program code according to the actual situation, and if the adjustment is performed, the integrated compiling can be performed again to obtain a new byte stream file.
In the embodiment of the invention, the information in the byte stream file comprises: the method comprises the steps of selecting connection data for user information, a chip model of FPGA experimental equipment and virtual peripherals, and comprehensively compiling byte stream file data obtained by compiling, wherein the format is expressed as follows:
< user information >
< chip model of FPGA Experimental device >
< virtual peripheral device selected wire data >
< byte stream File data obtained by compilation >
3. When a user uses a real download experiment function, FPGA experiment equipment is distributed to the user, corresponding byte stream files (namely, obtained by comprehensively compiling in the mode described above) are programmed into an FPGA chip through a singlechip of the FPGA experiment equipment, and the singlechip is controlled by combining with a virtual peripheral selected by the user to complete signal read-write direction configuration; and then, receiving signals generated when the user operates the virtual peripheral, converting the signals through the singlechip, generating corresponding output signals through the FPGA chip, and feeding back the corresponding output signals to the user.
In this step, the information related to completing the signal read-write direction configuration includes: virtual peripheral 1, input node, output interface, virtual peripheral 2, input node, output interface, …; the format of the information can be expressed as:
< virtual peripheral 1>
< input interface >
< output interface >
< virtual peripheral device 2>
< input interface >
< output interface >
……
In the embodiment of the invention, the user operates the virtual peripheral through the webpage interface provided by the front-end server, and the area division mode, the display mode and the like of the webpage interface can be designed according to actual conditions.
Another embodiment of the present invention further provides an online FPGA experimental platform using a plurality of FPGA chips in a mixed manner, as shown in fig. 3, which mainly includes: the system comprises a front-end server, a management server, a calculation server, a storage server and a plurality of FPGA experimental devices; wherein:
1) The front-end server is used for providing website services of an online FPGA experiment platform, and comprises: providing an editing area of circuit design program codes and a virtual peripheral selection area for a user, transmitting the editing area and the virtual peripheral selection area to a calculation server, and receiving and displaying simulation results and comprehensive compiling results fed back by the calculation server; and the device is also used for displaying output signals generated by the FPGA chip when a user uses the real download experiment function.
The front-end server can also provide experimental debugging functions and the like, and in addition, the front-end server needs to stably run website server software and needs to access a large network bandwidth, and a typical network bandwidth is that 1mbps is used for each user on average.
2) The management server is used for detecting and monitoring the states of all the FPGA experimental devices, and can also provide restarting and stopping functions and the functions of distributing or recycling the FPGA experimental devices for users.
The management server needs to stably run equipment detection management software, can detect the state of the FPGA experimental equipment, and can attempt restarting and reconnecting when the FPGA experimental equipment is stopped accidentally.
3) The calculation server is used for simulating the circuit design program codes, if the simulation result meets the expected requirement, the circuit design program codes are compiled comprehensively, and when the comprehensive compilation is successful, a corresponding byte stream file is obtained; and the system is also used for distributing FPGA experimental equipment for the user when the user uses the real download experimental function, programming the corresponding byte stream file to the FPGA chip through a singlechip of the FPGA experimental equipment, and controlling the singlechip to complete signal read-write direction configuration by combining with a virtual peripheral selected by the user.
Because the calculation server is required to complete the comprehensive compiling task of the FPGA chip corresponding to the user circuit design and complete the analog simulation task of the FPGA chip corresponding to the user circuit design, larger calculation force support is required, and a typical calculation force requirement is an average 4-8cpu calculation core and 2-4GB memory when the calculation server is used by each user.
4) The storage server is used for storing relevant information (such as equipment signals) of each FPGA experimental equipment and byte stream files.
In practice, the storage server may store various pieces of information required for running the process, such as user information, engineering and design codes, etc., as needed. The storage server needs to have a large capacity of fast stable storage space, and a typical storage quota is 400MB of data per user on average.
5) Each FPGA experimental apparatus includes: the singlechip and the FPGA chip; the singlechip burns the byte stream file to the FPGA chip under the control of the calculation server, collects signals generated when a user operates the virtual peripheral, converts the signals and sends the converted signals to the FPGA chip, and collects output signals generated by the FPGA chip.
In the embodiment of the invention, the FPGA experimental equipment can support various common FPGA chips and development boards. The right side of fig. 3 shows various experimental facilities.
The working flow of the experimental platform is described in detail in the previous experimental method introduction, so that the description is omitted.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional modules is illustrated, and in practical application, the above-mentioned functional allocation may be performed by different functional modules according to needs, i.e. the internal structure of the experimental platform is divided into different functional modules, so as to perform all or part of the functions described above.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (4)
1. An online FPGA experiment platform application method for mixedly using a plurality of FPGA chips is characterized by comprising the following steps:
receiving relevant circuit design program codes edited by a user aiming at FPGA experimental equipment and relevant virtual peripherals selected by the user;
simulating the circuit design program code, if the simulation result meets the expected requirement, comprehensively compiling the circuit design program code, and obtaining and storing a corresponding byte stream file when the comprehensive compiling is successful;
when a user uses a real download experiment function, FPGA experiment equipment is distributed to the user, corresponding byte stream files are programmed into an FPGA chip through a singlechip of the FPGA experiment equipment, and the singlechip is controlled by combining with virtual peripherals selected by the user to complete signal read-write direction configuration; then, receiving signals generated when a user operates the virtual peripheral, converting the signals through the singlechip, generating corresponding output signals through the FPGA chip, and feeding back the corresponding output signals to the user;
if the circuit design program code has errors, the information of compiling failure is fed back to a user, wherein the information comprises the following steps: error information 1, code line number causing error 1, error information 2, code line number causing error 2, …; alarm information 1, code line number for causing alarm 1, alarm information 2, code line number for causing alarm 2, …; if the circuit design program code has no error, the comprehensive compiling is successful, and a corresponding byte stream file is obtained;
when the comprehensive compiling is successful, if the design problem exists in the circuit design program code design, corresponding warning is generated, and the information fed back to the user comprises: alarm information 1, code line number for causing alarm 1, alarm information 2, code line number for causing alarm 2, …;
the information in the byte stream file includes: user information, the chip model of FPGA experimental equipment, the connection data selected by the virtual peripheral equipment and byte stream file data obtained by comprehensive compiling;
the information related to the completion of the signal read-write direction configuration includes: virtual peripheral 1, input node, output interface, …, virtual peripheral t, input node, output interface; wherein t is the number of virtual peripherals.
2. The method for applying the online FPGA experimental platform by using the multiple FPGA chips in a mixed mode according to claim 1, wherein a user edits related circuit design codes in a code editing area displayed by a front-end server of the experimental platform, and selects related virtual peripherals in an area for peripheral display of the front-end server to complete the online design.
3. The method for applying the online FPGA experimental platform by using a plurality of FPGA chips in a mixed mode according to claim 1, wherein the comprehensive compiling is realized in a calculation server of the experimental platform, and the information received by the calculation server comprises the following steps: the user information, the chip model of the FPGA experimental equipment, the circuit design program code and the virtual peripheral equipment adopt the wiring data.
4. An online FPGA experiment platform using a plurality of FPGA chips in combination, comprising: the system comprises a front-end server, a management server, a storage server, a calculation server and a plurality of FPGA experimental devices; wherein:
the front-end server is used for providing website services of an online FPGA experiment platform, and comprises: providing an editing area of circuit design program codes and a virtual peripheral selection area for a user, transmitting the received information to a calculation server, and receiving and displaying a simulation result and a comprehensive compiling result fed back by the calculation server; the device is also used for displaying output signals generated by the FPGA chip when a user uses a real download experiment function;
the management server is used for detecting and monitoring the states of all the FPGA experimental devices and distributing or recycling the FPGA experimental devices for users;
the calculation server is used for simulating the circuit design program codes, if the simulation result meets the expected requirement, the circuit design program codes are compiled comprehensively, and when the comprehensive compilation is successful, a corresponding byte stream file is obtained; the method is also used for distributing FPGA experimental equipment for a user when the user uses a real download experimental function, programming a corresponding byte stream file to an FPGA chip through a singlechip of the FPGA experimental equipment, and controlling the singlechip to complete signal read-write direction configuration by combining with a virtual peripheral selected by the user;
the storage server is used for storing the related information of each FPGA experimental device and the byte stream file;
each FPGA experimental apparatus includes: the singlechip and the FPGA chip; the singlechip burns the byte stream file to the FPGA chip under the control of the calculation server, collects signals generated when a user operates the virtual peripheral equipment, converts the signals and sends the converted signals to the FPGA chip, and collects output signals generated by the FPGA chip;
if the circuit design program code has errors, the information of compiling failure is fed back to a user, wherein the information comprises the following steps: error information 1, code line number causing error 1, error information 2, code line number causing error 2, …; alarm information 1, code line number for causing alarm 1, alarm information 2, code line number for causing alarm 2, …; if the circuit design program code has no error, the comprehensive compiling is successful, and a corresponding byte stream file is obtained;
when the comprehensive compiling is successful, if the design problem exists in the circuit design program code design, corresponding warning is generated, and the information fed back to the user comprises: alarm information 1, code line number for causing alarm 1, alarm information 2, code line number for causing alarm 2, …;
the information in the byte stream file includes: user information, the chip model of FPGA experimental equipment, the connection data selected by the virtual peripheral equipment and byte stream file data obtained by comprehensive compiling;
the information related to the completion of the signal read-write direction configuration includes: virtual peripheral 1, input node, output interface, …, virtual peripheral t, input node, output interface; wherein t is the number of virtual peripherals.
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| CN110706537A (en) * | 2019-10-10 | 2020-01-17 | 焦作大学 | Digital circuit training platform based on virtual chip and wireless management and application method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020107678A1 (en) * | 2001-02-07 | 2002-08-08 | Chuan-Lin Wu | Virtual computer verification platform |
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| CN107562221A (en) * | 2017-08-21 | 2018-01-09 | 北京航空航天大学 | PS/2 keyboard and mouse interface online experiment methods based on FPGA online experiment platforms |
| CN110706537A (en) * | 2019-10-10 | 2020-01-17 | 焦作大学 | Digital circuit training platform based on virtual chip and wireless management and application method |
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