CN112380801A - Online FPGA experiment platform using various FPGA chips in mixed mode and application method thereof - Google Patents
Online FPGA experiment platform using various FPGA chips in mixed mode and application method thereof Download PDFInfo
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Abstract
The invention discloses an online FPGA experimental platform using various FPGA chips in a mixed manner and an application method thereof. Therefore, various types of FPGA chips can be utilized to a great extent when an online FPGA experiment platform hardware system is built, and the acquisition cost is reduced; when the hardware system of the online FPGA experiment platform is upgraded, the novel FPGA chip can be conveniently expanded. When the FPGA development system is used, a user does not need to know differences of interface pins and the like of various FPGA chips and development boards in detail and install FPGA development environment and tool chain software locally, so that the use threshold is reduced; the computing server completes the comprehensive task of circuit design, and compared with a personal computer, the comprehensive speed is obviously improved.
Description
Technical Field
The invention relates to the technical field of online experiment platforms, in particular to an online FPGA experiment platform using various FPGA chips in a mixed manner and an application method thereof.
Background
The FPGA chip and the development board are mainly applied to the field of digital circuit design. In general FPGA development, a circuit integrated software eda tool of a chip manufacturer is required to be installed on a personal computer of a developer, the eda tool is used on the personal computer for simulation, and byte stream files are written into an FPGA development board through a download line for up-regulation experiment.
The common flow for FPGA development requires that each developer has an FPGA development board and a download line, and the developers need to be familiar with the conditions of chip models, peripheral connection of the development boards and the like in advance; the eda tool requires higher hardware to configure the pc, and the setup process of the installation tool environment is also more complicated.
Disclosure of Invention
The invention aims to provide an online FPGA experimental platform using various FPGA chips in a mixed manner and an application method thereof, wherein various FPGA chips and development boards are used in a mixed manner when a platform system is constructed, so that the construction cost of newly purchased FPGA chips and development boards is saved; meanwhile, when the FPGA chip is used by a user, the differences of interface pins and the like of various FPGA chips and development boards do not need to be known in detail; FPGA development environment and tool chain software do not need to be installed locally, and the use and debugging are convenient and flexible.
The purpose of the invention is realized by the following technical scheme:
an application method of an online FPGA experiment platform using various FPGA chips in a mixed manner comprises the following steps:
receiving relevant circuit design program codes edited by a user aiming at the FPGA experimental equipment and relevant virtual peripheral equipment selected by the user;
simulating the circuit design program code, if the simulation result meets the expected requirement, comprehensively compiling the circuit design program code, and obtaining and storing a corresponding byte stream file when the comprehensive compilation is successful;
when a user uses a real downloading experiment function, FPGA experiment equipment is distributed to the user, a corresponding byte stream file is programmed to an FPGA chip through a single chip microcomputer of the FPGA experiment equipment, and the single chip microcomputer is controlled to complete signal reading and writing direction configuration by combining with a virtual peripheral selected by the user; and then, receiving a signal generated when the user operates the virtual peripheral, converting the signal by the singlechip, generating a corresponding output signal by the FPGA chip, and feeding back the corresponding output signal to the user.
An online FPGA experiment platform for mixed use of multiple FPGA chips comprises: the system comprises a front-end server, a management server, a storage server, a calculation server and a plurality of FPGA experimental devices; wherein:
the front-end server is used for providing website services of the online FPGA experiment platform, and comprises: providing an editing area of a circuit design program code and a virtual peripheral selection area for a user, sending received information to a computing server, and receiving and displaying a simulation result and a comprehensive compiling result fed back by the computing server; the FPGA chip is also used for displaying an output signal generated by the FPGA chip when a user uses a real downloading experiment function;
the management server is used for detecting and monitoring the state of each FPGA experimental device and distributing or recycling the FPGA experimental device for a user;
the calculation server is used for simulating the circuit design program code, comprehensively compiling the circuit design program code if a simulation result meets an expected requirement, and obtaining a corresponding byte stream file when the comprehensive compilation is successful; the system is also used for distributing FPGA experimental equipment to a user when the user uses a real downloading experimental function, programming a corresponding byte stream file to an FPGA chip through a singlechip of the FPGA experimental equipment, and controlling the singlechip to complete signal read-write direction configuration by combining with a virtual peripheral selected by the user;
the storage server is used for storing relevant information of each FPGA experimental device and byte stream files;
each FPGA experimental device comprises: the single chip microcomputer and the FPGA chip; the single chip microcomputer writes the byte stream file to the FPGA chip under the control of the computing server, collects signals generated when a user operates the virtual peripheral, converts the signals and transmits the signals to the FPGA chip, and collects output signals generated by the FPGA chip.
According to the technical scheme provided by the invention, various FPGA chips and development boards can be used in a mixed manner to build an online FPGA experimental platform, and the types of the FPGA chips and input and output connecting lines can be different. Therefore, various types of FPGA chips can be utilized to a great extent when an online FPGA experiment platform hardware system is built, and the acquisition cost is reduced; when the hardware system of the online FPGA experiment platform is upgraded, the novel FPGA chip can be conveniently expanded. When the FPGA development system is used, a user does not need to know differences of interface pins and the like of various FPGA chips and development boards in detail and install FPGA development environment and tool chain software locally, so that the use threshold is reduced; the computing server completes the comprehensive task of circuit design, and compared with a personal computer, the comprehensive speed is obviously improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a flowchart of an application method of an online FPGA experiment platform using multiple FPGA chips in a mixed manner according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a front-end server display interface according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an online FPGA experimental platform using multiple FPGA chips in a mixed manner according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention provides an application method of an online FPGA experimental platform using various FPGA chips in a mixed manner, which mainly comprises the following steps of:
1. and receiving related circuit design program codes edited by a user aiming at the FPGA experimental equipment and related virtual peripherals selected by the user.
In the embodiment of the invention, the FPGA experimental equipment can be selected by a user and can also be randomly distributed by the system.
In the embodiment of the invention, a user edits related circuit design codes in a code editing area displayed by a front-end server of an experiment platform, and selects related virtual peripherals to complete connection design in a peripheral selection area displayed by the front-end server; fig. 2 is a schematic diagram of a front-end server display interface (web interface).
Those skilled in the art can understand that various editing areas related in the website interface and various information display areas mentioned later can be set in the same page or different pages, and are displayed to the user according to the related signals at various stages; in addition, the position area and size of the related function button in the web interface can be set by itself, different functions can be triggered by different buttons, or the functions can be integrated into the same button, for example, the integrated compiling and burning can be integrated into one button (for example, the integrated burning button in fig. 2).
The technical personnel in the field can understand that the selection of the related virtual peripheral to complete the wiring design refers to the completion of the wiring of the FPGA chip and the experimental peripheral, and particularly, the wiring design can be completed in a drawing mode in a page.
2. And simulating the circuit design program code, if the simulation result meets the expected requirement, comprehensively compiling the circuit design program code, and obtaining and storing a corresponding byte stream file when the comprehensive compilation is successful.
In the embodiment of the invention, the simulation is realized on the computing server of the experimental platform, the simulation mode can be realized by the conventional technology, the simulation result can comprise a oscillogram and the like, and the simulation result is presented to a user through a front-end server display interface. If the simulation result does not meet the expected requirement, the problem of the program code is shown, so the code needs to be modified until the simulation result meets the expected requirement, and then comprehensive compilation is carried out.
In the embodiment of the invention, the comprehensive compilation is realized in the computing server of the experimental platform, the computing server carries out the comprehensive compilation according to the circuit design program code transmitted by the front-end server, and the comprehensive compilation mode can be realized by the conventional technology. The information received by the computing server at this stage includes: user information, the chip model of the FPGA experimental equipment, circuit design program codes and virtual peripheral optional connecting line data. The information format may be expressed as:
< subscriber information >
< chip model of FPGA Experimental Equipment >
< Circuit design program code >
< virtual peripheral device selection connection data >
If the circuit design program code has errors, the information of compiling failure is fed back to a user, and the information comprises: error message 1, error 1 causing code line number, error message 2, error 2 causing code line number, …; alarm information 1, code line number causing alarm 1, alarm information 2, code line number causing alarm 2, …. The ellipses here mean that the numbers of error messages and warning messages are uncertain, and the following expressions also have the same meaning, which is specifically considered according to the actual situation.
The format of the information of the user compiling failure can be expressed as:
< compilation failure >
< error message 1>
< code line number causing error 1>
< error message 2>
< code line number causing error 2>
……
< Warning information 1>
< code line number causing Warning 1>
< Warning information 2>
< code line number causing Warning 2>
And modifying errors in the circuit design program codes by a user and then performing comprehensive compilation.
If the circuit design program code has no error, the comprehensive compilation is successful, and the corresponding byte stream file can be obtained at the moment.
Of course, a warning may also be generated when compiling is successful, which prompts potential design problems, such as some connection lines are not used, some designs are relatively resource-consuming, some signals are cut off, and the like; the information fed back to the user at this time includes: alarm information 1, code line number causing alarm 1, alarm information 2, code line number causing alarm 2, ….
The relevant information format can be expressed as:
< success of compilation >
< Warning information 1>
< code line number causing Warning 1>
< Warning information 2>
< code line number causing Warning 2>
At this time, the user can adjust the circuit design program code according to the actual situation, and if the adjustment is made, the comprehensive compilation can be carried out again to obtain a new byte stream file.
In the embodiment of the present invention, the information in the byte stream file includes: user information, the chip model of the FPGA experimental equipment, virtual peripheral optional connection data and byte stream file data obtained by comprehensive compilation, wherein the format is expressed as follows:
< subscriber information >
< chip model of FPGA Experimental Equipment >
< virtual peripheral device selection connection data >
< byte stream File data obtained by compilation >
3. When a user uses a real downloading experiment function, FPGA experiment equipment is distributed to the user, a corresponding byte stream file (obtained by comprehensive compiling in the mode introduced above) is programmed to an FPGA chip through a single chip microcomputer of the FPGA experiment equipment, and the single chip microcomputer is controlled to complete signal reading and writing direction configuration by combining with a virtual peripheral selected by the user; and then, receiving a signal generated when the user operates the virtual peripheral, converting the signal by the singlechip, generating a corresponding output signal by the FPGA chip, and feeding back the corresponding output signal to the user.
In this step, the information related to completing the signal read-write direction configuration includes: virtual peripheral 1, input node, output interface, virtual peripheral 2, input node, output interface, …; the format of the information may be expressed as:
< virtual peripheral 1>
< input interface >
< output interface >
< virtual peripheral 2>
< input interface >
< output interface >
……
In the embodiment of the invention, the virtual peripheral is operated by the user through the webpage interface provided by the front-end server, and the area division mode, the display mode and the like of the webpage interface can be designed according to the actual situation.
Another embodiment of the present invention further provides an online FPGA experimental platform using a plurality of FPGA chips in a mixed manner, as shown in fig. 3, which mainly includes: the system comprises a front-end server, a management server, a calculation server, a storage server and a plurality of FPGA experimental devices; wherein:
1) the front-end server is used for providing website services of the online FPGA experiment platform, and comprises: providing an editing area of a circuit design program code and a virtual peripheral selection area for a user, sending the editing area and the virtual peripheral selection area to a computing server, and receiving and displaying a simulation result and a comprehensive compiling result fed back by the computing server; and the display module is also used for displaying the output signal generated by the FPGA chip when the user uses the real downloading experiment function.
The front-end server can also provide an experiment debugging function and the like, in addition, the front-end server needs to stably run website server software and needs to access a larger network bandwidth, and a typical network bandwidth is 1mbps used by each user on average.
2) And the management server is used for detecting and monitoring the state of each FPGA experimental device, and also can provide the functions of restarting and stopping, and distributing or recycling the FPGA experimental devices for users.
The management server needs to stably run the equipment detection management software, can detect the state of the FPGA experimental equipment, and can try to restart reconnection when the FPGA experimental equipment is terminated accidentally.
3) The calculation server is used for simulating the circuit design program code, comprehensively compiling the circuit design program code if a simulation result meets an expected requirement, and obtaining a corresponding byte stream file when the comprehensive compilation is successful; and when the user uses the real downloading experiment function, the FPGA experiment equipment is distributed to the user, the corresponding byte stream file is programmed to the FPGA chip through the singlechip of the FPGA experiment equipment, and the singlechip is controlled by combining the virtual peripheral selected by the user to complete the signal reading and writing direction configuration.
Because the computation server needs to complete the comprehensive compiling task of the FPGA chip corresponding to the user circuit design and the analog simulation task of the FPGA chip corresponding to the user circuit design, a large computational effort support is needed, and a typical computational effort requirement is that an average 4-8cpu computation core and a 2-4GB memory are used by each user.
4) The storage server is used for storing relevant information (such as equipment signals) of each FPGA experimental equipment and byte stream files.
In fact, the storage server can store various information required by the running process, such as user information, engineering and design codes and the like, according to needs. The storage server needs to have a large amount of fast and stable storage space, and a typical storage quota is 400MB of data per user on average.
5) Each FPGA experimental device comprises: the single chip microcomputer and the FPGA chip; the single chip microcomputer writes the byte stream file to the FPGA chip under the control of the computing server, collects signals generated when a user operates the virtual peripheral, converts the signals and transmits the signals to the FPGA chip, and collects output signals generated by the FPGA chip.
In the embodiment of the invention, the FPGA experimental equipment can support various common FPGA chips and development boards. The right side of fig. 3 shows various experimental equipment.
The working process of the experimental platform is described in detail in the introduction of the experimental method, and thus, the detailed description is omitted.
It can be clearly understood by those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the foregoing function distribution may be completed by different functional modules according to needs, that is, the internal structure of the experimental platform is divided into different functional modules to complete all or part of the above-described functions.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. An application method of an online FPGA experiment platform using various FPGA chips in a mixed manner is characterized by comprising the following steps:
receiving relevant circuit design program codes edited by a user aiming at the FPGA experimental equipment and relevant virtual peripheral equipment selected by the user;
simulating the circuit design program code, if the simulation result meets the expected requirement, comprehensively compiling the circuit design program code, and obtaining and storing a corresponding byte stream file when the comprehensive compilation is successful;
when a user uses a real downloading experiment function, FPGA experiment equipment is distributed to the user, a corresponding byte stream file is programmed to an FPGA chip through a single chip microcomputer of the FPGA experiment equipment, and the single chip microcomputer is controlled to complete signal reading and writing direction configuration by combining with a virtual peripheral selected by the user; and then, receiving a signal generated when the user operates the virtual peripheral, converting the signal by the singlechip, generating a corresponding output signal by the FPGA chip, and feeding back the corresponding output signal to the user.
2. The method as claimed in claim 1, wherein a user edits relevant circuit design codes in a code editing area displayed by a front-end server of the experiment platform, and selects relevant virtual peripherals in a peripheral selection area displayed by the front-end server to complete a wiring design.
3. The method as claimed in claim 1, wherein the comprehensive compilation is implemented in a computing server of the experiment platform, and the information received by the computing server includes: user information, the chip model of the FPGA experimental equipment, circuit design program codes and virtual peripheral optional connecting line data.
4. The method for applying the on-line FPGA experiment platform by using multiple FPGA chips in a mixed way according to claim 1,
if the circuit design program code has errors, the information of compiling failure is fed back to a user, and the information comprises: error message 1, error 1 causing code line number, error message 2, error 2 causing code line number, …; alarm information 1, code line number causing alarm 1, alarm information 2, code line number causing alarm 2, …;
if the circuit design program code has no error, the comprehensive compilation is successful, and a corresponding byte stream file is obtained.
5. The method as claimed in claim 4, wherein when the comprehensive compilation is successful, if there is a design problem in the design of the circuit design program code, a corresponding alarm is generated, and the information fed back to the user includes: alarm information 1, code line number causing alarm 1, alarm information 2, code line number causing alarm 2, ….
6. The method for applying the on-line FPGA experiment platform by mixedly using multiple FPGA chips as recited in claim 1, wherein the information in the byte stream file comprises: user information, the chip model of the FPGA experimental equipment, virtual peripheral optional connecting data and byte stream file data obtained by comprehensive compiling.
7. The method for applying the on-line FPGA experiment platform by using multiple FPGA chips in a mixed manner according to claim 1, wherein the information related to the completion of the signal read-write direction configuration comprises: virtual peripheral 1, input node, output interface …, virtual peripheral t, input node, output interface; wherein t is the number of virtual peripherals.
8. The utility model provides an online FPGA experiment platform that uses multiple FPGA chip in mixture which characterized in that includes: the system comprises a front-end server, a management server, a storage server, a calculation server and a plurality of FPGA experimental devices; wherein:
the front-end server is used for providing website services of the online FPGA experiment platform, and comprises: providing an editing area of a circuit design program code and a virtual peripheral selection area for a user, sending received information to a computing server, and receiving and displaying a simulation result and a comprehensive compiling result fed back by the computing server; the FPGA chip is also used for displaying an output signal generated by the FPGA chip when a user uses a real downloading experiment function;
the management server is used for detecting and monitoring the state of each FPGA experimental device and distributing or recycling the FPGA experimental device for a user;
the calculation server is used for simulating the circuit design program code, comprehensively compiling the circuit design program code if a simulation result meets an expected requirement, and obtaining a corresponding byte stream file when the comprehensive compilation is successful; the system is also used for distributing FPGA experimental equipment to a user when the user uses a real downloading experimental function, programming a corresponding byte stream file to an FPGA chip through a singlechip of the FPGA experimental equipment, and controlling the singlechip to complete signal read-write direction configuration by combining with a virtual peripheral selected by the user;
the storage server is used for storing relevant information of each FPGA experimental device and byte stream files;
each FPGA experimental device comprises: the single chip microcomputer and the FPGA chip; the single chip microcomputer writes the byte stream file to the FPGA chip under the control of the computing server, collects signals generated when a user operates the virtual peripheral, converts the signals and transmits the signals to the FPGA chip, and collects output signals generated by the FPGA chip.
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Citations (3)
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| US20020107678A1 (en) * | 2001-02-07 | 2002-08-08 | Chuan-Lin Wu | Virtual computer verification platform |
| CN107562221A (en) * | 2017-08-21 | 2018-01-09 | 北京航空航天大学 | PS/2 keyboard and mouse interface online experiment methods based on FPGA online experiment platforms |
| CN110706537A (en) * | 2019-10-10 | 2020-01-17 | 焦作大学 | Digital circuit training platform based on virtual chip and wireless management and application method |
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2020
- 2020-12-03 CN CN202011414511.XA patent/CN112380801B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020107678A1 (en) * | 2001-02-07 | 2002-08-08 | Chuan-Lin Wu | Virtual computer verification platform |
| CN107562221A (en) * | 2017-08-21 | 2018-01-09 | 北京航空航天大学 | PS/2 keyboard and mouse interface online experiment methods based on FPGA online experiment platforms |
| CN110706537A (en) * | 2019-10-10 | 2020-01-17 | 焦作大学 | Digital circuit training platform based on virtual chip and wireless management and application method |
Non-Patent Citations (1)
| Title |
|---|
| 周佳晖;杜世民;杨润萍;殷金曙;: "基于Proteus和FPGA的"虚实结合"的数字电路综合实验研究", 无线通信技术, no. 01 * |
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