CN112380084B - Fault injection and simulation verification method - Google Patents
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Abstract
The invention discloses a fault injection and simulation verification method, which comprises the steps of establishing a signal flow model, analyzing the signal flow model to obtain a dependency matrix of a system, analyzing the signal flow model to obtain a fault tree model, and carrying out logical reasoning and state simulation on the signal flow model to obtain the state of the system; and performing fault input on the signal flow model to acquire state data of the system. The invention can find out weak links of the electronic system to typical fault recognition, find out indexes such as fault detection rate, fault isolation rate and the like of the complex electronic system, and is used for improving and optimizing the test diagnosis design scheme of the electronic system and improving the usability and reliability of the diagnosis system.
Description
Technical Field
The invention relates to the field of data processing, in particular to a fault injection and simulation verification method.
Background
The traditional electronic system cannot respond to real faults in a multi-working mode and a working state, and cannot find out the position of a weak link, so that the usability and the reliability of the electronic system are affected.
Disclosure of Invention
The invention provides a fault injection and simulation verification method for solving the problems.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a fault injection and simulation verification method.
Optionally, a signal flow model is established, the signal flow model is analyzed to obtain a dependency matrix of the system, the signal flow model is analyzed to obtain a fault tree model, and the signal flow model is subjected to logic reasoning and state simulation to obtain the state of the system;
and performing fault input on the signal flow model to acquire state data of the system.
Optionally, the signal flow model includes a component node, a test point node, an AND node, AND a switch node, AND the input structure model, the schematic diagram, or the conceptual block diagram generates the test signal.
Optionally, the analyzing the signal flow model to obtain the dependency matrix of the system includes: dividing the system into a top system and each level of subsystems according to functions, carrying out layered operation on the reachability matrixes of each level of subsystems and each system level, combining the dependency matrixes of each level of subsystems layer by layer in sequence to obtain the dependency matrix of the top system, transmitting the dependency matrix to a model analysis module, finding the relation between a test signal and a fault source in the model analysis module, and determining the type and the point position of the fault.
Optionally, the analyzing the signal flow model to obtain the fault tree model includes: abstracting the fault tree into five classes of objects, wherein the five classes of objects are respectively: the method comprises the steps of a bottom event, a result event, a top event, an intermediate event and a logic gate, wherein the top event represents faults or risks, a cut set and a minimum cut set are determined, a structural function is generated according to the structure of a fault tree, the structural function is expanded and simplified in a Boolean operation mode to be in a form with the sum of minimum term products, each minimum term is the minimum cut set, the relation between a test signal and a fault source is analyzed in a dependency matrix, parameters are input at designated positions, and a fault result is measured.
Optionally, the performing logic reasoning and state simulation on the signal flow model to obtain the state of the system includes: and (3) starting from the bottom event, carrying out hierarchical logic reasoning on the bottom event, obtaining intermediate events by a plurality of bottom events through logic gate operation, repeatedly executing the intermediate events to calculate the result of the top event, obtaining the state of the top event, carrying out state simulation on the fault tree model according to the reasoning result of the fault tree model, and determining the occurrence point position and the fault type of the fault.
Optionally, the bottom event includes an AND gate through logic gate operation, and as long as the AND gate has fault input, the output result is fault; when all the inputs of the OR gate are faulty, the output result is faulty; the output result state of the NOT gate is opposite to the input result state.
Optionally, the performing fault input on the signal flow model includes: digital signal fault injection, analog signal fault injection, power signal fault injection, bus signal fault injection, probe fault injection, and software fault injection.
Compared with the prior art, the invention has the following technical progress:
the invention can find out weak links of the electronic system to typical fault recognition, find out indexes such as fault detection rate, fault isolation rate and the like of the complex electronic system, and is used for improving and optimizing the test diagnosis design scheme of the electronic system and improving the usability and reliability of the diagnosis system.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention.
In the drawings:
fig. 1 is a schematic diagram of the present invention.
Fig. 2 is a schematic diagram of the digital signal fault injection of the present invention.
Fig. 3 is a schematic diagram of the analog signal fault injection of the present invention.
Fig. 4 is a schematic diagram of power source fault injection in accordance with the present invention.
Fig. 5 is a schematic diagram of bus-like fault injection according to the present invention.
Fig. 6 is a schematic diagram of the probe fault injection of the present invention.
Detailed Description
The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments. Embodiments of the present invention will be described below with reference to the accompanying drawings.
As shown in fig. 1, the invention discloses a fault injection and simulation verification method, which comprises the following steps:
establishing a signal flow model, analyzing the signal flow model to obtain a dependency matrix of the system, analyzing the signal flow model to obtain a fault tree model, and carrying out logic reasoning and state simulation on the signal flow model to obtain the state of the system;
and performing fault input on the signal flow model to acquire state data of the system.
Specifically, the signal flow model is a multi-signal model, and the multi-signal model is a model representation mode for representing the correlation among the system components, functions, faults and tests by defining the signal (function) and the component units (fault mode) and the direct correlation of the test and the signal on the basis of the system structure and the function analysis and by representing the constitution and the interconnection relation of the signal flow guide and each component unit (fault mode) in a layered directed graph.
The signals in the multi-signal model refer to characteristics, states, attributes and parameters of the characteristic system or the component unit characteristics thereof, can be quantitative parameter values and qualitative characteristic descriptions, can be divided into normal states and abnormal states, and can be judged to pass or fail by corresponding test conclusion.
In the multi-signal model, failure modes of constituent units are classified into two types according to the action results: functional failure F (component unit failure causes a system to lose part of its function, system operation is not completely interrupted) and overall failure G (component unit failure causes a system to lose main function, operation is completely interrupted).
The signal flow model consists of four different types of nodes: component nodes, test point nodes, AND switch nodes.
Wherein component nodes represent a piece of hardware with a specific set of functions, components allow hierarchical modeling, and components in a model graph can be described in detail with another graph containing its subcomponents and other nodes;
the test point node represents a physical or logical test operation position, and a plurality of tests are allowed to be completed at one test point;
the AND node represents a redundant connection, AND is applied to fault tolerant system modeling, for example, if both a AND B fail, C is only affected, AND the connection between a, B AND C represents that the AND node is required;
the switch node represents the change relation of internal connection and can be used for modeling different working states of the system.
Modeling a signal flow model comprises the following three steps:
the first step: an input structural model, schematic or conceptual block diagram generates a test signal, such as: the structuring module may be converted from a VHDL structural model, EDIFnetlists, or directly input from a Graphical User Interface (GUI);
and a second step of: adding signals to the test points, which signals may be independent variables in the transfer function;
and a third step of: for some specific cases, the model is revised.
Analyzing the signal flow model to obtain a dependency matrix of the system comprises the following steps: for a large-scale complex electronic system, the number of nodes is numerous, the dependency relationship between test and faults is complicated, the system is a large-scale complex electronic system, the system is required to be divided into subsystem modules of each level layer by layer according to functions, the termination condition of division is that the bottommost module can acquire a multi-signal flow model of the system through an expert system or simulation, in the process of establishing the multi-signal model in a layering manner, the key steps are layering operation of the reachability matrix of each level subsystem and even the whole system, when the reachability analysis is carried out, a plurality of sub-graphs of the reachability to be discussed can be combined with the adjacent matrix of the directed graph, and then the reachability of the combined large graph is calculated; or the reachability of each directed graph is calculated first and then combined.
In the directed graph, a loop exists, an output result acts on an input position to influence the output result, and even deadlock occurs, so that feedback loop analysis is needed to determine the influence of feedback on a system in the process of model analysis.
The final form of the multi-signal flow model is a dependency matrix, namely a dependency relation matrix between the test signal and the fault source, after the accessibility of each level subsystem and the whole top system is obtained, the dependency matrixes of the level subsystems are sequentially combined layer by layer, the dependency matrix of the top system is finally obtained, the dependency matrix is transmitted to a model analysis module, the relation between the test signal and the fault source is found in the analysis module, and then the type and the point position of the fault are determined.
The analyzing the signal flow model to obtain a fault tree model comprises the following steps: the fault tree is abstracted into five classes of objects, wherein the five classes of objects are respectively a bottom event, a result event, a top event, an intermediate event, a logic gate and the like. The bottom event is the event at the bottom layer in the fault tree and cannot be segmented any more, and the standard for judging whether the bottom event is that all parameters can be obtained from the multi-signal flow model; the result event is an event caused by other events or a plurality of event combinations, and is an output event of a certain logic gate in the fault tree; top events are the final result of the fault tree, the realistic meaning of which generally represents "fault" or "risk occurrence", top events being the target guide for the fault tree analysis; the middle event is used as the input and the output of the logic gate, is connected with the upper event and the lower event and is positioned in the middle position of the top event and the bottom event; logic gates are logical symbols that describe causal relationships between events, including "and", "or", "not", "exclusive or", and the like.
At the time of diagnosis, it is necessary to determine "cut sets" and "minimum cut sets". So-called "cutsets", when a certain number of bottom events occur simultaneously, a top event will be caused to occur, and the set of these bottom events is a "cutset". In the "cutset", any bottom event is removed, and no top event can occur, and the "cutset" is called as a "minimum cutset". According to the structure of the fault tree, generating a structural function, expanding the structural function, and simplifying the structural function by using a Boolean operation mode to form a form with the sum of the least terms, wherein each least term is a least cut set.
In the dependency matrix, the relation between the test signal and the fault source can be resolved, and the corresponding relation is provided, so that in order to measure the fault result, only input parameters are needed to be added at the designated position.
Performing logic reasoning and state simulation on the signal flow model to obtain the state of the system, wherein the step of obtaining the state of the system comprises the following steps: and according to the existing fault tree model, starting from the bottom event, carrying out hierarchical logic reasoning. The intermediate events are obtained through the logical gate operation of a plurality of bottom events, and the intermediate events repeatedly execute the process until the result of the top event is operated. When in operation, the AND gate only has fault input, and the output result is fault; when all inputs of the OR gate are faulty, the output result is faulty; the output result state of the not gate is opposite to the input result state. According to this process, the state of the top event can be deduced from the bottom event hierarchically.
And carrying out state simulation on the fault tree model according to the reasoning result of the fault tree model, determining the point position and the fault type of the fault, and providing decision basis for establishing a fault diagnosis knowledge base.
The fault input to the signal flow model comprises: digital signal fault injection, analog signal fault injection, power signal fault injection, bus signal fault injection, probe fault injection, and software fault injection.
The specific application mode is as follows: for faults among different subsystems (combinations), if the faults are connected by adopting a standard bus cable, a bus signal fault injection mode can be adopted, otherwise, an analog signal and digital signal fault injection mode can be adopted; for different circuit boards, the external circuit board mode can be used for leading out connection signals, if the connection signals belong to standard bus signals, the bus signal fault injection mode can be adopted, otherwise, the connection signals can be implemented by using the analog signal and digital signal fault injection mode; for the inside of the circuit board, fault injection can be implemented on components through a probe or software fault injection mode; the power failure injection is mainly used for simulating and loading faults such as primary power supply and secondary power supply which are commonly used in the power failure injection.
The digital signal fault injection is specifically as follows:
the digital signal needs fault modes of disconnection, high fixation, low fixation, string resistance, bridging and the like, in the design of the digital signal fault injection equipment, a digital IO module is used as a core to realize the fault simulation of the high fixation and the low fixation of the digital signal, and the switch matrix is used for switching to realize the fault simulation of disconnection of the string resistance and bridging. Wherein the digital signal is selectable by two level modes, 5V and 3.3V, respectively. According to the common signal fault injection requirement, the fault injection device can provide a plurality of output channels, and the digital signal fault injection principle is shown in fig. 2.
The analog signal fault injection specifically comprises the following steps:
the analog signal requires fault modes such as disconnection of the analog signal transmission line, grounding, impedance change, amplitude change of the transmission signal, offset change and the like. In the design of fault injection equipment, an arbitrary wave generator module is taken as a core, and a special driving circuit and a relay matrix switch are configured to realize the simulation of signals. The arbitrary wave module is mainly used for generating simulation of frequency signals required by the system, and the amplitude of the signals meets the system requirements through amplification and filtering of the driving circuit and is output to a tested object through the relay, as shown in fig. 3.
The power supply fault injection is specifically as follows:
the method adopts the form of a programmable power supply and an electronic load, simulates faults of frequency change, output impedance change and output amplitude change of the power supply, and switches the analog power supply to break and short circuit faults through a matrix switch. In a specific implementation, according to the design of an external power supply and an internal secondary power supply, as shown in fig. 4, the power supply amplitude fault can be realized through remote control of a LAN bus; the open circuit fault can be realized through switching; the impedance change enables the output of the power supply module to be connected into the electronic program control direct current electronic load, and then simulation of impedance change faults can be achieved. In the process of power failure injection, in order to prevent the secondary power supply of the tested product from being damaged, the secondary power supply board needs to be disconnected from the system, the power failure injector replaces the system secondary power supply board to provide the secondary power supply for the tested product, and in the process, the power failure injection is implemented.
The bus fault injection specifically comprises the following steps:
according to the fault diagnosis requirement of an electronic system, the bus fault injection mainly comprises fault injection of a physical layer, an electric layer and a protocol layer of an RS232/422/485 bus, a CAN bus, a FlexRay bus, a LAN and the like. The physical layer faults mainly comprise signal serial impedance and parallel impedance transformation, signal disconnection, short circuit and the like; the electric layer faults mainly comprise amplitude faults, output waveform distortion, output noise faults, duty ratio changes, output signal slope changes and the like; protocol layer failures mainly include signal bit errors, message substitutions, data bit loss, data gap errors, etc.
The bus fault injection principle is shown in fig. 5, and when fault injection is performed, the connection relationship between the fault injection system and the bus is formed by the left side of a broken line in the figure, and in the injection process, a bus control and fault injection module is used for simulating required bus faults and the like.
The probe fault injection is specifically as follows:
the fault mode realized by the fault injection of the probe is similar to the fault mode of the digital signal, and is mainly used for the fault injection of the component level in the circuit board. The probes are contacted with pins of the injected device or pin connecting wires or with pins of an internal or external electric connector to be tested, and the on-line simulation or off-line simulation of faults is realized by changing pin output signals or inter-pin interconnection structures. Probe-based fault injection is divided into: post-drive fault injection, voltage summation fault injection, and switch cascade fault injection, the basic principle is shown in fig. 6.
The software fault injection specifically comprises the following steps:
the software fault injection is a fault injection mode for realizing fault simulation and injection by modifying software codes. In general, by modifying the software interface or the operating logic in the device under test, it is possible to simulate target chips, software itself failures, and other failures that cannot be simulated through the external interface.
The method can use the upper computer development platform and the lower computer operation platform to operate, and the upper computer development platform independently operates on a PC and is used for performing flow design and fault injection knowledge design to provide a secondary development environment. The fault injection upper computer development platform has three main functions of simulation flow development, fault injection knowledge development and instrument resource management.
The simulation process development is used for establishing a process, instrument configuration and resource configuration of the operation of the lower computer;
the fault injection knowledge development is used for editing fault modes and binding the fault modes, and additionally, the fault injection management module is used for generating the fault modes and binding signal flows, and instrument resource management is used for configuring instrument channels;
and finally downloading the simulation flow and the fault knowledge to a lower computer operation platform, receiving the simulation flow and the fault knowledge by the lower computer through an operation control function, analyzing the simulation flow and the fault knowledge, and driving instrument resources to make excitation response actions.
The lower computer platform can call all instrument resources, channel resources, power supply resources, excitation resources and inspection resources provided by the system, monitor the change condition of excitation signals from the outside in real time, and trigger the internal resources to carry out excitation response according to the bound target model simulation flow. And simultaneously, according to 1 or more fault modes defined by fault injection software, the response parameters and the response events can be modified, and the excitation resource is mobilized for fault state output and response.
The fault injection and simulation verification software system development platform operates on a notebook or PC independent of the system, and can realize information interaction, instruction transmission, knowledge loading and simulation process binding between two forms of online and offline and simulation system operation control software through a network interface or mobile storage equipment. When in online connection, the upper computer software can be connected with the upper hardware instrument resource to carry out online debugging and running; when offline, the upper computer software can derive information data such as simulation flow, fault injection knowledge and the like, and the information data is copied to a general simulation system platform through the mobile storage equipment to be synchronized with the operation control software.
The fault injection and simulation verification system operation control software (lower computer) is a computer which directly controls equipment to acquire equipment conditions, and is generally a computer such as PXI/singlechip single chip microcomputer slave controller/lowercompartware.
After the simulation flow development platform of the fault injection and simulation verification system is started, the simulation flow, rules and facts in the fault knowledge base backup are loaded to the operation control software of the fault injection and simulation verification system. The fault injection and simulation verification system development platform receives incoming data from the data processing system interface through a network, firstly analyzes the data and works through a data driving reasoning engine. The inference engine obtains the interpreted configuration information, including the type of traffic (parameter interpretation, instruction interpretation, event interpretation, instruction monitoring, event monitoring, etc.) and other configuration information that the interpretation takes. The knowledge base copy on the fault injection and simulation verification development platform is refreshed from the knowledge base on the database server.
At this time, the inference engine adopts specific inference strategies, methods and inference algorithms, invokes facts loaded by the development platform, and achieves an inference process through rules in a knowledge base loaded by the development platform to obtain a monitoring interpretation result. In the reasoning process, the scheduling engine module realizes dynamic scheduling of rules. The inference engine sends the interpretation result to the interpreter, the interpreter explains the interpretation conclusion, and the reason for the conclusion is explained. And then the interpreter saves the interpretation conclusion and related interpretation data into a data interpretation result database, and sends the data monitoring interpretation result to a monitoring interpretation client side in a UDP broadcast mode by utilizing a communication interface, and the client side returns an interface for displaying the interpretation result, namely, sends the result to a database server for the user to view in the future.
In addition, the client maintains a knowledge base of the database server side. Fault knowledge management completes the addition, deletion, modification and knowledge inspection of knowledge base knowledge. The users with the rights have the following functions of user management; when the new state and the actual situation exist, the inference engine is manually interfered, the fact configuration information in the fault injection and simulation verification development platform is directly modified in batches, and the configuration information of the fault injection and simulation verification development platform can be acquired, displayed and modified, wherein the configuration information comprises customized data interpretation content (comprising business category and subsystem), interpretation conclusion storage mode, interpretation server IP address and port, telemetry data source and port, knowledge base copy updating mode and the like.
The fault injection and simulation verification lower computer platform is used for physical fault injection simulation, achieves the real-time requirement of excitation response in a mode of considering software and hardware in design, can realize full-channel online real-time detection of input signals from a testability system or special test equipment, completely simulates the passive test and response state of a real model in terms of operation effect, and prompts the current model operation state through animation.
Finally, it should be noted that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (6)
1. The fault injection and simulation verification method is characterized by comprising the following steps of:
establishing a signal flow model, analyzing the signal flow model to obtain a dependency matrix of the system, analyzing the signal flow model to obtain a fault tree model, and carrying out logic reasoning and state simulation on the signal flow model to obtain the state of the system;
performing fault input on the signal flow model to acquire state data of the system;
the fault input to the signal flow model comprises: digital signal fault injection, analog signal fault injection, power signal fault injection, bus signal fault injection, probe fault injection, and software fault injection;
for faults among different subsystems, if the faults are connected by adopting a standard bus cable, the fault injection mode of bus signals is adopted, otherwise, the fault injection mode of analog signals and digital signals is adopted; for the different circuit boards, the external circuit board mode is used for leading out the connection signals, if the connection signals belong to standard bus signals, the bus signal fault injection mode is adopted, otherwise, the connection signals are implemented by using the analog signal and digital signal fault injection mode; performing fault injection on the components in the circuit board by using a probe or software fault injection mode; the power failure injection simulates and loads the primary power failure and the secondary power failure;
the digital signal fault injection is as follows:
the digital signal needs fault modes of disconnection, high fixation, low fixation, string resistance and bridging, in the design of the digital signal fault injection equipment, a digital IO module is used as a core to realize the fault simulation of high fixation and low fixation of the digital signal, and a switch matrix is used for switching to realize the fault simulation of disconnection of the string resistance and bridging, wherein the digital signal has two level modes which are selectable and respectively 5V and 3.3V, and the fault injection equipment can provide a plurality of output channels according to the common signal fault injection requirements;
the fault injection of the analog signals is as follows:
in the design of fault injection equipment, an arbitrary wave generator module is used as a core, a special driving circuit and a relay matrix switch are configured to realize the simulation of signals, wherein the arbitrary wave module is used for generating the simulation of frequency signals required by a system, and the amplitude of the signals meets the system requirement through the amplification and filtering of the driving circuit and is output to a tested object through a relay;
the power supply fault injection is as follows:
the method comprises the steps of adopting a program-controlled power supply and an electronic load to simulate faults of frequency change, output impedance change and output amplitude change of the power supply, switching off the analog power supply through a matrix switch to break and short-circuit the faults, and realizing the power amplitude faults through LAN bus remote control according to the design of an external power supply and an internal secondary power supply; the open circuit fault is realized by switching; the impedance change enables the output of the power supply module to be connected with an electronic program-controlled direct current electronic load to realize the simulation of impedance change faults, in the process of power supply fault injection, a secondary power supply board is disconnected with a system to prevent damage to a secondary power supply of a tested product, a power supply fault injector replaces the system secondary power supply board to provide the secondary power supply for the tested product, and the fault injection of the power supply is implemented in the process;
the bus fault injection is as follows:
according to the fault diagnosis requirement of an electronic system, the bus fault injection comprises the fault injection of an RS232/422/485 bus, a CAN bus, a FlexRay bus, a physical layer, an electric layer and a protocol layer of a LAN, and the physical layer fault comprises the transformation of serial impedance and parallel impedance of signals and signal disconnection and short circuit; the electrical layer faults comprise amplitude faults, output waveform distortion, output noise faults, duty ratio changes and output signal slope changes; the protocol layer faults comprise signal bit errors, message replacement, data bit loss and data gap errors, and when fault injection is carried out, a bus control and fault injection module is used for simulating required bus faults;
the probe fault injection is as follows:
the method comprises the steps of enabling a probe to be in contact with a pin of an injected device or a pin connecting wire or in contact with a pin of an internal or external electric connector of a tested product, realizing online simulation or offline simulation of faults by changing pin output signals or an interconnection structure between pins, and dividing fault injection based on the probe into: post-drive fault injection, voltage summation fault injection, and switching cascade fault injection;
the software fault injection specifically comprises the following steps:
by modifying the software interface or the operating logic in the tested device, the faults of the target chip, the software and other faults which cannot be simulated through the external interface are simulated.
2. The fault injection and simulation verification method according to claim 1, wherein: the signal flow model comprises a component node, a test point node, an AND node AND a switch node, AND the input structure model, the schematic diagram or the conceptual block diagram generates a test signal.
3. The fault injection and simulation verification method according to claim 2, wherein: the analyzing the signal flow model to obtain the dependency matrix of the system comprises the following steps: dividing the system into a top system and each level of subsystems according to functions, carrying out layered operation on the reachability matrixes of each level of subsystems and the top system, combining the dependency matrixes of each level of subsystems layer by layer in sequence to obtain the dependency matrix of the top system, transmitting the dependency matrix to a model analysis module, finding the relation between a test signal and a fault source in the model analysis module, and determining the type and the point position of the fault.
4. A fault injection and simulation verification method according to claim 3, wherein: the analyzing the signal flow model to obtain a fault tree model comprises the following steps: abstracting the fault tree into five classes of objects, wherein the five classes of objects are respectively: the method comprises the steps of a bottom event, a result event, a top event, an intermediate event and a logic gate, wherein the top event represents faults or risks, a cut set and a minimum cut set are determined, a structural function is generated according to the structure of a fault tree, the structural function is expanded and simplified in a Boolean operation mode to be in a form with the sum of minimum term products, each minimum term is the minimum cut set, the relation between a test signal and a fault source is analyzed in a dependency matrix, parameters are input at designated positions, and a fault result is measured.
5. The fault injection and simulation verification method of claim 4, wherein: the logic reasoning and state simulation are carried out on the signal flow model, and the obtaining of the state of the system comprises the following steps: and carrying out logic reasoning from the bottom events in a layered manner according to the fault tree model, obtaining intermediate events by a plurality of bottom events through logic gate operation, repeatedly executing the intermediate events to calculate the result of the top event, obtaining the state of the top event, carrying out state simulation on the fault tree model according to the reasoning result of the fault tree model, and determining the occurrence point position and the fault type of the fault.
6. The fault injection and simulation verification method according to claim 5, wherein: the bottom event comprises an AND gate through logical gate operation, and an output result is a fault as long as the AND gate has fault input; when all the inputs of the OR gate are faulty, the output result is faulty; the output result state of the NOT gate is opposite to the input result state.
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Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103559112A (en) * | 2013-11-05 | 2014-02-05 | 北京经纬恒润科技有限公司 | Software fault injection method and system |
| CN103631255A (en) * | 2013-12-03 | 2014-03-12 | 中国航空无线电电子研究所 | Fault injection equipment and method for avionics system health diagnosis |
| JP2015026184A (en) * | 2013-07-25 | 2015-02-05 | 日立オートモティブシステムズ株式会社 | Failure simulation method and device |
| CN104504248A (en) * | 2014-12-05 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | Failure diagnosis modeling method based on designing data analysis |
| CN105223941A (en) * | 2014-06-23 | 2016-01-06 | 中航商用航空发动机有限责任公司 | Hardware is in loop fault injected system |
| CN105512011A (en) * | 2015-11-30 | 2016-04-20 | 中国人民解放军63908部队 | Electronic device testability modeling evaluation method |
| CN106601061A (en) * | 2015-10-20 | 2017-04-26 | 中国人民解放军装甲兵工程学院 | Simulation platform for information terminal maintenance training of armoured vehicle |
| CN107943004A (en) * | 2017-12-06 | 2018-04-20 | 北京交通大学 | The test system of tractor dynamic power shift controller |
| CN108255649A (en) * | 2017-11-30 | 2018-07-06 | 中国航空综合技术研究所 | A kind of Diagnosis Strategy Design method based on modeling and simulating Cooperative Analysis |
| CN109030983A (en) * | 2018-06-11 | 2018-12-18 | 北京航空航天大学 | A kind of diagnosis relational matrix generation method considering exciting test |
| CN110688271A (en) * | 2019-09-11 | 2020-01-14 | 上海高性能集成电路设计中心 | Controllable random fault injection method applied to processor chip simulation verification |
| CN110879584A (en) * | 2019-09-29 | 2020-03-13 | 北京动力机械研究所 | Turbofan engine comprehensive simulation test and fault injection platform for unmanned aerial vehicle |
| CN111190759A (en) * | 2019-12-25 | 2020-05-22 | 中国航空工业集团公司北京长城航空测控技术研究所 | Hybrid diagnosis strategy generation method based on function and fault mode |
| CN111597122A (en) * | 2020-07-24 | 2020-08-28 | 四川新网银行股份有限公司 | Software fault injection method based on historical defect data mining |
| CN111783283A (en) * | 2020-06-15 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Hierarchical fault transfer modeling and reasoning method based on fuzzy directed graph |
| CN111782538A (en) * | 2020-07-09 | 2020-10-16 | 中国人民解放军32181部队 | Equipment testability demonstration analysis and simulation evaluation system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8527441B2 (en) * | 2011-03-10 | 2013-09-03 | GM Global Technology Operations LLC | Developing fault model from service procedures |
-
2020
- 2020-12-05 CN CN202011408485.XA patent/CN112380084B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015026184A (en) * | 2013-07-25 | 2015-02-05 | 日立オートモティブシステムズ株式会社 | Failure simulation method and device |
| CN103559112A (en) * | 2013-11-05 | 2014-02-05 | 北京经纬恒润科技有限公司 | Software fault injection method and system |
| CN103631255A (en) * | 2013-12-03 | 2014-03-12 | 中国航空无线电电子研究所 | Fault injection equipment and method for avionics system health diagnosis |
| CN105223941A (en) * | 2014-06-23 | 2016-01-06 | 中航商用航空发动机有限责任公司 | Hardware is in loop fault injected system |
| CN104504248A (en) * | 2014-12-05 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | Failure diagnosis modeling method based on designing data analysis |
| CN106601061A (en) * | 2015-10-20 | 2017-04-26 | 中国人民解放军装甲兵工程学院 | Simulation platform for information terminal maintenance training of armoured vehicle |
| CN105512011A (en) * | 2015-11-30 | 2016-04-20 | 中国人民解放军63908部队 | Electronic device testability modeling evaluation method |
| CN108255649A (en) * | 2017-11-30 | 2018-07-06 | 中国航空综合技术研究所 | A kind of Diagnosis Strategy Design method based on modeling and simulating Cooperative Analysis |
| CN107943004A (en) * | 2017-12-06 | 2018-04-20 | 北京交通大学 | The test system of tractor dynamic power shift controller |
| CN109030983A (en) * | 2018-06-11 | 2018-12-18 | 北京航空航天大学 | A kind of diagnosis relational matrix generation method considering exciting test |
| CN110688271A (en) * | 2019-09-11 | 2020-01-14 | 上海高性能集成电路设计中心 | Controllable random fault injection method applied to processor chip simulation verification |
| CN110879584A (en) * | 2019-09-29 | 2020-03-13 | 北京动力机械研究所 | Turbofan engine comprehensive simulation test and fault injection platform for unmanned aerial vehicle |
| CN111190759A (en) * | 2019-12-25 | 2020-05-22 | 中国航空工业集团公司北京长城航空测控技术研究所 | Hybrid diagnosis strategy generation method based on function and fault mode |
| CN111783283A (en) * | 2020-06-15 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Hierarchical fault transfer modeling and reasoning method based on fuzzy directed graph |
| CN111782538A (en) * | 2020-07-09 | 2020-10-16 | 中国人民解放军32181部队 | Equipment testability demonstration analysis and simulation evaluation system |
| CN111597122A (en) * | 2020-07-24 | 2020-08-28 | 四川新网银行股份有限公司 | Software fault injection method based on historical defect data mining |
Non-Patent Citations (4)
| Title |
|---|
| 分层递阶多信号建模算法;陈晓梅;孟晓风;季宏;钟波;;仪器仪表学报(第12期);第2497-2504页 * |
| 基于故障仿真的诊断知识获取关键技术研究;赵守伟;马飒飒;吴国庆;;计算机仿真(第01期);全文 * |
| 基于故障树及LabVIEW的雷达设备故障诊断;潘红兵;蔡云龙;;电子测量技术(第09期);第115-118页 * |
| 基于测试性设计的软件故障注入研究综述;李志宇;黄考利;连光耀;;计算机测量与控制(第05期);全文 * |
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