CN112380084A - Fault injection and simulation verification method - Google Patents
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Abstract
The invention discloses a fault injection and simulation verification method, which comprises the steps of establishing a signal flow model, analyzing the signal flow model to obtain a dependency matrix of a system, analyzing the signal flow model to obtain a fault tree model, and performing logical reasoning and state simulation on the signal flow model to obtain the state of the system; and performing fault input on the signal flow model to acquire state data of the system. The method can find the weak link of the electronic system for typical fault identification, and find out the indexes of the complex electronic system, such as fault detection rate, fault isolation rate and the like, so as to improve and optimize the test diagnosis design scheme of the electronic system and improve the availability and reliability of the diagnosis system.
Description
Technical Field
The invention relates to the field of data processing, in particular to a fault injection and simulation verification method.
Background
The traditional electronic system cannot respond to real faults in a multi-working mode and a working state, and cannot find out the position of a weak link, so that the usability and the reliability of the electronic system are influenced.
Disclosure of Invention
In order to solve the above problems, the present invention provides a fault injection and simulation verification method.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a fault injection and simulation verification method is disclosed.
Optionally, a signal flow model is established, the signal flow model is analyzed to obtain a dependency matrix of the system, the signal flow model is analyzed to obtain a fault tree model, and logical reasoning and state simulation are performed on the signal flow model to obtain a state of the system;
and performing fault input on the signal flow model to acquire state data of the system.
Optionally, the signal flow model includes a component node, a test point node, an AND node, AND a switch node, AND the input structure model, the schematic diagram, or the conceptual block diagram generates the test signal.
Optionally, the analyzing the signal flow model to obtain a dependency matrix of the system includes: the method comprises the steps of dividing a system into a top system and subsystems at all levels according to functions, operating reachability matrixes of the subsystems at all levels and reachability matrixes of the subsystems at all levels in a layering mode, combining the reachability matrixes layer by layer in sequence to obtain dependency matrixes of the subsystems at all levels, obtaining the dependency matrixes of the top system, transmitting the dependency matrixes to a model analysis module, finding the relation between a test signal and a fault source in the model analysis module, and determining the type and the point position of the fault.
Optionally, the analyzing the signal flow model to obtain the fault tree model includes: abstracting a fault tree into five types of objects, wherein the five types of objects are respectively as follows: the method comprises the steps of determining a cut set and a minimum cut set according to the structure of a fault tree, generating a structure function, expanding the structure function, simplifying the structure function in a Boolean operation mode to form a mode with the sum of minimum term products, analyzing the relation between a test signal and a fault source in a dependency matrix, inputting parameters at a specified position, and measuring a fault result.
Optionally, the performing logic reasoning and state simulation on the signal flow model to obtain the state of the system includes: and the root fault tree model performs logical reasoning in a layering mode from bottom events, a plurality of bottom events obtain intermediate events through logical gate operation, the intermediate events repeatedly perform operation to obtain the result of the top event to obtain the state of the top event, and the fault tree model is subjected to state simulation according to the reasoning result of the fault tree model to determine the point position where the fault occurs and the fault type.
Optionally, the bottom event includes that the output result is a fault as long as the and gate has a fault input through the logic gate operation; when all the inputs of the OR gate are faults, the output result is the fault; the output result state of the not gate is opposite to the input result state.
Optionally, the performing fault input on the signal flow model includes: digital signal fault injection, analog signal fault injection, power signal fault injection, bus signal fault injection, probe fault injection, and software fault injection.
Compared with the prior art, the invention has the technical progress that:
the method can find the weak link of the electronic system for typical fault identification, and find out the indexes of the complex electronic system, such as fault detection rate, fault isolation rate and the like, so as to improve and optimize the test diagnosis design scheme of the electronic system and improve the availability and reliability of the diagnosis system.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention.
In the drawings:
fig. 1 is a schematic diagram of the present invention.
Fig. 2 is a schematic diagram of digital signal fault injection in accordance with the present invention.
Fig. 3 is a schematic diagram of analog signal fault injection in accordance with the present invention.
Fig. 4 is a schematic diagram of power class fault injection in accordance with the present invention.
FIG. 5 is a schematic diagram of bus-like fault injection in accordance with the present invention.
Fig. 6 is a schematic diagram of fault injection for the probe of the present invention.
Detailed Description
The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments. Embodiments of the present invention will be described below with reference to the accompanying drawings.
As shown in fig. 1, the present invention discloses a fault injection and simulation verification method, which comprises:
establishing a signal flow model, analyzing the signal flow model to obtain a dependency matrix of the system, analyzing the signal flow model to obtain a fault tree model, and performing logical reasoning and state simulation on the signal flow model to obtain the state of the system;
and performing fault input on the signal flow model to acquire state data of the system.
Specifically, the signal flow model is a multi-signal model, and the multi-signal model is a model representation mode which represents the correlation among system composition, function, fault and test by representing the signal flow direction and the composition and interconnection relation of each composition unit (fault mode) through a layered directed graph on the basis of system structure and function analysis and by defining the direct correlation among signals (function) and component units (fault mode) and test and signals.
The signals in the multi-signal model refer to characteristics, states, attributes and parameters representing characteristics of a system or a component unit of the system, can be quantitative parameter values and qualitative characteristic descriptions, can be distinguished into normal states and abnormal states, and the corresponding test conclusion is that the system passes or does not pass the two states.
In the multi-signal model, the failure modes of the constituent units are divided into two categories according to different action results: functional failure F (failure of a component unit results in loss of partial functionality of the system, incomplete interruption of system operation) and global failure G (failure of a component unit results in loss of primary functionality of the system, complete interruption of operation).
The signal flow model is composed of four different types of nodes: a component node, a test point node, an AND node, AND a switch node.
Wherein a component node represents a piece of hardware with a particular set of functions, the component allows for hierarchical modeling, and the component in a model graph can be described in detail with another graph that contains its subcomponents and other nodes;
the test point nodes represent physical or logical test operation positions, and multiple tests are allowed to be completed at one test point;
the AND node represents a redundant connection AND is applied to fault-tolerant system modeling, for example, if A AND B both fail, C is affected, AND the connection between A, B AND C represents that the AND node is needed;
the switch node represents the variation relation of the internal connection and can be used for modeling different working states of the system.
The modeling of the signal flow model is divided into the following three steps:
the first step is as follows: the input structural model, schematic diagram or conceptual block diagram generates test signals such as: the structuring module can be converted from a VHDL structure model, EDIFnetlists, or directly input from a Graphical User Interface (GUI);
the second step is that: adding signals to the test points, which signals may be independent variables that may be in a transfer function;
the third step: for some specific cases, the model is revised.
The analyzing the signal flow model to obtain the dependency matrix of the system comprises the following steps: for a large complex electronic system, the number of nodes is numerous, the dependency relationship of testing and faults is complex, the system is a large complex electronic system, therefore, the system needs to be divided into subsystems of various levels layer by layer according to functions, the division termination condition is that the bottommost module can obtain a multi-signal flow model of the system through an expert system or simulation, in the process of establishing the multi-signal model in a layering way, the key step is to hierarchically calculate reachability matrixes of the subsystems of various levels and even the whole system, when reachability analysis is carried out, a plurality of sub-graphs of reachability to be discussed can be combined with adjacent matrixes of directed graphs of the sub-graphs, and then reachability of the combined large graphs is calculated; or the reachability of each directed subgraph is operated first and then merged.
In the directed graph, a loop exists, the output result acts on the input position, the output result is influenced, and even deadlock occurs, so in the process of model analysis, feedback loop analysis is needed to determine the influence of feedback on the system.
The final form of the multi-signal flow model is a dependency matrix, namely, a dependency relation matrix between the test signal and the fault source, after the accessibility of each level subsystem and the whole top system is obtained, the dependency matrix of each level subsystem is obtained by combining layer by layer in sequence, finally the dependency matrix of the top system is obtained, the dependency matrix is transmitted to a model analysis module, the relation between the test signal and the fault source is found in the analysis module, and the type and the point position of the fault are further determined.
The analyzing the signal flow model to obtain the fault tree model comprises: the fault tree is abstracted into five types of objects, wherein the five types of objects are respectively a bottom event, a result event, a top event, a middle event, a logic gate and the like. The bottom event is the event at the bottom layer in the fault tree and can not be segmented, and the standard for judging whether the bottom event is that all parameters can be obtained from a multi-signal flow model; the result event is an event caused by other events or a plurality of event combinations and is an output event of a logic gate in the fault tree; the top event is the final result of the fault tree, the realistic meaning of the top event usually represents 'fault' or 'risk occurrence', and the top event is the target guide for performing fault tree analysis; the middle event is simultaneously used as the input and the output of the logic gate, is connected with the upper layer event and the lower layer event and is positioned in the middle of the top event and the bottom event; logic gates are logical symbols describing causal relationships between events and include "and gates", "or gates", "not gates", "xor gates", and the like.
At the time of diagnosis, it is necessary to determine a "cut set" and a "minimum cut set". The so-called "cut set" is a set of bottom events that, when they occur simultaneously, cause the top event to occur. In the cut set, if any bottom event is removed and the top event cannot occur, the cut set is called as the minimum cut set. According to the structure of the fault tree, a structure function is generated and expanded, and is simplified in a Boolean operation mode to form the sum of the products of the minimum terms, wherein each minimum term is a minimal cut set.
In the dependency matrix, the relationship between the test signal and the fault source can be analyzed, and the corresponding relationship is existed, so that in order to measure the fault result, only the input parameters need to be added at the specified position.
Performing logic reasoning and state simulation on the signal flow model to obtain the state of the system, wherein the state of the system comprises the following steps: and carrying out logic reasoning in a layering mode from a bottom event according to the existing fault tree model. A plurality of bottom events are operated through logic gates to obtain intermediate events, and the intermediate events repeat the process until the result of the top event is operated. During operation, as long as the AND gate has a fault input, the output result is a fault; when all the inputs of the OR gate are faults, the output result is the fault; the output result state of the not gate is opposite to the input result state. According to the process, the state of the top event can be obtained by hierarchical reasoning from the bottom event.
And according to the reasoning result of the fault tree model, performing state simulation on the fault tree model, determining the point position of the fault and the fault type, and providing a decision basis for establishing a fault diagnosis knowledge base.
The fault inputting the signal flow model comprises: digital signal fault injection, analog signal fault injection, power signal fault injection, bus signal fault injection, probe fault injection, and software fault injection.
The specific application mode is as follows: for faults among different subsystems (combinations), if the faults are connected by adopting a standard bus cable, the faults can be implemented by adopting a bus signal fault injection mode, otherwise, the faults can be implemented by adopting an analog signal and digital signal fault injection mode; for different circuit boards, a connection signal can be led out by using an external circuit board, if the connection signal belongs to a standard bus signal, a bus signal fault injection mode can be adopted for implementation, otherwise, an analog signal and digital signal fault injection mode can be adopted for implementation; for the interior of the circuit board, fault injection can be carried out on the components in a probe or software fault injection mode; the power supply fault injection is mainly used for simulating and loading faults of a primary power supply, a secondary power supply and the like which are commonly used.
The digital signal fault injection specifically comprises the following steps:
the fault modes required by the digital signal are disconnection, solid high, solid low, string resistance, bridging and the like, in the design of the digital signal fault injection equipment, the digital IO module is used as a core, the fault simulation of the solid high and the solid low of the digital signal is realized, and the fault simulation of the disconnection string resistance and the bridging is realized by switching of a switch matrix. The digital signal is selectable by two level modes, namely 5V and 3.3V. According to the common signal fault injection requirement, the fault injection device can provide a plurality of output channels, and the digital signal fault injection principle is shown in fig. 2.
The analog signal fault injection specifically comprises the following steps:
analog signals require failure modes such as disconnection, grounding, impedance changes, amplitude changes of transmitted signals, and offset changes of analog signal transmission lines. In the design of the fault injection equipment, an arbitrary wave generator module is used as a core, and a special drive circuit and a relay matrix switch are configured to realize the simulation of signals. The arbitrary wave module is mainly used for generating simulation of frequency signals required by the system, the amplitude of the signals meets the system requirements through amplification and filtering of the driving circuit, and the signals are output to a tested object through the relay, as shown in fig. 3.
The power supply fault injection specifically comprises the following steps:
the form of a program control power supply and an electronic load is adopted, the frequency change, the output impedance change and the output amplitude change faults of the power supply are simulated, and the open circuit and short circuit faults of the power supply are simulated through switching of a matrix switch. In the specific implementation, according to the design of an external power supply and an internal secondary power supply, as shown in fig. 4, the power supply amplitude fault can be realized through the remote control of a LAN bus; open circuit faults can be realized by switching the switches; the impedance change enables the output of the power supply module to be connected into the electronic program-controlled direct current electronic load, and therefore the impedance change fault can be simulated. In the power failure injection process, in order to prevent the secondary power supply of the tested product from being damaged, the secondary power supply board is required to be disconnected from the system, the power failure injector replaces the system secondary power supply board to provide the secondary power supply for the tested product, and the power failure injection is implemented in the process.
The bus fault injection specifically comprises the following steps:
according to the requirement of electronic system fault diagnosis, the bus type fault injection mainly comprises fault injection of a physical layer, an electrical layer and a protocol layer of an RS232/422/485 bus, a CAN bus, a FlexRay bus, a LAN and the like. The physical layer faults mainly comprise the transformation of signal serial impedance and parallel impedance, signal open circuit, short circuit and the like; the electric layer faults mainly comprise amplitude faults, output waveform distortion, output noise faults, duty ratio changes, output signal slope changes and the like; protocol layer faults mainly include signal bit errors, message replacement, data bit loss, data gap errors, and the like.
The principle of bus fault injection is shown in fig. 5, when fault injection is performed, the connection relationship between a fault injection system and a bus is formed by the left side of a dotted line in the figure, and in the injection process, a bus control and fault injection module is used for simulating required bus faults and the like.
The probe fault injection specifically comprises the following steps:
the fault mode realized by the probe fault injection is similar to the digital signal fault mode, and is mainly used for the requirement of component-level fault injection in a circuit board. The probe is contacted with a pin and a pin connecting line of an injected device or contacted with a pin of a tested internal or external electric connector, and the on-line simulation or off-line simulation of the fault is realized by changing a pin output signal or an interconnection structure between the pins. The fault injection based on the probe is divided into: post-drive fault injection, voltage summation fault injection, and switch cascade fault injection, the basic principle is shown in fig. 6.
The software fault injection specifically comprises the following steps:
software fault injection is a fault injection mode which realizes fault simulation and injection by modifying software codes. Generally, by modifying the software interface or the operating logic in the device under test, the target chip, the software itself and other faults that cannot be simulated through the external interface can be simulated.
The method can be operated by using an upper computer development platform and a lower computer operation platform, wherein the upper computer development platform independently operates on a PC (personal computer) and is used for carrying out flow design and fault injection knowledge design to provide a secondary development environment. The fault injection upper computer development platform has three main functions of simulation process development, fault injection knowledge development and instrument resource management.
The simulation process is used for building the process, instrument configuration and resource configuration of the operation of the lower computer;
fault injection knowledge development is used for editing fault modes and binding the fault modes, in addition, a fault injection management module generates the fault modes and binds the fault modes with signal streams, and instrument resource management is used for configuring instrument channels;
and finally, loading the simulation process and the fault knowledge to a lower computer running platform, receiving the simulation process and the fault knowledge by the lower computer through a running control function, analyzing the simulation process and the fault knowledge, and driving instrument resources to perform excitation response actions.
The lower computer platform can call all instrument resources, channel resources, power supply resources, excitation resources and inspection resources provided by the system, monitor the change condition of an excitation signal from the outside in real time, and trigger internal resources to perform excitation response according to a bound target model simulation flow. Meanwhile, according to 1 or more fault modes defined by fault injection software, response parameters and response events can be modified, and excitation resources are transferred to carry out fault state output and response.
The fault injection and simulation verification software system development platform runs on a notebook or a PC (personal computer) independent of the system, and can realize information interaction, instruction transmission, knowledge loading and simulation flow binding with simulation system running control software in two online and offline modes through a network interface or a mobile storage device. When the connection is on line, the upper computer software can be connected with hardware instrument resources to carry out on-line debugging and operation; when the simulation system is off-line, the upper computer software can export information data such as simulation flow, fault injection knowledge and the like, and the information data is copied to the general simulation system platform through the mobile storage device to be synchronous with the operation control software.
The fault injection and simulation verification development platform (the upper computer is a computer which can directly send out control instructions, generally a PC/host computer/master computer/upper computer, and various signal changes are displayed on a screen, the fault injection and simulation verification system operation control software (the lower computer) is a computer which directly controls equipment to obtain equipment conditions, generally a PXI/single-chip microcomputer single computer/lower computer and the like, a command sent by the fault injection and simulation verification development platform is firstly sent to the fault injection and simulation verification system operation control software, the fault injection and simulation verification system operation control software is then interpreted into corresponding time sequence signals according to the command to directly control corresponding equipment, the fault injection and simulation verification system operation control software reads equipment state data (switching value, analog quantity, communication amount) is converted into a digital signal and fed back to the upper computer.
After the simulation flow development platform of the fault injection and simulation verification system is started, rules and facts in the simulation flow and the fault knowledge base backup are loaded to the operation control software of the fault injection and simulation verification system. After the fault injection and simulation verification system development platform receives the incoming data from the data processing system interface through the network, the data is firstly analyzed, and the inference engine is driven to work through the data. The inference engine obtains interpreted configuration information including the type of service (parameter interpretation, instruction interpretation, event interpretation, instruction monitoring, event monitoring, etc.) and other configuration information that is interpreted. And the knowledge base copy on the fault injection and simulation verification development platform is refreshed from the knowledge base on the database server.
At the moment, the inference machine adopts a specific inference strategy, a specific inference method and an inference algorithm, calls the fact loaded by the development platform, realizes an inference process through rules in a knowledge base loaded by the development platform, and obtains a monitoring and interpretation result. In the inference process, the scheduling engine module realizes the dynamic scheduling of the rules. The inference engine sends the interpretation result to the interpreter, and the interpreter explains the interpretation result and explains the reason for the conclusion. Then the interpreter stores the interpretation conclusion and the related interpretation data in a data interpretation result database, and transmits the data monitoring interpretation result to a monitoring interpretation client by using a communication interface in a UDP (user Datagram protocol) broadcasting mode, and returns an interface for displaying the interpretation result at the client, and transmits the result to a database server for a user to check at a later date.
In addition, the client maintains a knowledge base of the database server side. And the fault knowledge management completes the addition, deletion, modification and knowledge check of knowledge in the knowledge base. The user with authority has the following functions of user management; and when the new state and the actual situation are in, manual intervention is carried out on the inference engine, the fact configuration information in the fault injection and simulation verification development platform is directly modified in batch, and the configuration information of the fault injection and simulation verification development platform can be obtained, displayed and modified, and comprises custom data interpretation contents (comprising service types and subsystems), an interpretation conclusion storage mode, an interpretation server IP address and port, a remote measurement data source and port, a knowledge base copy updating mode and the like.
The lower computer platform is used for physical fault injection simulation, the real-time requirement of excitation response is met by considering the software and hardware modes from the aspect of design, the digital/analog channel can realize the on-line real-time detection of the input signals from a testability system or special test equipment by the full channel, the passive test and response states of real models are completely simulated from the aspect of operation effect, and the current model operation state is prompted through animation.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
Claims (7)
1. A fault injection and simulation verification method is characterized by comprising the following steps:
establishing a signal flow model, analyzing the signal flow model to obtain a dependency matrix of the system, analyzing the signal flow model to obtain a fault tree model, and performing logical reasoning and state simulation on the signal flow model to obtain the state of the system;
and performing fault input on the signal flow model to acquire state data of the system.
2. The fault injection and simulation verification method according to claim 1, wherein: the signal flow model comprises component nodes, test point nodes, AND nodes AND switch nodes, AND the input structure model, the schematic diagram or the concept block diagram generates test signals.
3. The fault injection and simulation verification method according to claim 2, wherein: the analyzing the signal flow model to obtain the dependency matrix of the system includes: the method comprises the steps of dividing a system into a top system and subsystems at all levels according to functions, operating reachability matrixes of the subsystems at all levels and reachability matrixes of the subsystems at all levels in a layering mode, combining the reachability matrixes layer by layer in sequence to obtain dependency matrixes of the subsystems at all levels, obtaining the dependency matrixes of the top system, transmitting the dependency matrixes to a model analysis module, finding the relation between a test signal and a fault source in the model analysis module, and determining the type and the point position of the fault.
4. The fault injection and simulation verification method according to claim 3, wherein: the analyzing the signal flow model to obtain the fault tree model comprises: abstracting a fault tree into five types of objects, wherein the five types of objects are respectively as follows: the method comprises the steps of determining a cut set and a minimum cut set according to the structure of a fault tree, generating a structure function, expanding the structure function, simplifying the structure function in a Boolean operation mode to form a mode with the sum of minimum term products, analyzing the relation between a test signal and a fault source in a dependency matrix, inputting parameters at a specified position, and measuring a fault result.
5. The fault injection and simulation verification method according to claim 4, wherein: the logic reasoning and state simulation of the signal flow model to obtain the state of the system comprises the following steps: according to the fault tree model, logical reasoning is carried out in a layering mode from bottom events, a plurality of bottom events obtain intermediate events through logical gate operation, the intermediate events repeatedly execute operation to obtain the result of the top event, the state of the top event is obtained, state simulation is carried out on the fault tree model according to the reasoning result of the fault tree model, and the point position where a fault occurs and the fault type are determined.
6. The fault injection and simulation verification method according to claim 5, wherein: the bottom event comprises that the output result is a fault as long as the AND gate inputs the fault through the logic gate operation; when all the inputs of the OR gate are faults, the output result is the fault; the output result state of the not gate is opposite to the input result state.
7. The fault injection and simulation verification method according to claim 1, wherein: the fault inputting the signal flow model comprises: digital signal fault injection, analog signal fault injection, power signal fault injection, bus signal fault injection, probe fault injection, and software fault injection.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114879636A (en) * | 2022-05-15 | 2022-08-09 | 浙江工业大学 | Chemical process fault isolation method based on fault interpreter |
| CN115408802A (en) * | 2022-11-01 | 2022-11-29 | 中国汽车技术研究中心有限公司 | Fault tree construction method based on Modelica simulation model |
| CN116149801A (en) * | 2023-04-18 | 2023-05-23 | 商飞软件有限公司 | Airborne maintenance and health management simulation system and simulation method |
Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120232743A1 (en) * | 2011-03-10 | 2012-09-13 | GM Global Technology Operations LLC | Developing fault model from service procedures |
| CN103559112A (en) * | 2013-11-05 | 2014-02-05 | 北京经纬恒润科技有限公司 | Software fault injection method and system |
| CN103631255A (en) * | 2013-12-03 | 2014-03-12 | 中国航空无线电电子研究所 | Fault injection equipment and method for avionics system health diagnosis |
| JP2015026184A (en) * | 2013-07-25 | 2015-02-05 | 日立オートモティブシステムズ株式会社 | Failure simulation method and device |
| CN104504248A (en) * | 2014-12-05 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | Failure diagnosis modeling method based on designing data analysis |
| CN105223941A (en) * | 2014-06-23 | 2016-01-06 | 中航商用航空发动机有限责任公司 | Hardware is in loop fault injected system |
| CN105512011A (en) * | 2015-11-30 | 2016-04-20 | 中国人民解放军63908部队 | Electronic device testability modeling evaluation method |
| CN106601061A (en) * | 2015-10-20 | 2017-04-26 | 中国人民解放军装甲兵工程学院 | Simulation platform for information terminal maintenance training of armoured vehicle |
| CN107943004A (en) * | 2017-12-06 | 2018-04-20 | 北京交通大学 | The test system of tractor dynamic power shift controller |
| CN108255649A (en) * | 2017-11-30 | 2018-07-06 | 中国航空综合技术研究所 | A kind of Diagnosis Strategy Design method based on modeling and simulating Cooperative Analysis |
| CN109030983A (en) * | 2018-06-11 | 2018-12-18 | 北京航空航天大学 | A kind of diagnosis relational matrix generation method considering exciting test |
| CN110688271A (en) * | 2019-09-11 | 2020-01-14 | 上海高性能集成电路设计中心 | Controllable random fault injection method applied to processor chip simulation verification |
| CN110879584A (en) * | 2019-09-29 | 2020-03-13 | 北京动力机械研究所 | Turbofan engine comprehensive simulation test and fault injection platform for unmanned aerial vehicle |
| CN111190759A (en) * | 2019-12-25 | 2020-05-22 | 中国航空工业集团公司北京长城航空测控技术研究所 | Hybrid diagnosis strategy generation method based on function and fault mode |
| CN111597122A (en) * | 2020-07-24 | 2020-08-28 | 四川新网银行股份有限公司 | Software fault injection method based on historical defect data mining |
| CN111783283A (en) * | 2020-06-15 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Hierarchical fault transfer modeling and reasoning method based on fuzzy directed graph |
| CN111782538A (en) * | 2020-07-09 | 2020-10-16 | 中国人民解放军32181部队 | Equipment testability demonstration analysis and simulation evaluation system |
-
2020
- 2020-12-05 CN CN202011408485.XA patent/CN112380084B/en active Active
Patent Citations (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120232743A1 (en) * | 2011-03-10 | 2012-09-13 | GM Global Technology Operations LLC | Developing fault model from service procedures |
| JP2015026184A (en) * | 2013-07-25 | 2015-02-05 | 日立オートモティブシステムズ株式会社 | Failure simulation method and device |
| CN103559112A (en) * | 2013-11-05 | 2014-02-05 | 北京经纬恒润科技有限公司 | Software fault injection method and system |
| CN103631255A (en) * | 2013-12-03 | 2014-03-12 | 中国航空无线电电子研究所 | Fault injection equipment and method for avionics system health diagnosis |
| CN105223941A (en) * | 2014-06-23 | 2016-01-06 | 中航商用航空发动机有限责任公司 | Hardware is in loop fault injected system |
| CN104504248A (en) * | 2014-12-05 | 2015-04-08 | 中国航空工业集团公司第六三一研究所 | Failure diagnosis modeling method based on designing data analysis |
| CN106601061A (en) * | 2015-10-20 | 2017-04-26 | 中国人民解放军装甲兵工程学院 | Simulation platform for information terminal maintenance training of armoured vehicle |
| CN105512011A (en) * | 2015-11-30 | 2016-04-20 | 中国人民解放军63908部队 | Electronic device testability modeling evaluation method |
| CN108255649A (en) * | 2017-11-30 | 2018-07-06 | 中国航空综合技术研究所 | A kind of Diagnosis Strategy Design method based on modeling and simulating Cooperative Analysis |
| CN107943004A (en) * | 2017-12-06 | 2018-04-20 | 北京交通大学 | The test system of tractor dynamic power shift controller |
| CN109030983A (en) * | 2018-06-11 | 2018-12-18 | 北京航空航天大学 | A kind of diagnosis relational matrix generation method considering exciting test |
| CN110688271A (en) * | 2019-09-11 | 2020-01-14 | 上海高性能集成电路设计中心 | Controllable random fault injection method applied to processor chip simulation verification |
| CN110879584A (en) * | 2019-09-29 | 2020-03-13 | 北京动力机械研究所 | Turbofan engine comprehensive simulation test and fault injection platform for unmanned aerial vehicle |
| CN111190759A (en) * | 2019-12-25 | 2020-05-22 | 中国航空工业集团公司北京长城航空测控技术研究所 | Hybrid diagnosis strategy generation method based on function and fault mode |
| CN111783283A (en) * | 2020-06-15 | 2020-10-16 | 中国电子科技集团公司第十四研究所 | Hierarchical fault transfer modeling and reasoning method based on fuzzy directed graph |
| CN111782538A (en) * | 2020-07-09 | 2020-10-16 | 中国人民解放军32181部队 | Equipment testability demonstration analysis and simulation evaluation system |
| CN111597122A (en) * | 2020-07-24 | 2020-08-28 | 四川新网银行股份有限公司 | Software fault injection method based on historical defect data mining |
Non-Patent Citations (4)
| Title |
|---|
| 李志宇;黄考利;连光耀;: "基于测试性设计的软件故障注入研究综述", 计算机测量与控制, no. 05 * |
| 潘红兵;蔡云龙;: "基于故障树及LabVIEW的雷达设备故障诊断", 电子测量技术, no. 09, pages 115 - 118 * |
| 赵守伟;马飒飒;吴国庆;: "基于故障仿真的诊断知识获取关键技术研究", 计算机仿真, no. 01 * |
| 陈晓梅;孟晓风;季宏;钟波;: "分层递阶多信号建模算法", 仪器仪表学报, no. 12, pages 2497 - 2504 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114879636A (en) * | 2022-05-15 | 2022-08-09 | 浙江工业大学 | Chemical process fault isolation method based on fault interpreter |
| CN115408802A (en) * | 2022-11-01 | 2022-11-29 | 中国汽车技术研究中心有限公司 | Fault tree construction method based on Modelica simulation model |
| CN115408802B (en) * | 2022-11-01 | 2023-04-07 | 中国汽车技术研究中心有限公司 | Fault tree construction method based on Modelica simulation model |
| CN116149801A (en) * | 2023-04-18 | 2023-05-23 | 商飞软件有限公司 | Airborne maintenance and health management simulation system and simulation method |
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