CN105512011A - Electronic device testability modeling evaluation method - Google Patents

Electronic device testability modeling evaluation method Download PDF

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CN105512011A
CN105512011A CN201510855831.1A CN201510855831A CN105512011A CN 105512011 A CN105512011 A CN 105512011A CN 201510855831 A CN201510855831 A CN 201510855831A CN 105512011 A CN105512011 A CN 105512011A
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testability
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test
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lambda
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CN105512011B (en
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连光耀
孙江生
闫鹏程
孙连武
曹卫宁
张西山
李会杰
蔡丽影
王凯
周云川
邱文昊
魏忠林
厚泽
潘国庆
王承红
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63908 Troops of PLA
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Abstract

The invention discloses an electronic device testability modeling evaluation method, and relates to the technical field of device testing. The electronic device testability modeling evaluation method comprises the following steps of 1) determining the modeling object; 2) building a testability hierarchical mixture model; 3) adjusting, correcting and verifying the built testability hierarchical mixture model, and evaluating the accuracy of the built model; and 4) analyzing and evaluating the device testability. The electronic device testability modeling evaluation method has good observability, the association and dependency relation between faults and tests can be reflected, and the structural relation and the fault propagation relation between system modules can be reflected; multi-source testability information can be fused to carry out testability quantitative analysis and evaluation, at the same time, the electronic device testability modeling evaluation method has hierarchy, small fragment testability models such as subsystems or function modules are combined to form the testability model of the whole system, the modeling difficulty level is reduced, and the testability model can be extended and modified conveniently.

Description

A kind of electronics testability modeling appraisal procedure
Technical field
The present invention relates to testing of equipment technical field.
Background technology
In equipment demonstration and design phase, early stage testability assessment can be realized by setting up testability model.Meanwhile, along with going deep into of equipment preparation, this model is also wanted to merge the testability information such as expertise information, historical test data produced in equipment preparation process, improves the accuracy of testability Simulation Evaluation result.
At present, also there is the deficiency of following three aspects in model-based testing Simulation Evaluation:
(1) model be based upon on determinacy basis cannot process the uncertain problem of test, such as information flow model, multi-signal flow graph model etc.;
(2) the probabilistic model of test can be processed, the hierarchical structure of equipment can not be reflected again, be not easy to the testability prediction assessment at equipment Design initial stage, such as testability Bayesian network model;
(3) determine that the method for testability model interior joint conditional probability is unpractical by lot of experiments, be directly provide result according to hypothesis or expertise mostly, process more coarse, cause the precision of testability Simulation Evaluation result very low.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of electronics testability modeling appraisal procedure; The method has good observability, can not only faults and test between association dependence, the structural relation between system module and fault propagation relation can also be reflected; And multi-source testability information can be merged, carry out testability quantitative test and assessment; Also there is level simultaneously, adopt the testability model of subsystem or functional module small fragment testability model group synthesis whole system, reduce modeling difficulty, be also convenient to expansion and the amendment of testability model.
For solving the problems of the technologies described above, the technical solution used in the present invention is: a kind of electronics testability modeling appraisal procedure, and the method comprises the following steps:
1) clear and definite modeling object; Carrying out schematic model, testability structural model and failure mode effect and HAZAN to being modeled equipment, identifying and extracting Composition and distribution, fault mode and the detecting information equipped, and partition structure level, be clearly modeled each component units of equipment;
2) testability layering mixture model builds;
A, according to analysis to change system, set up each functional module of change system, the submodel fragment of incidence relation between fault and test;
B, according to the propagation relation of fault mode and the functional relationship of system architecture, each submodel to be coupled together, set up the whole testability layering mixture model being modeled change system;
C, according to accessibility principle, testability layering mixture model can be converted into the expectation that Bayes's testability model carries out testability quantitative target;
3) the testability layering mixture model built is adjusted, revises and verified, the order of accuarcy of the constructed model of assessment;
4) equipment Test is analyzed and assessment;
A, prior distribation by expertise determination node condition probability;
B, test figure is utilized to upgrade conditional probability prior distribation;
C, the testability of utilization layering mixture model reasoning to equipment are assessed.
The technical scheme of further optimization is described step 2) in testability layering mixture model comprise system component units finite set C, fault mode finite set F, test finite set T, directed edge finite set E, node condition conceptual schema collection P;
System component units finite set C:C={c 1, c 2..., c i..., c m, c i(1≤i≤m) represents i-th component units; Incidence relation between component units can be expressed as CC={c ic j, c ic j=<c i, c j> represents component units c iand c jbetween incidence relation, c i, c j∈ C;
Fault mode finite set F:F={f 1, f 2..., f i..., f n, f i(1≤i≤n) represents i-th kind of fault mode, and the subordinate relation between system failure mode and component units can be expressed as CF={c if j, c if j=<c i, f j> represents parts c iwith fault f jbetween subordinate relation, c i∈ C, f j∈ F;
Test finite set T:T={t 1, t 2..., t i..., t l, t i(1≤i≤l) represents i-th test, specifies that each test is two-value, namely passes through and does not pass through; Mapping relations between fault mode and test can be expressed as FT={f it j, f it j=<f i, t j> representing fault pattern f iwith test t jbetween mapping relations, f i∈ F, t j∈ T;
Directed edge finite set E: represent fault mode f iwith test t jbetween information flow, represent fault mode f kwith fault mode f lbetween information flow, represent test t gwith test t hbetween information flow;
Node condition probability set P:P={ (FD ij, FA ij), (FD ij, FA ij) for detecting---false-alarm probability pair; Wherein FD ijrepresent by t jthe source of trouble f of monitoring itime abnormal, test t jalso abnormal probability; FA ijrepresent by t jthe source of trouble f of monitoring itime normal, test t jalso abnormal probability.
The technical scheme of further optimization is that described testability layering mixture model also comprises systemic-function collection G:G={g 1, g 2..., g i..., g k, g i(1≤i≤k) representative system i-th function; Interact relation between function and fault mode can be expressed as FG={f ig j, f ig j=<f i, g j> representing fault pattern f iwith function g jbetween mapping relations, f i∈ F, g j∈ G;
The failure rate λ={ λ of fault mode 1, λ 2..., λ i..., λ n,
λ itabular form fault mode f ifailure rate;
Fault mode F and the correlation matrix D:D=[d testing T ij], be m × n dimension, each test t jrow of (1≤j≤n) homography: wherein d jrepresenting matrix D jth arranges; If test t j(1≤j≤n) can detect fault mode f i, then d ijbe 1, otherwise be 0;
System level unit L={l 1, l 2..., l i..., l m, l ii-th level of representative system, i is larger, and level residing is in systems in which lower.
The technical scheme of further optimization is described step 2) in the quantitative computing method of testability index be can obtain fault by the reasoning of testability layering mixture model---the dependence matrix between test is D=[d ij], i=1,2 ..., m; J=1,2 ..., n; Fault and test between detection---false-alarm probability matrix is P (FD; FA)={ (PFD ij, PFA ij),
The computing formula of fault detect rate FDR:
F D R = &Sigma; &lambda; i &CenterDot; FDR i &Sigma; &lambda; i &times; 100 %
Wherein, FDR ifor fault f i, if there is t in the probability that may be detected jmake d ij=1, then fault f imay be detected, otherwise, fault f ican not be detected; FDR icomputing formula be:
The computing formula of single Percent Isolated:
FIR i = &lambda; i &times; &Pi; d i k = 1 P ( t k | f i ) &Sigma; j = 1 m &lambda; j &times; FDR j = &lambda; i &times; &Pi; d i k = 1 PFD i k &Sigma; j = 1 m &lambda; j &times; FDR j
The Percent Isolated that isolation is L to ambiguity group size is:
F I R ( L ) = &Sigma; L = | AG i | FIR i &times; 100 %
Wherein, f ithe computing formula of the fault isolation ambiguity group at place is:
AG i={f j|D Ri=D Rj,j∈[1,m]}
The computing formula of single fault false alarm rate:
FAR i = &lambda; i &Sigma; j = 1 m &lambda; j &times; &lsqb; 1 - &Pi; d i k &prime; = 1 ( 1 - PFA i k ) &rsqb;
The computing formula of cumulative fault false alarm rate:
F A R = &Sigma; i = 1 m FAR i .
The beneficial effect that produces of technique scheme is adopted to be: the present invention can not only carry out modeling to the dependence of the component units of modeling object, fault and test, and can the hierarchical structure of faults propagation characteristic and system; The testability layering mixture model adopted is the organic combination of graph theory and theory of probability, has solid theoretical foundation, supports qualitative analysis and quantitative test, and the function that extend testing is analyzed can provide computation model information for testability Simulation Evaluation; The testability relevant information such as expertise information, history Test Information can be fully utilized simultaneously, solving complex equipment due to test figure lacks, be difficult to a difficult problem of carrying out testability modeling and assessment, Simulation Evaluation result is more close to the authentic testing level of equipment.
Accompanying drawing explanation
Fig. 1 is the functional module c of the embodiment of the present invention 1 1model schematic;
Fig. 2 is the functional module c of the embodiment of the present invention 1 2model schematic;
Fig. 3 is the testability layering mixture model of the embodiment of the present invention 1;
Fig. 4 is the schematic diagram of changing one's profession of the testability Bayesian network model of the testability layering mixture model of the embodiment of the present invention 1;
Fig. 5 is the testability layered modeling process flow diagram of the embodiment of the present invention 1.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The present invention is kind of an electronics testability modeling appraisal procedure, and the method comprises the following steps:
1) clear and definite modeling object; Carrying out schematic model, testability structural model and failure mode effect and HAZAN to being modeled equipment, identifying and extracting Composition and distribution, fault mode and the detecting information equipped, and partition structure level, be clearly modeled each component units of equipment;
2) testability layering mixture model builds;
A, according to analysis to change system, set up each functional module of change system, the submodel fragment of incidence relation between fault and test;
B, according to the propagation relation of fault mode and the functional relationship of system architecture, each submodel to be coupled together, set up the whole testability layering mixture model being modeled change system;
C, according to accessibility principle, testability layering mixture model can be converted into the expectation that Bayes's testability model carries out testability quantitative target;
3) the testability layering mixture model built is adjusted, revises and verified, the order of accuarcy of the constructed model of assessment;
4) equipment Test is analyzed and assessment;
A, prior distribation by expertise determination node condition probability;
B, test figure is utilized to upgrade conditional probability prior distribation;
C, the testability of utilization layering mixture model reasoning to equipment are assessed.
The technical scheme of further optimization is described step 2) in testability layering mixture model comprise system component units finite set C, fault mode finite set F, test finite set T, directed edge finite set E, node condition conceptual schema collection P;
System component units finite set C:C={c 1, c 2..., c i..., c m, c i(1≤i≤m) represents i-th component units; Incidence relation between component units can be expressed as CC={c ic j, c ic j=<c i, c j> represents component units c iand c jbetween incidence relation, c i, c j∈ C;
Fault mode finite set F:F={f 1, f 2..., f i..., f n, f i(1≤i≤n) represents i-th kind of fault mode, and the subordinate relation between system failure mode and component units can be expressed as CF={c if j, c if j=<c i, f j> represents parts c iwith fault f jbetween subordinate relation, c i∈ C, f j∈ F;
Test finite set T:T={t 1, t 2..., t i..., t l, t i(1≤i≤l) represents i-th test, specifies that each test is two-value, namely passes through and does not pass through; Mapping relations between fault mode and test can be expressed as FT={f it j, f it j=<f i, t j> representing fault pattern f iwith test t jbetween mapping relations, f i∈ F, t j∈ T;
Directed edge finite set E: represent fault mode f iwith test t jbetween information flow, represent fault mode f kwith fault mode f lbetween information flow, represent test t gwith test t hbetween information flow;
Node condition probability set P:P={ (FD ij, FA ij), (FD ij, FA ij) for detecting---false-alarm probability pair; Wherein FD ijrepresent by t jthe source of trouble f of monitoring itime abnormal, test t jalso abnormal probability; FA ijrepresent by t jthe source of trouble f of monitoring itime normal, test t jalso abnormal probability.
The technical scheme of further optimization is that described testability layering mixture model also comprises systemic-function collection G:G={g 1, g 2..., g i..., g k, g i(1≤i≤k) representative system i-th function; Interact relation between function and fault mode can be expressed as FG={f ig j, f ig j=<f i, g j> representing fault pattern f iwith function g jbetween mapping relations, f i∈ F, g j∈ G;
The failure rate λ={ λ of fault mode 1, λ 2..., λ i..., λ n,
λ itabular form fault mode f ifailure rate;
Fault mode F and the correlation matrix D:D=[d testing T ij], be m × n dimension, each test t jrow of (1≤j≤n) homography: wherein d jrepresenting matrix D jth arranges; If test t j(1≤j≤n) can detect fault mode f i, then d ijbe 1, otherwise be 0;
System level unit L={l 1, l 2..., l i..., l m, l ii-th level of representative system, i is larger, and level residing is in systems in which lower.
The technical scheme of further optimization is described step 2) in the quantitative computing method of testability index be can obtain fault by the reasoning of testability layering mixture model---the dependence matrix between test is D=[d ij], i=1,2 ..., m; J=1,2 ..., n; Fault and test between detection---false-alarm probability matrix is P (FD; FA)={ (PFD ij, PFA ij);
The computing formula of fault detect rate FDR:
F D R = &Sigma; &lambda; i &CenterDot; FDR i &Sigma; &lambda; i &times; 100 %
Wherein, FDR ifor fault f i, if there is t in the probability that may be detected jmake d ij=1, then fault f imay be detected, otherwise, fault f ican not be detected; FDR icomputing formula be:
The computing formula of single Percent Isolated:
FIR i = &lambda; i &times; &Pi; d i k = 1 P ( t k | f i ) &Sigma; j = 1 m &lambda; j &times; FDR j = &lambda; i &times; &Pi; d i k = 1 PFD i k &Sigma; j = 1 m &lambda; j &times; FDR j
The Percent Isolated that isolation is L to ambiguity group size is:
F I R ( L ) = &Sigma; L = | AG i | FIR i &times; 100 %
Wherein, f ithe computing formula of the fault isolation ambiguity group at place is:
AG i={f j|D Ri=D Rj,j∈[1,m]}
The computing formula of single fault false alarm rate:
FAR i = &lambda; i &Sigma; j = 1 m &lambda; j &times; &lsqb; 1 - &Pi; d i k &prime; = 1 ( 1 - PFA i k ) &rsqb;
The computing formula of cumulative fault false alarm rate:
F A R = &Sigma; i = 1 m FAR i .
Embodiment 1:
Certain system is by two functional module c 1and c 2composition, total f 1, f 2, f 3, f 4, f 5, f 6and f 7deng 7 fault modes, devise t 1, t 2, t 3, t 4, t 5and t 5deng 5 tests.According to the functional module c that testability layering hybrid modeling method is set up 1model fragment as shown in Figure 1.This functional module has 4 fault mode f 1, f 2, f 3and f 4, corresponding 3 test t 1, t 2and t 3.
According to the functional module c that testability layering hybrid modeling method is set up 2model fragment as shown in Figure 2.This functional module has 3 fault mode f 5, f 6and f 7, corresponding 2 test t 4and t 5.
After the model fragment of each functional module establishes, according to module relation relation and fault propagation relation, each model fragment is coupled together, set up the testability layering mixture model of whole system, as shown in Figure 3.Wherein functional module c 1fault mode f 1, f 2, f 3cause functional module c respectively 2break down pattern f 4, f 5, f 6.
For the ease of carrying out testability prediction assessment, needing the node propagation characteristic based on digraph, setting up fault mode collection and the direct incidence relation of test set.According to model conversion step, first, determine location mode node in testability Bayesian network model, and generate separate observation node.Then, in testability layering mixture model, the annexation of structure is directly converted to the annexation in testability Bayesian network model, sets up the connection between observation node and location mode node, generates the testability Bayesian network model shown in Fig. 4.
Whole modeling procedure as shown in Figure 5, comprise the foundation of testability layering mixture model fragment, annexation analysis between testability layering mixture model fragment, whole testability layering mixture model build and testability layering mixture model to the conversion of testability Bayesian network model.
Visible, adopt testability layering mixture model can either fully demonstrate the dependence of fault mode and test, be applicable to very much again setting up with different levels Complex System Models, not only can the architectural feature of characterization system, and also simple and clear.In addition, when certain part needs only need change corresponding model fragment during variation, whole model need not be changed, be with good expansibility.
The present embodiment in conjunction with the testability quantitative target modelling in IEEEStd1522 standard based on the testability index quantitative calculation method of testability layering mixture model.After making property layering mixture model reasoning after tested, obtaining fault---the dependence matrix between test is D=[d ij], i=1,2 ..., m; J=1,2 ..., n; Fault and test between detection---false-alarm probability matrix is P (FD; FA)={ (PFD ij, PFA ij), with reference to the information model definition of the FDR provided in IEEEStd1522 standard, the computing formula given based on the FDR of testability layering mixture model is as follows:
F D R = &Sigma; &lambda; i &CenterDot; FDR i &Sigma; &lambda; i &times; 100 %
Wherein, FDR ifor fault f i, if there is t in the probability that may be detected jmake d ij=1, then fault f imay be detected, otherwise, fault f ican not be detected.FDR icomputing formula be:
When calculating Percent Isolated, first fault will be divided into multiple separate fault isolation ambiguity group, each fault isolation ambiguity group comprises l fault element, l ∈ 1,2 ..., m}.Fault ambiguity group refers to have same characteristic features, can not by the fault group of uniquely isolating.If D riand D rjfor two row vectors any in matrix D, and i ≠ j, if D ri=D rj, i.e. d ik=d jk(k=1,2 ..., n), illustrate and work as f ior f jwhen breaking down, at t kon the information that shows be the same, therefore f iwith f jfor the fault of undistinguishable, they can be classified as an ambiguity group, similar can be classified as an ambiguity group by multiple fault.F ithe computing formula of the fault isolation ambiguity group at place is:
AG i={f j|D Ri=D Rj,j∈[1,m]}
Single fault hypothesis requires f iduring generation, all detection f itest all do not pass through, fault f ijust can be isolated.The isolation rate defining single fault is in testability layering mixture model framework, and the test set that provides of using a model makes the ratio of the segregate failure rate of single fault and the total failare rate of the fault detected, then f isegregate probability is:
FIR i = &lambda; i &times; &Pi; d i k = 1 P ( t k | f i ) &Sigma; j = 1 m &lambda; j &times; FDR j = &lambda; i &times; &Pi; d i k = 1 PFD i k &Sigma; j = 1 m &lambda; j &times; FDR j
The Percent Isolated that isolation is L to ambiguity group size is:
F I R ( L ) = &Sigma; L = | AG i | FIR i &times; 100 %
Think in IEEEStd1522 that fault false alarm rate is unpredicted, for this reason not to the computing method of the false alarm rate that is out of order.Defining single fault test false alarm rate is herein that the use a model test set that provides carries out the false alarm rate of single fault detect, and computing formula is as follows:
FAR i = &lambda; i &Sigma; j = 1 m &lambda; j &times; &lsqb; 1 - &Pi; d i k &prime; = 1 ( 1 - PFA i k ) &rsqb;
As can be seen from formula, when detecting for same fault, association test is more, and the probability of false-alarm is larger.Cumulative fault expects that false alarm rate is:
F A R = &Sigma; i = 1 m FAR i
Testability layering hybrid modeling method can carry out dependence modeling for the parts of object, fault and test etc., and the hierarchical structure of energy faults propagation characteristic and system; The testability relevant information such as expertise information, history Test Information can be fully utilized simultaneously, solving complex equipment due to test figure lacks, be difficult to a difficult problem of carrying out testability modeling and assessment, Simulation Evaluation result is more close to the authentic testing level of equipment.

Claims (4)

1. an electronics testability modeling appraisal procedure, is characterized in that: the method comprises the following steps:
1) clear and definite modeling object; Carrying out schematic model, testability structural model and failure mode effect and HAZAN to being modeled equipment, identifying and extracting Composition and distribution, fault mode and the detecting information equipped, and partition structure level, be clearly modeled each component units of equipment;
2) testability layering mixture model builds;
A, according to analysis to change system, set up each functional module of change system, the submodel fragment of incidence relation between fault and test;
B, according to the propagation relation of fault mode and the functional relationship of system architecture, each submodel to be coupled together, set up the whole testability layering mixture model being modeled change system;
C, according to accessibility principle, testability layering mixture model can be converted into the expectation that Bayes's testability model carries out testability quantitative target;
3) the testability layering mixture model built is adjusted, revises and verified, the order of accuarcy of the constructed model of assessment;
4) equipment Test is analyzed and assessment;
A, prior distribation by expertise determination node condition probability;
B, test figure is utilized to upgrade conditional probability prior distribation;
C, the testability of utilization layering mixture model reasoning to equipment are assessed.
2. a kind of electronics testability modeling appraisal procedure according to claim 1, is characterized in that: described step 2) the testability layering mixture model described in b comprise system component units finite set C, fault mode finite set F, test finite set T, directed edge finite set E, node condition conceptual schema collection P;
System component units finite set C:C={c 1, c 2..., c i..., c m, c i(1≤i≤m) represents i-th component units; Incidence relation between component units can be expressed as CC={c ic j, c ic j=<c i, c j> represents component units c iand c jbetween incidence relation, c i, c j∈ C;
Fault mode finite set F:F={f 1, f 2..., f i..., f n, f i(1≤i≤n) represents i-th kind of fault mode, and the subordinate relation between system failure mode and component units can be expressed as CF={c if j, c if j=<c i, f j> represents parts c iwith fault f jbetween subordinate relation, c i∈ C, f j∈ F;
Test finite set T:T={t 1, t 2..., t i..., t l, t i(1≤i≤l) represents i-th test, specifies that each test is two-value, namely passes through and does not pass through; Mapping relations between fault mode and test can be expressed as FT={f it j, f it j=<f i, t j> representing fault pattern f iwith test t jbetween mapping relations, f i∈ F, t j∈ T;
Directed edge finite set E: represent fault mode f iwith test t jbetween information flow, represent fault mode f kwith fault mode f lbetween information flow, represent test t gwith test t hbetween information flow;
Node condition probability set P:P={ (FD ij, FA ij), (FD ij, FA ij) for detecting---false-alarm probability pair; Wherein FD ijrepresent by t jthe source of trouble f of monitoring itime abnormal, test t jalso abnormal probability; FA ijrepresent by t jthe source of trouble f of monitoring itime normal, test t jalso abnormal probability.
3. a kind of electronics testability modeling appraisal procedure according to claim 2, is characterized in that: described testability layering mixture model also comprises systemic-function collection G:G={g 1, g 2..., g i..., g k, g i(1≤i≤k) representative system i-th function; Interact relation between function and fault mode can be expressed as FG={f ig j, f ig j=<f i, g j> representing fault pattern f iwith function g jbetween mapping relations, f i∈ F, g j∈ G;
The failure rate λ={ λ of fault mode 1, λ 2..., λ i..., λ n,
λ itabular form fault mode f ifailure rate;
Fault mode F and the correlation matrix D:D=[d testing T ij], be m × n dimension, each test t jrow a: d of (1≤j≤n) homography j t=[d 1jd mj], wherein d jrepresenting matrix D jth arranges; If test t j(1≤j≤n) can detect fault mode f i, then d ijbe 1, otherwise be 0;
System level unit L={l 1, l 2..., l i..., l m, l ii-th level of representative system, i is larger, and level residing is in systems in which lower.
4. a kind of electronics testability modeling appraisal procedure according to claim 1, is characterized in that: described step 2) c in the quantitative computing method of testability index be can obtain fault by the reasoning of testability layering mixture model---the dependence matrix between test is D=[d ij], i=1,2 ..., m; J=1,2 ..., n; Fault and test between detection---false-alarm probability matrix is P (FD; FA)={ (PFD ij, PFA ij);
The computing formula of fault detect rate FDR:
F D R = &Sigma;&lambda; i &CenterDot; FDR i &Sigma;&lambda; i &times; 100 %
Wherein, FDR ifor fault f i, if there is t in the probability that may be detected jmake d ij=1, then fault f imay be detected, otherwise, fault f ican not be detected; FDR icomputing formula be:
The computing formula of single Percent Isolated:
FIR i = &lambda; i &times; &Pi; d i k = 1 P ( t k | f i ) &Sigma; j = 1 m &lambda; i &times; FDR j = &lambda; i &times; &Pi; d i k = 1 PFD i k &Sigma; j = 1 m &lambda; j &times; FDR j
The Percent Isolated that isolation is L to ambiguity group size is:
F I R ( L ) = &Sigma; L = | AG i | FIR i &times; 100 %
Wherein, f ithe computing formula of the fault isolation ambiguity group at place is:
AG i={f j|D Ri=D Rj,j∈[1,m]}
The computing formula of single fault false alarm rate:
FAR i = &lambda; i &Sigma; j = 1 m &lambda; j &times; &lsqb; 1 - &Pi; d i k &prime; = 1 ( 1 - PFA i k ) &rsqb;
The computing formula of cumulative fault false alarm rate:
F A R = &Sigma; i = 1 m FAR i .
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109918295A (en) * 2019-02-13 2019-06-21 长沙泰斯信息科技有限公司 A kind of function coverage calculating appraisal procedure
CN111626008A (en) * 2020-05-27 2020-09-04 哈尔滨工业大学 Layered sequential testability modeling method for circuit system
CN111626622A (en) * 2020-05-28 2020-09-04 哈尔滨工业大学 Circuit system testability index prediction method considering uncertainty
CN112380084A (en) * 2020-12-05 2021-02-19 中国人民解放军32181部队 Fault injection and simulation verification method
CN113626267A (en) * 2021-07-31 2021-11-09 西南电子技术研究所(中国电子科技集团公司第十研究所) Method for evaluating uncertainty fault diagnosis efficiency of complex electronic system
CN115269401A (en) * 2022-07-22 2022-11-01 中国人民解放军海军航空大学 A Method for Generating Equipment Test Sequence Based on Hierarchical Model

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115858403B (en) * 2023-03-01 2023-06-02 中国电子科技集团公司第十研究所 False alarm rate prediction method of electronic system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020022942A1 (en) * 2000-05-11 2002-02-21 Nec Corporation Apparatus and method for producing a performance evaluation model
CN101571802A (en) * 2009-06-19 2009-11-04 北京航空航天大学 Visualization automatic generation method of embedded software test data and system thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020022942A1 (en) * 2000-05-11 2002-02-21 Nec Corporation Apparatus and method for producing a performance evaluation model
CN101571802A (en) * 2009-06-19 2009-11-04 北京航空航天大学 Visualization automatic generation method of embedded software test data and system thereof

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
吕晓明 等: "基于多信号流图的分层系统测试下建模与分析", 《北京航空航天大学学报》 *

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CN109918295A (en) * 2019-02-13 2019-06-21 长沙泰斯信息科技有限公司 A kind of function coverage calculating appraisal procedure
CN111626008A (en) * 2020-05-27 2020-09-04 哈尔滨工业大学 Layered sequential testability modeling method for circuit system
CN111626622A (en) * 2020-05-28 2020-09-04 哈尔滨工业大学 Circuit system testability index prediction method considering uncertainty
CN112380084A (en) * 2020-12-05 2021-02-19 中国人民解放军32181部队 Fault injection and simulation verification method
CN112380084B (en) * 2020-12-05 2024-03-26 中国人民解放军32181部队 Fault injection and simulation verification method
CN113626267A (en) * 2021-07-31 2021-11-09 西南电子技术研究所(中国电子科技集团公司第十研究所) Method for evaluating uncertainty fault diagnosis efficiency of complex electronic system
CN113626267B (en) * 2021-07-31 2024-07-16 西南电子技术研究所(中国电子科技集团公司第十研究所) Complex electronic system uncertainty fault diagnosis efficiency evaluation method
CN115269401A (en) * 2022-07-22 2022-11-01 中国人民解放军海军航空大学 A Method for Generating Equipment Test Sequence Based on Hierarchical Model
CN115269401B (en) * 2022-07-22 2023-09-22 中国人民解放军海军航空大学 Equipment test sequence generation method based on layering model

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