CN112367081B - Capacitor array correction system and method for successive approximation analog-to-digital converter - Google Patents
Capacitor array correction system and method for successive approximation analog-to-digital converter Download PDFInfo
- Publication number
- CN112367081B CN112367081B CN202011165074.2A CN202011165074A CN112367081B CN 112367081 B CN112367081 B CN 112367081B CN 202011165074 A CN202011165074 A CN 202011165074A CN 112367081 B CN112367081 B CN 112367081B
- Authority
- CN
- China
- Prior art keywords
- capacitor
- group
- calibrated
- controlling
- bank
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 577
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000012937 correction Methods 0.000 title claims abstract description 11
- 238000005070 sampling Methods 0.000 claims abstract description 71
- 230000009471 action Effects 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 14
- 238000004590 computer program Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000012935 Averaging Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
- H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
- H03M1/1019—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error by storing a corrected or correction value in a digital look-up table
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The embodiment of the invention provides a capacitor array correction system and method of a successive approximation type analog-digital converter, and belongs to the technical field of chips. The system comprises: the sampling circuit comprises a first comparator, a digital logic controller, a sampling switch group, a first switch group and a second switch group, wherein one sampling switch in the sampling switch group is connected between the upper polar plate of the first capacitor group and the ground, and the other sampling switch is connected between the upper polar plate of the second capacitor group and the ground; one switch of the first switch group is connected between the positive end of the first comparator and the upper pole plate of the first capacitor group, and the other switch is connected between the negative end of the first comparator and the upper pole plate of the second capacitor group; one switch of the second switch set is connected between the positive terminal of the first comparator and the upper plate of the second capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the first capacitor set. The invention can accurately calibrate the capacitor array of the successive approximation type analog-digital converter.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a capacitor array correction system and method of a successive approximation type analog-digital converter.
Background
The high-precision successive approximation type analog-digital converter gradually becomes the popular research field due to low power consumption, high conversion rate and good timeliness. The main reason for limiting the development of the high-precision successive approximation type analog-digital converter is the system error mismatch formed by a capacitor, a comparator and the like. The main reasons for mismatches in capacitance and comparators are poor process manufacturing accuracy and non-standard circuit design. The latter can be avoided but the former must be present.
In the actual circuit production process, not only capacitors, but also MOS devices have mismatch phenomena of different degrees due to different process corners and different layout positions and wiring. This makes designing high-precision capacitor circuits extremely dependent on the production process and the level of designers, and the phase change increases the production cost and the design time. The comparator self zeroing technique also has the disadvantage that it requires a high degree of matching of the capacitors.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a system and a method for calibrating a capacitor array of a successive approximation analog-to-digital converter, which can accurately calibrate the capacitor array of the successive approximation analog-to-digital converter.
In order to achieve the above object, an embodiment of the present invention provides a capacitor array calibration system for a successive approximation analog-to-digital converter, where the capacitor array includes a first capacitor bank and a second capacitor bank, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, and the capacitors of the first capacitor bank and the second capacitor bank are set correspondingly, and the system includes: the circuit comprises a first comparator, a digital logic controller, a sampling switch group, a first switch group and a second switch group, wherein one sampling switch in the sampling switch group is connected between the upper plate of the first capacitor group and the ground, and the other sampling switch is connected between the upper plate of the second capacitor group and the ground; one switch of the first switch set is connected between the positive terminal of the first comparator and the upper plate of the first capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the second capacitor set; one switch of the second switch set is connected between the positive terminal of the first comparator and the upper plate of the second capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the first capacitor set; for any capacitor of the first capacitor bank or the second capacitor bank to be calibrated, the digital logic controller is configured to: controlling the sampling switch group to be closed, and controlling the lower electrode plates of the first capacitor group and the second capacitor group to act so as to sample; controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated; controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower pole plates of the first capacitor group and the second capacitor group to act so as to perform sampling; controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated; and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
Preferably, the controlling the lower plate action of the first capacitor bank and the second capacitor bank to perform sampling includes: and controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor group where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor group to be grounded.
Preferably, the controlling the lower plate actions of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment; the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
Preferably, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, wherein theoretical capacitance values of the plurality of reference capacitors are sequentially doubled, and theoretical capacitance values of any one of the plurality of reference capacitors are smaller than theoretical capacitance values of any one of the plurality of capacitors to be calibrated.
Preferably, the system further comprises: and the digital calibration register is used for storing actual information of the corresponding capacitor to be calibrated.
Preferably, the successive approximation analog-to-digital converter includes: and the second comparator is connected with the upper electrode plates of the first capacitor group and the second capacitor group, so that the successive approximation type analog-digital converter is used when the successive approximation type analog-digital converter enters formal work after the calibration of each capacitor to be calibrated of the first capacitor group and the second capacitor group is completed.
The invention also provides a capacitor array correction method of the successive approximation type analog-digital converter, wherein the capacitor array comprises a first capacitor group and a second capacitor group, the first capacitor group and the second capacitor group respectively comprise a plurality of capacitors to be calibrated and a plurality of reference capacitors, and the capacitors of the first capacitor group and the second capacitor group are correspondingly arranged; one switch of the first switch set is connected between the positive terminal of the first comparator and the upper plate of the first capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the second capacitor set; one switch of the second switch set is connected between the positive terminal of the first comparator and the upper plate of the second capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the first capacitor set; for any capacitor to be calibrated of the first capacitor bank or the second capacitor bank, the method comprises: controlling the sampling switch group to be closed, and controlling the lower electrode plates of the first capacitor group and the second capacitor group to act so as to sample; controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated; controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower pole plates of the first capacitor group and the second capacitor group to act so as to perform sampling; controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated; and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
Preferably, the controlling the lower plate action of the first capacitor bank and the second capacitor bank to perform sampling includes: and controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor group where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor group to be grounded.
Preferably, the controlling the lower plate actions of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment; the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
Preferably, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, wherein theoretical capacitance values of the plurality of reference capacitors are sequentially doubled, and theoretical capacitance values of any one of the plurality of reference capacitors are smaller than theoretical capacitance values of any one of the plurality of capacitors to be calibrated.
According to the technical scheme, the capacitor array correction system and method of the successive approximation type analog-digital converter provided by the invention are adopted, the first comparator, the digital logic controller, the sampling switch group, the first switch group and the second switch group are used, the output of the comparator is turned over by turning over the reference capacitor, so that the relation between the capacitor to be calibrated and the turned-over reference capacitor is obtained twice, and the capacitor array of the successive approximation type analog-digital converter is accurately calibrated.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a schematic structural diagram of a capacitor array calibration system of a successive approximation analog-to-digital converter according to an embodiment of the invention;
fig. 2 is a schematic diagram of control signals of the first switch group and the second switch group according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a capacitor array calibration system of a successive approximation analog-to-digital converter according to another embodiment of the present invention;
fig. 4 is a flowchart of a method for calibrating a capacitor array of a successive approximation analog-to-digital converter according to an embodiment of the invention.
Description of the reference numerals
W1 first switch group W2 second switch group
1 first comparator 2 second comparator
3 digital logic controller 4 digital calibration register
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of a capacitor array calibration system of a successive approximation analog-to-digital converter according to an embodiment of the invention. As shown in fig. 1, the capacitor array includes a first capacitor bank and a second capacitor bank, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, and the capacitors of the first capacitor bank and the second capacitor bank are correspondingly arranged, and the system includes: the circuit comprises a first comparator 1, a digital logic controller 3, a sampling switch group (sample) and a first switch group (W1), wherein one sampling switch in the sampling switch group (sample) is connected between the upper plate of the first capacitor group and the ground, and the other sampling switch is connected between the upper plate of the second capacitor group and the ground; one switch of the first switch group (W1) is connected between the positive terminal of the first comparator 1 and the upper plate of the first capacitor group, and the other switch is connected between the negative terminal of the first comparator 1 and the upper plate of the second capacitor group.
The first capacitor bank and the second capacitor bank may respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, in which theoretical capacitance values of any one of the plurality of reference capacitors are sequentially doubled, and the theoretical capacitance value of any one of the plurality of reference capacitors is smaller than the theoretical capacitance value of any one of the plurality of capacitors to be calibrated. For example, the first capacitance group may include capacitances Cp1-Cpn, for a total of n capacitances, where the theoretical capacitance ratio Cp 1: cp 2: cp3 … … Cpn is 1: 2: 4 … … 2n-1. The second capacitance group may include capacitances Cn1-Cnn, for a total of n capacitances, where the theoretical capacitance ratio Cn 1: cn 2: cn3 … … Cnn is 1: 2: 4 … … 2n-1. In practice, however, the actual weighting of the capacitances (i.e. the capacitance ratio) is not the ideal case due to mismatches in the integrated circuit. Typically, the mismatch of the lower bits is negligible, while the mismatch of the higher bits affects the performance of the digitizer. The invention can take the low position Cp1-Cp6, Cn1-Cn6 as reference capacitance, and the high position Cp7-Cpn, Cn7-Cnn as capacitance to be calibrated. The invention calibrates the capacitors to be calibrated.
For any capacitance to be calibrated of the first capacitance group or the second capacitance group, the digital logic controller 3 is configured to: controlling the sampling switch group (sample) to be closed, and controlling the lower pole plate of the corresponding capacitor to be calibrated to be grounded, the lower pole plates of a plurality of reference capacitors of the capacitor group where the corresponding capacitor to be calibrated is located to be connected with a reference voltage, and the lower pole plates of a plurality of reference capacitors of the other capacitor group to be grounded; controlling the first switch group (W1) to be closed, the sampling switch group (sample) to be opened, and controlling the lower plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in another capacitor bank until the output of the first comparator 1 is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located; and obtaining actual information of the capacitance to be calibrated according to the recorded first information.
For example, the embodiment of the present invention may calibrate the minimum capacitor to be calibrated first, i.e. for the capacitor Cp7, first, the digital logic controller 3 controls sample to be closed and W1 to be opened, which allows the upper plates of all capacitors (including the reference capacitor and the capacitor to be calibrated) to be grounded (VSS). At the same time, the digital control logic controls the lower plate of Cp0-Cp6 to be connected with a reference Voltage (VREF), the lower plate of Cp7 to be connected with VSS, and the lower plate of Cn0-Cn6 to be connected with VSS. For other capacitors, a direct VSS or a direct VREF may be maintained.
After sampling is finished, the digital logic controller 3 controls sample to be opened and W1 to be closed. The digital logic controller 3 controls the switching of the lower plate of Cp7 from being connected with VSS to being connected with VREF, then at least one capacitor of Cp0-Cp6 is inverted, namely, the capacitor is inverted from being connected with VREF to being connected with VSS, and correspondingly arranged capacitors in Cn0-Cn6 are inverted in the opposite direction, namely, the capacitor is inverted from being connected with VSS to being connected with VREF. Based on this, the inversion is performed using successive approximation, for example, assuming that the weight of Cp7 deviates from 64 to 63, it is first verified whether 64 is greater than 32(C6 inverts first), if greater than 32 (first comparator 1 results in 1), it is next verified whether greater than 32+16(C6 and C5 invert together) for comparison, and so on until the first comparator 1 output inverts, i.e., the result is from 1 to 0. When the first comparator 1 is flipped, the weight of the capacitor with calibration is considered equal to the sum of the flipped capacitors in the remaining capacitors. At this time, information (i.e., first information) of all reference capacitances, for example, weights, inverted by the capacitance group in which Cp7 is located are recorded. The sum of the weights of all the reference capacitances flipped is the weight of Cp 7.
However, in practical situations, an offset voltage may be generated at the input terminal of the first comparator 1 to affect the calibration accuracy, for example, an analog voltage generated by inverting the Cp7 side is supplied to the positive terminal of the first comparator 1, and the voltage is UCp7+ Δ (offset voltage), to which the present invention also provides a solution, as described below.
The system further comprises: a second switch group (W2), one switch of the second switch group (W2) being connected between the positive terminal of the first comparator 1 and the upper plate of the second capacitor group, the other switch being connected between the negative terminal of the first comparator 1 and the upper plate of the first capacitor group.
The digital logic controller 3, after recording the first information, is further configured to: controlling the sampling switch group to be closed, the first switch group (W1) to be opened, and controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor group where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor group to be grounded; controlling the second switch group (W2) to be closed, the sampling switch group (sample) to be opened, and controlling the lower plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in another capacitor bank until the output of the first comparator 1 is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located; and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
For example, after obtaining the first information described above, the digital logic controller 3 controls sample to be closed and both W1 and W2 to be open, which allows the upper plates of all capacitors (including the reference capacitor and the capacitor to be calibrated) to be VSS. Meanwhile, the digital control logic controls the lower pole plate of Cp0-Cp6 to be connected with VREF, the lower pole plate of Cp7 to be connected with VSS, and the lower pole plate of Cn0-Cn6 to be connected with VSS. For other capacitors, a direct VSS or a direct VREF may be maintained.
After sampling is finished, the digital logic controller 3 controls sample to be opened and W2 to be closed. The digital logic controller 3 controls the lower plate of Cp7 to be switched from VSS to VSSVREF, and then flip Cp0-Cp6 and Cn0-Cn6 using a successive approximation until the first comparator 1 output flips. At this time, information (i.e., second information) of all reference capacitances (i.e., weights) inverted by the capacitance group in which Cp7 is located is recorded. The sum of the weights of all the reference capacitances flipped is also the weight of Cp 7. However, in this calibration, the analog voltage generated by the side-flip of Cp7 is supplied to the negative terminal of the first comparator 1, and the voltage is UCp7- Δ, so that the results from the calibrations using W1 and using W2 are summed and averaged to offset the systematic offset, a more accurate weight of Cp7 can be obtained. It will be appreciated that the above-described calibration method using W1 and W2 is repeated a number of times, and that the results are further refined by summing all the results and averaging.
After the calibration of Cp7 is completed, Cn7 may be calibrated in the same manner, and then the calibrated capacitor may be used as a reference capacitor to continue calibrating the higher-order capacitor, or the above-mentioned method of adding and averaging the calibration results using W1 and W2 may be applied to perform calibration, which is not described herein again.
Fig. 2 is a schematic diagram of control signals of the first switch group and the second switch group according to an embodiment of the present invention. As shown in fig. 2, W1 and W2 are two pairs of non-overlapping alternating switches, strictly ensuring that the W1 signal and the W2 signal cannot be high at the same time, i.e., that W1 and W2 are not turned off at the same time.
Fig. 3 is a schematic structural diagram of a capacitor array calibration system of a successive approximation analog-to-digital converter according to another embodiment of the invention. As shown in fig. 3, the system further includes: and the digital calibration register 4 is used for storing actual information of the corresponding capacitor to be calibrated. The successive approximation analog-to-digital converter includes: and the second comparator 2 is connected with the upper electrode plates of the first capacitor group and the second capacitor group, so that the successive approximation type analog-digital converter is used when the successive approximation type analog-digital converter enters formal work after the calibration of each capacitor to be calibrated of the first capacitor group and the second capacitor group is completed.
The second comparator 2 is identical to the first comparator 1, and is also matched strictly during layout design. In normal operation, the second comparator 2 is put into operation and the actual information of the capacitor to be calibrated in the digital calibration register 4 can be used directly. The present invention uses the first comparator 1 and its associated circuitry for capacitance calibration so as not to affect the signal path under normal operating conditions.
Fig. 4 is a flowchart of a method for calibrating a capacitor array of a successive approximation analog-to-digital converter according to an embodiment of the invention. As shown in fig. 4, the capacitor array includes a first capacitor group and a second capacitor group, the first capacitor group and the second capacitor group respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, and the capacitors of the first capacitor group and the second capacitor group are correspondingly arranged, wherein the method is based on a first comparator, a sampling switch group, a first switch group and a second switch group, wherein one sampling switch in the sampling switch group is connected between the upper plate of the first capacitor group and ground, and the other sampling switch is connected between the upper plate of the second capacitor group and ground; one switch of the first switch set is connected between the positive terminal of the first comparator and the upper plate of the first capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the second capacitor set; one switch of the second switch set is connected between the positive terminal of the first comparator and the upper plate of the second capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the first capacitor set; for any capacitor to be calibrated of the first capacitor bank or the second capacitor bank, the method comprises:
step S41, controlling the sampling switch group to be closed, and controlling the lower plates of the first capacitor group and the second capacitor group to act so as to perform sampling;
step S42, controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated;
step S43, controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower plates of the first capacitor group and the second capacitor group to act so as to perform sampling;
step S44, controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated;
step S45, obtaining actual information of the capacitance to be calibrated according to the recorded first information and second information.
Preferably, the controlling the lower plate action of the first capacitor bank and the second capacitor bank to perform sampling includes: controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor bank to be grounded;
preferably, the controlling the lower plate actions of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment; the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
Preferably, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, wherein theoretical capacitance values of the plurality of reference capacitors are sequentially doubled, and theoretical capacitance values of any one of the plurality of reference capacitors are smaller than theoretical capacitance values of any one of the plurality of capacitors to be calibrated.
The capacitor array calibration method of the successive approximation analog-to-digital converter is similar to the embodiment of the capacitor array calibration system of the successive approximation analog-to-digital converter, and is not repeated here.
An embodiment of the present invention provides a storage medium having a program stored thereon, where the program is executed by a processor to implement the capacitor array calibration method of a successive approximation analog-to-digital converter.
The embodiment of the invention provides a processor, which is used for running a program, wherein the program is used for executing the capacitor array correction method of the successive approximation type analog-digital converter during running.
The embodiment of the invention provides equipment, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein the processor executes the program and realizes the following steps:
controlling the sampling switch group to be closed, and controlling the lower electrode plates of the first capacitor group and the second capacitor group to act so as to sample; controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated; controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower pole plates of the first capacitor group and the second capacitor group to act so as to perform sampling; controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated; and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
Preferably, the controlling the lower plate action of the first capacitor bank and the second capacitor bank to perform sampling includes: controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor bank to be grounded;
preferably, the controlling the lower plate actions of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment; the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
Preferably, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, wherein theoretical capacitance values of the plurality of reference capacitors are sequentially doubled, and theoretical capacitance values of any one of the plurality of reference capacitors are smaller than theoretical capacitance values of any one of the plurality of capacitors to be calibrated.
The device herein may be a server, a PC, a PAD, a mobile phone, etc.
The present application further provides a computer program product adapted to perform a program for initializing the following method steps when executed on a data processing device:
controlling the sampling switch group to be closed, and controlling the lower electrode plates of the first capacitor group and the second capacitor group to act so as to sample; controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated; controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower pole plates of the first capacitor group and the second capacitor group to act so as to perform sampling; controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated; and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
Preferably, the controlling the lower plate action of the first capacitor bank and the second capacitor bank to perform sampling includes: controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor bank to be grounded;
preferably, the controlling the lower plate actions of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment; the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes: controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage; and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
Preferably, the first capacitor bank and the second capacitor bank respectively include a plurality of capacitors to be calibrated and a plurality of reference capacitors, wherein theoretical capacitance values of the plurality of reference capacitors are sequentially doubled, and theoretical capacitance values of any one of the plurality of reference capacitors are smaller than theoretical capacitance values of any one of the plurality of capacitors to be calibrated.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A capacitor array correction system of a successive approximation analog-digital converter, wherein the capacitor array comprises a first capacitor bank and a second capacitor bank, the first capacitor bank and the second capacitor bank respectively comprise a plurality of capacitors to be calibrated and a plurality of reference capacitors, and the capacitors of the first capacitor bank and the second capacitor bank are correspondingly arranged, the system is characterized by comprising:
the circuit comprises a first comparator, a digital logic controller, a sampling switch group, a first switch group and a second switch group, wherein one sampling switch in the sampling switch group is connected between the upper plate of the first capacitor group and the ground, and the other sampling switch is connected between the upper plate of the second capacitor group and the ground; one switch of the first switch set is connected between the positive terminal of the first comparator and the upper plate of the first capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the second capacitor set; one switch of the second switch set is connected between the positive terminal of the first comparator and the upper plate of the second capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the first capacitor set;
for any capacitor of the first capacitor bank or the second capacitor bank to be calibrated, the digital logic controller is configured to:
controlling the sampling switch group to be closed, and controlling the lower electrode plates of the first capacitor group and the second capacitor group to act so as to sample;
controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated;
controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower pole plates of the first capacitor group and the second capacitor group to act so as to perform sampling;
controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated;
and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
2. The system of claim 1, wherein the controlling the bottom plate of the first capacitor bank and the second capacitor bank to perform sampling comprises:
and controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor group where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor group to be grounded.
3. The capacitance array correction system of a successive approximation analog-to-digital converter according to claim 2,
the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes:
controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage;
controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment;
the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes:
controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage;
and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
4. The system according to claim 1, wherein the first capacitor bank and the second capacitor bank respectively comprise a plurality of capacitors to be calibrated and a plurality of reference capacitors with theoretical capacitance values being sequentially doubled, and wherein the theoretical capacitance value of any one of the plurality of reference capacitors is smaller than that of any one of the plurality of capacitors to be calibrated.
5. The system of claim 1 or 2, further comprising:
and the digital calibration register is used for storing actual information of the corresponding capacitor to be calibrated.
6. The capacitance array correction system of a successive approximation analog-to-digital converter according to claim 1, wherein the successive approximation analog-to-digital converter comprises:
and the second comparator is connected with the upper electrode plates of the first capacitor group and the second capacitor group, so that the successive approximation type analog-digital converter is used when the successive approximation type analog-digital converter enters formal work after the calibration of each capacitor to be calibrated of the first capacitor group and the second capacitor group is completed.
7. A capacitor array correction method of a successive approximation type analog-digital converter is disclosed, wherein a capacitor array comprises a first capacitor group and a second capacitor group, the first capacitor group and the second capacitor group respectively comprise a plurality of capacitors to be calibrated and a plurality of reference capacitors, and the capacitors of the first capacitor group and the second capacitor group are correspondingly arranged; one switch of the first switch set is connected between the positive terminal of the first comparator and the upper plate of the first capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the second capacitor set; one switch of the second switch set is connected between the positive terminal of the first comparator and the upper plate of the second capacitor set, and the other switch is connected between the negative terminal of the first comparator and the upper plate of the first capacitor set; for any capacitor to be calibrated of the first capacitor bank or the second capacitor bank, the method comprises:
controlling the sampling switch group to be closed, and controlling the lower electrode plates of the first capacitor group and the second capacitor group to act so as to sample;
controlling the first switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording first information of the corresponding capacitor to be calibrated;
controlling the sampling switch group to be closed, the first switch group to be opened, and controlling the lower pole plates of the first capacitor group and the second capacitor group to act so as to perform sampling;
controlling the second switch group to be closed, the sampling switch group to be opened, controlling the lower pole plates of the first capacitor group and the second capacitor group to act, and recording second information of the corresponding capacitor to be calibrated;
and obtaining actual information of the capacitance to be calibrated according to the recorded first information and the second information.
8. The method of claim 7, wherein the controlling the bottom plate of the first capacitor bank and the second capacitor bank to perform sampling comprises:
and controlling the lower plate of the corresponding capacitor to be calibrated to be grounded, the lower plates of a plurality of reference capacitors of the capacitor group where the corresponding capacitor to be calibrated is located to be grounded, and the lower plates of a plurality of reference capacitors of the other capacitor group to be grounded.
9. The method of claim 8, wherein the method comprises the steps of,
the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the first information of the capacitor to be calibrated includes:
controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage;
controlling the lower pole plate of at least one reference capacitor in a plurality of reference capacitors of a capacitor bank where the corresponding capacitor to be calibrated is located to overturn between grounding and reference voltage in a successive approximation mode, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording first information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment;
the controlling the lower plate action of the first capacitor bank and the second capacitor bank, and the recording of the second information of the capacitor to be calibrated includes:
controlling the lower pole plate of the corresponding capacitor to be calibrated to be connected with a reference voltage;
and controlling the lower plate of at least one reference capacitor in the plurality of reference capacitors of the capacitor bank where the corresponding capacitor to be calibrated is located to overturn between the ground and the reference voltage in a successive approximation manner, and reversely overturning the reference capacitor correspondingly arranged in the other capacitor bank until the output of the first comparator is overturned, and recording second information of the overturned reference capacitor in the capacitor bank where the corresponding capacitor to be calibrated is located at the moment.
10. The method according to claim 7, wherein the first capacitor bank and the second capacitor bank respectively comprise a plurality of capacitors to be calibrated and a plurality of reference capacitors with theoretical capacitance values being sequentially doubled, and wherein the theoretical capacitance value of any one of the plurality of reference capacitors is smaller than that of any one of the plurality of capacitors to be calibrated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011165074.2A CN112367081B (en) | 2020-10-27 | 2020-10-27 | Capacitor array correction system and method for successive approximation analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011165074.2A CN112367081B (en) | 2020-10-27 | 2020-10-27 | Capacitor array correction system and method for successive approximation analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112367081A CN112367081A (en) | 2021-02-12 |
| CN112367081B true CN112367081B (en) | 2022-01-14 |
Family
ID=74510426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011165074.2A Active CN112367081B (en) | 2020-10-27 | 2020-10-27 | Capacitor array correction system and method for successive approximation analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112367081B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113922820B (en) * | 2021-12-15 | 2022-05-13 | 之江实验室 | Discontinuous buffer circuit based on background calibration and analog-to-digital converter |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873059A (en) * | 2014-03-10 | 2014-06-18 | 天津大学 | Digital calibration method for high-precision SAR ADC (successive approximation register analog to digital converter) |
| CN104168020A (en) * | 2014-08-19 | 2014-11-26 | 复旦大学 | Capacitive nonlinear calibration circuit of bit-by-bit approximation analog-digital converter and method |
| CN111614354A (en) * | 2020-05-14 | 2020-09-01 | 和芯星通（上海）科技有限公司 | Calibration circuit for capacitance weight of analog-to-digital converter |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013201691A (en) * | 2012-03-26 | 2013-10-03 | Toshiba Corp | Successive approximation a/d converter |
-
2020
- 2020-10-27 CN CN202011165074.2A patent/CN112367081B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873059A (en) * | 2014-03-10 | 2014-06-18 | 天津大学 | Digital calibration method for high-precision SAR ADC (successive approximation register analog to digital converter) |
| CN104168020A (en) * | 2014-08-19 | 2014-11-26 | 复旦大学 | Capacitive nonlinear calibration circuit of bit-by-bit approximation analog-digital converter and method |
| CN111614354A (en) * | 2020-05-14 | 2020-09-01 | 和芯星通（上海）科技有限公司 | Calibration circuit for capacitance weight of analog-to-digital converter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112367081A (en) | 2021-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11436478B2 (en) | Control circuit for multiply accumulate circuit of neural network system | |
| JP5427663B2 (en) | A / D converter | |
| US7366021B2 (en) | Method and apparatus for sensing flash memory using delta sigma modulation | |
| CN111833934B (en) | Storage and calculation integrated ferroelectric memory and operation method thereof | |
| CN112367081B (en) | Capacitor array correction system and method for successive approximation analog-to-digital converter | |
| US20230198535A1 (en) | Calibration method of capacitor array type successive approximation register analog-to-digital converter | |
| US8847801B2 (en) | Calibration systems and methods for digital-to-analog converter | |
| Lee et al. | A charge-sharing based 8t sram in-memory computing for edge dnn acceleration | |
| CN103746693A (en) | Calibration circuit eliminating capacitor mismatch error | |
| CN111614354B (en) | Calibration circuit for capacitance weight of analog-to-digital converter | |
| US20120133541A1 (en) | Analog-digital converter | |
| JP2000031824A (en) | Offset cancel comparator for a/d converter | |
| Yang et al. | A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion | |
| US11128311B1 (en) | Analog-to-digital converting system and method with offset and bit-weighting correction mechanisms | |
| JP2014042358A (en) | A/d converter | |
| CN115525250A (en) | Memory computing circuit | |
| US10910072B1 (en) | Accurate self-calibrated negative to positive voltage conversion circuit and method | |
| Zang et al. | Temperature Compensation on SRAM-Based Computation in Memory Array | |
| CN115940949B (en) | Split capacitor structure successive approximation analog-to-digital converter calibration circuit and method | |
| US20210181777A1 (en) | Voltage generation system and method for negative and positive voltage driven systems | |
| CN116938245B (en) | Analog-to-digital converter calibration method and analog-to-digital converter | |
| CN116318142B (en) | Analog-to-digital converter calibration method and analog-to-digital converter | |
| CN114280998B (en) | Logic operation control circuit, method, device and medium | |
| CN117879602A (en) | Capacitor mismatch calibration circuit for SAR ADC and calibration method thereof | |
| RU2812300C2 (en) | Reading amplifier, memory and control method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20210212 Assignee: CHINA GRIDCOM Co.,Ltd. Assignor: BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY Co.,Ltd. Contract record no.: X2024980004798 Denomination of invention: A capacitive array calibration system and method for successive approximation analog-to-digital converters Granted publication date: 20220114 License type: Common License Record date: 20240423 |