CN117879602A - Capacitor mismatch calibration circuit for SAR ADC and calibration method thereof - Google Patents

Abstract

The application provides a capacitor mismatch calibration circuit for an SAR ADC and a calibration method thereof, and relates to the technical field of analog-to-digital conversion. According to the method, on the basis of combining the time domain comparator with the time-digital converter in the traditional scheme, SAR ADC self-calibration control logic is additionally arranged, namely, after the steps of acquiring first voltage difference information and second voltage difference information when the upper polar plate of the low-level differential capacitor respectively generates differential voltages of 1LSB and 2LSB and the linear function relation between the differential voltages generated by the upper polar plate of the low-level differential capacitor and the oscillation times of the oscillator in the time-digital converter, SAR ADC successive approximation conversion step is additionally arranged, so that the differential voltages generated by the upper polar plate of the differential capacitor are always in the range of 2LSB, and then the quantization process of the time domain comparator and the time-digital converter is carried out to obtain the actual weight of the higher-level capacitor, namely, only the differential voltages within 2LSB are quantized for each time, so that the calibration time and dynamic power consumption are reduced, and the measurement accuracy is improved.

Description

Capacitor mismatch calibration circuit for SAR ADC and calibration method thereof

[ field of technology ]

The application relates to the technical field of analog-to-digital conversion, in particular to a capacitor mismatch calibration circuit for an SAR ADC and a calibration method thereof.

[ background Art ]

The analog-to-digital converter (SAR ADC) is a device for converting an analog signal into a digital signal, and has the advantages of simple structure, low power consumption and the like, so that the SAR ADC becomes a research hot spot in the industry in recent years, the performance of the SAR ADC is limited by various non-ideal factors, and particularly, the capacitor mismatch is most prominent, and is one of the main factors influencing the actual quantization precision of the SAR ADC, so that the calibration of the capacitor mismatch is very important. The existing capacitance mismatch calibration scheme can be roughly divided into LMS (least mean square algorithm) calibration, auxiliary capacitance calibration, SAR ADC calibration, histogram calibration and the like, wherein the LMS calibration needs to be subjected to a large amount of iterative computation, occupies a large amount of storage resources, and is more suitable for off-chip calibration; the auxiliary capacitance calibration occupies a larger area, parasitism is increased, and the accuracy is limited by the minimum capacitance of the auxiliary capacitance; mismatch errors of SAR ADC self calibration can be accumulated slowly, so that the precision of the SAR ADC self calibration is difficult to improve; histogram calibration requires a large number of computations, tens of thousands of convergence times.

In the related art, the capacitor mismatch can be measured by using a time domain comparator and a time-to-digital converter (TDC) to calibrate the SAR ADC, specifically, by controlling the oscillation frequency of an oscillator in the time domain comparator, the voltage difference signal is converted into a phase difference signal, and finally, the phase difference signal is quantized by the TDC based on the oscillator. The shortcomings of this capacitance mismatch calibration scheme are: for the high-order capacitor, the mismatch weight error is larger, the oscillation time required for measuring the mismatch of the low-order capacitor is shorter, but the oscillation time required for measuring the mismatch of the high-order capacitor can be tens or even thousands times of that required for measuring the mismatch of the low-order capacitor, the capacitor voltage difference is quite far from the theoretical voltage difference of 1LSB (least significant bit), and the smaller the capacitor capacitance value is, the larger the mismatch standard deviation is, the larger the mismatch weight of the high-order capacitor of the SAR ADC with higher precision is, so the calibration speed is quite slow, the dynamic power consumption is also increased, and the measurement precision is reduced due to nonlinearity.

Therefore, there is a need for improvements to existing calibration schemes for capacitance mismatch.

[ invention ]

The application provides a capacitor mismatch calibration circuit for an SAR ADC and a calibration method thereof, and aims to solve the problems of long time, high dynamic power consumption and low precision of capacitor mismatch calibration in the related technology.

In order to solve the above-mentioned technical problems in the related art, a first aspect of the present application provides a capacitor mismatch calibration circuit for a SAR ADC, which includes a first capacitor array, a second capacitor array, a main comparator, a time domain comparator, and a time-to-digital converter, where the first capacitor array and the second capacitor array include a plurality of capacitors connected in parallel, the number of capacitors between the first capacitor array and the second capacitor array is the same, upper plates of the plurality of capacitors in the first capacitor array are connected in parallel and then connected to a positive input end of the main comparator, upper plates of the plurality of capacitors in the second capacitor array are connected in parallel and then connected to a negative input end of the main comparator, and according to a direction away from the main comparator, the number of bits of the plurality of capacitors in the first capacitor array and the plurality of capacitors in the second capacitor array are sequentially increased, each two corresponding capacitors in the first capacitor array and the second capacitor array form a differential capacitor, and the number of bits of each differential capacitor is adapted to two capacitors of the first capacitor array, the upper plates of the plurality of capacitors in the first capacitor array are connected in parallel and the time domain comparator and the time-to the converter in the second capacitor array is connected in parallel respectively. Specifically, the calibration flow of the capacitance mismatch calibration circuit includes: the voltage of the upper polar plate and the lower polar plate of each capacitor is switched, so that the upper polar plate of the first potential difference capacitor generates a first pair of differential voltages of 1LSB, the first pair of differential voltages are quantized by a time domain comparator and a time-to-digital converter to obtain first voltage difference information of 1LSB, and the voltage switching of the upper polar plate and the lower polar plate of the capacitor comprises any one of common-mode voltage, reference high voltage and reference low voltage; the voltage of the upper polar plate and the voltage of the lower polar plate of each capacitor are switched, so that the upper polar plate of the first potential difference capacitor generates a second pair of differential voltages of 2LSB, the second pair of differential voltages are quantized by a time domain comparator and a time-to-digital converter to obtain second voltage difference information of 2LSB, and a linear function relation between the differential voltage generated by the upper polar plate of the first potential difference capacitor and the oscillation frequency of a first oscillator in the time-to-digital converter is obtained through the first voltage difference information and the second voltage difference information; switching the voltages of the upper and lower polar plates of each capacitor, outputting a corresponding comparison result by the main comparator according to a pair of differential voltages generated by the upper polar plates of the second differential capacitor, and enabling the upper polar plates of the second differential capacitor to generate a pair of differential voltages to be tested, which are smaller than 1LSB, by switching the voltages of the lower polar plates of the two first capacitors in the first capacitor array and the second capacitor array, and obtaining corresponding voltage difference information to be tested after the differential voltages to be tested are quantized by the time domain comparator and the time-to-digital converter; and reversely pushing out the actual weights of the two second capacitors in the first capacitor array and the second capacitor array according to the voltage difference information to be detected and the weights of the two first capacitors in the first capacitor array and the second capacitor array, and the like until the actual weights of the capacitors are obtained.

A second aspect of the embodiments of the present application provides a capacitance mismatch calibration method for a SAR ADC, which is applied to the capacitance mismatch calibration circuit mentioned in the first aspect of the embodiments of the present application, and includes: the method comprises the steps that voltages of an upper polar plate and a lower polar plate of each capacitor are switched, so that the upper polar plate of a first potential difference capacitor generates a first pair of differential voltages of 1LSB, the first pair of differential voltages are quantized through a time domain comparator and a time-to-digital converter to obtain first voltage difference information of 1LSB, and the voltage switching of the upper polar plate and the lower polar plate of the capacitor comprises any one of common-mode voltage, reference high voltage and reference low voltage; the voltage of the upper polar plate and the voltage of the lower polar plate of each capacitor are switched, so that the upper polar plate of the first potential difference capacitor generates a second pair of differential voltages of 2LSB, the second pair of differential voltages are quantized by a time domain comparator and a time-to-digital converter to obtain second voltage difference information of 2LSB, and a linear function relation between the differential voltage generated by the upper polar plate of the first potential difference capacitor and the oscillation times of a first oscillator in the time-to-digital converter is obtained through the first voltage difference information and the second voltage difference information; switching the voltages of the upper and lower polar plates of each capacitor, outputting a corresponding comparison result by the main comparator according to a pair of differential voltages generated by the upper polar plates of the second differential capacitor, and enabling the upper polar plates of the second differential capacitor to generate a pair of differential voltages to be tested, which are smaller than 1LSB, by switching the voltages of the lower polar plates of the two first capacitors in the first capacitor array and the second capacitor array, and obtaining corresponding voltage difference information to be tested after the differential voltages to be tested are quantized by the time domain comparator and the time-to-digital converter; and according to the voltage difference information to be detected and the weights of the two first-bit capacitors in the first capacitor array and the second capacitor array, reversely pushing out the actual weights of the two second-bit capacitors in the first capacitor array and the second capacitor array, and the like until the actual weights of the capacitors are obtained.

It can be understood that by implementing the above technical scheme, on the basis of combining the time-to-digital converter with the time-domain comparator in the traditional scheme, the control logic for self-calibration of the SAR ADC is added, that is, after the step of obtaining the first voltage difference information, the second voltage difference information and the linear function relationship between the differential voltage generated by the upper plate of the differential capacitor and the oscillation frequency of the first oscillator in the time-to-digital converter is added, the successive approximation conversion step of the SAR ADC is added, so that the differential voltage generated by the upper plate of the differential capacitor is always within the range of 2LSB, and then the quantization process of the time-domain comparator and the time-to-digital converter is performed to obtain the actual weights of the second capacitor and higher capacitor, that is, only the differential voltage within 2LSB is required to be quantized for each quantization, so that the calibration time and dynamic power consumption can be greatly reduced, and the measurement accuracy can be improved.

[ description of the drawings ]

In order to more clearly illustrate the technology of the related art or the technical solutions in the embodiments of the present application, the following description will briefly introduce the drawings that are required to be used in the description of the related technology or the embodiments of the present application, and it is apparent that the drawings in the following description are only some embodiments of the present application, but not all embodiments, and that other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a capacitance mismatch calibration circuit according to an embodiment of the present application;

fig. 2 is a flow chart of a capacitance mismatch calibration method according to an embodiment of the present application.

[ detailed description ] of the invention

For the purposes of making the objects, technical solutions and advantages of the present application more apparent and understandable, the present application will be clearly and completely described in the following description with reference to the embodiments of the present application and the corresponding drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be understood that the following embodiments of the present application are described only for explaining the present application, and are not intended to limit the present application, that is, all other embodiments obtained by persons of ordinary skill in the art without making any inventive effort based on the embodiments of the present application are within the scope of protection of the present application. Furthermore, the technical features referred to in the embodiments of the present application described below may be combined with each other as long as they do not constitute a conflict with each other.

In the related art, the capacitor mismatch can be measured by using a time domain comparator and a time-to-digital converter (TDC) to calibrate the SAR ADC, specifically, by controlling the oscillation frequency of an oscillator in the time domain comparator, the voltage difference signal is converted into a phase difference signal, and finally, the phase difference signal is quantized by the TDC based on the oscillator, which has the following drawbacks: for the high-order capacitor, the mismatch weight error is larger, the oscillation time required for measuring the mismatch of the low-order capacitor is shorter, but the oscillation time required for measuring the mismatch of the high-order capacitor can be tens or even thousands times of that required for measuring the mismatch of the low-order capacitor, the capacitor voltage difference is quite far from the theoretical voltage difference of 1LSB (least significant bit), and the smaller the capacitor capacitance value is, the larger the mismatch standard deviation is, the higher the mismatch weight of the high-order capacitor of the SAR ADC with higher precision is, the calibration speed is quite slow, the dynamic power consumption is also increased, and the measurement precision is also reduced due to nonlinearity, namely, the capacitor mismatch calibration scheme is difficult to be applied to the SAR ADC with higher precision. Therefore, in the embodiments described below, the present application provides a capacitor mismatch calibration circuit and a calibration method thereof for an SAR ADC, by which the calibration time can be effectively reduced, the dynamic power consumption can be reduced, and the measurement accuracy of capacitor mismatch can be improved when the capacitor mismatch calibration circuit and the calibration method thereof perform the calibration of capacitor mismatch.

Fig. 1 is a schematic diagram of a capacitance mismatch calibration circuit, in some embodiments, the capacitance mismatch calibration circuit includes a first capacitance array 110, a second capacitance array 120, a main comparator 130, a time domain comparator 140, and a time-to-digital converter 150, the first capacitance array 110 and the second capacitance array 120 respectively include a plurality of capacitors connected in parallel, the number of capacitors between the first capacitance array 110 and the second capacitance array 120 is the same, upper plates of the plurality of capacitors in the first capacitance array 110 are connected in parallel and then connected to a positive input end of the main comparator 130, upper plates of the plurality of capacitors in the second capacitance array 120 are connected in parallel and then connected to a negative input end of the main comparator 130, a comparison result output by an output end of the main comparator 130 is used for indicating capacitance mismatch information, upper plates of the plurality of capacitors in the first capacitance array 110 are connected in parallel and upper plates of the plurality of capacitors in the second capacitance array 120 are connected in parallel and then connected to the time domain comparator 140, and the time domain comparator 140 is connected to the time-to-digital converter 150. In addition, the number of bits of the plurality of capacitors in the first capacitor array 110 and the plurality of capacitors in the second capacitor array 120 sequentially increases in a direction away from the main comparator 130, and the plurality of capacitors included in the first capacitor array 110 and the second capacitor array 120 are each represented by C1 to Cn in an order of increasing the number of bits, where C1 represents a first bit capacitor, C2 represents a second bit capacitor, cn represents an nth bit capacitor, and n is a positive integer greater than 1. It should be further noted that, each two corresponding capacitors in the first capacitor array 110 and the second capacitor array 120 form a differential capacitor, and the number of bits of each differential capacitor is adapted to two capacitors forming the differential capacitor, that is, the first bit differential capacitor is formed by two first bit capacitors (C1) in the first capacitor array 110 and the second capacitor array 120, and the nth bit differential capacitor is formed by two nth bit capacitors (Cn) in the first capacitor array 110 and the second capacitor array 120.

Specifically, the calibration procedure of the capacitance mismatch calibration circuit can be substantially divided into four steps, namely: the first step, by switching the voltages of the upper and lower plates of each capacitor, the upper plate of the first potential difference capacitor generates a first pair of differential voltages of 1LSB, and the first pair of differential voltages is quantized by the time-domain comparator 140 and the time-to-digital converter 150 to obtain first voltage difference information of 1LSB, wherein the voltage switching of the upper and lower plates of the capacitor comprises any one of a common-mode voltage VCM, a reference high voltage VREF and a reference low voltage VGND; a second step of switching the voltages of the upper and lower plates of each capacitor to generate a second pair of differential voltages of 2LSB on the upper plate of the first differential capacitor, and obtaining second voltage difference information of 2LSB after the second pair of differential voltages are quantized by the time domain comparator 140 and the time-to-digital converter 150, wherein a linear function relationship between the differential voltage generated on the upper plate of the first differential capacitor and the oscillation frequency of the first oscillator in the time-to-digital converter 150 can be obtained through the first voltage difference information and the second voltage difference information; the third step, the voltages of the upper and lower plates of each capacitor are switched, and after the main comparator 130 outputs a corresponding comparison result according to a pair of differential voltages generated by the upper plates of the second differential capacitors, the upper plates of the second differential capacitors generate a pair of differential voltages to be tested smaller than 1LSB by switching the voltages of the lower plates of the two first capacitors in the first capacitor array 110 and the second capacitor array 120, and the differential voltages to be tested are quantized by the time domain comparator 140 and the time-to-digital converter 150 to obtain corresponding information of the voltage difference to be tested; and a fourth step of reversely pushing out the actual weights of the two second capacitors in the first capacitor array 110 and the second capacitor array 120 according to the voltage difference information to be detected and the weights of the two first capacitors in the first capacitor array 110 and the second capacitor array 120, and the like until the actual weights of the capacitors are obtained, and then performing normal operation of the SAR ADC. It should be noted that the weights of the two first capacitors in the first capacitor array 110 and the second capacitor array 120 are essentially their actual weights, which are predicted.

As can be seen from the above, the present application adds the control logic for self calibration of the SAR ADC based on the combination of the time-domain comparator 140 and the time-to-digital converter 150 in the conventional scheme, that is, after the step of obtaining the first voltage difference information, the second voltage difference information, and the linear function relationship between the differential voltage generated by the upper plate of the low-level differential capacitor and the oscillation frequency of the first oscillator in the time-to-digital converter 150, the successive approximation conversion step of the SAR ADC is added, so that the differential voltage generated by the upper plate of the differential capacitor is always within the range of 2LSB, and then the quantization process of the time-domain comparator 140 and the time-to-digital converter 150 is performed to obtain the actual weights of the second-level capacitor and the higher-level capacitor, that is, only the differential voltage within 2LSB needs to be quantized for each quantization, so that the calibration time and the dynamic power consumption can be greatly reduced, and the measurement accuracy can be improved.

As one embodiment, the process of generating the first pair of differential voltages specifically includes: after resetting the upper and lower plates of all capacitors to the common mode voltage VCM and opening the switch for connecting the upper plate of each capacitor to the common mode voltage VCM (i.e. the common mode switch hereinafter), the lower plate of the first capacitor in the first capacitor array 110 is switched to the reference high voltage VREF, and the lower plate of the first capacitor in the second capacitor array 120 is switched to the reference low voltage VGND, so that the upper plate of the first differential capacitor generates a first pair of differential voltages of 1 LSB. Further, the first oscillator in the time-to-digital converter 150 includes two in total, the time domain comparator 140 includes two counters and two second oscillators, and the process of obtaining the first voltage difference information specifically includes: the first pair of differential voltages is input into the time domain comparator 140, the first pair of differential voltages controls currents in the two second oscillators to be different in magnitude and enables the two second oscillators to oscillate, the two counters record oscillation times of the two second oscillators respectively, when the oscillation times of the two second oscillators respectively reach preset times, the time domain comparator 140 respectively outputs two first rising edge signals to arrive at the time domain comparator 150, a phase difference between the two first rising edge signals is positively related to the first pair of differential voltages, the two first rising edge signals enable the two first oscillators in the time domain comparator 150 to oscillate, when the oscillation times of the two first oscillators are identical, the corresponding oscillation times indicate first phase difference information, and the time domain comparator 150 outputs corresponding first voltage difference information based on the first phase difference information.

As one embodiment, the process of generating the second pair of differential voltages specifically includes: after the lower plate of the first capacitor in the first capacitor array 110 is switched to the reference low voltage VGND, the lower plate of the first capacitor in the second capacitor array 120 is switched to the reference high voltage VREF, the upper and lower plates of the other capacitors are reset to the common mode voltage VCM, and the switch for connecting the upper plate of each capacitor to the common mode voltage VCM (hereinafter referred to as the common mode switch) is turned off, the lower plate of the first capacitor in the first capacitor array 110 is switched to the reference high voltage VREF, and the lower plate of the first capacitor in the second capacitor array 120 is switched to the reference low voltage VGND, so that the upper plate of the first differential capacitor generates a second pair of differential voltages of 2 LSB. Further, the process of obtaining the second voltage difference information specifically includes: the second pair of differential voltages is input into the time domain comparator 140, the currents of the two second oscillators in the second pair of differential voltage control time domain comparators 140 are different, the two second oscillators are made to oscillate, the two counters in the time domain comparator 140 record the oscillating times of the two second oscillators respectively, when the oscillating times of the two second oscillators reach preset times respectively, the time domain comparator 140 outputs two second rising edge signals to the time-to-digital converter 150 respectively, the phase difference between the two second rising edge signals is positive to the second pair of differential voltages, the two second rising edge signals enable the two first oscillators in the time-to-digital converter 150 to oscillate, when the oscillating times of the two first oscillators are identical, the corresponding oscillating times indicate second phase difference information, and the time-to-digital converter 150 outputs corresponding second voltage difference information based on the second phase difference information.

As one embodiment, the process of generating the differential voltage to be measured specifically includes: after resetting the upper and lower plates of all capacitors to the common mode voltage VCM and opening the switch for connecting the upper plate of each capacitor to the common mode voltage VCM (i.e. the common mode switch hereinafter), the lower plate of the second capacitor in the first capacitor array 110 is switched to the reference high voltage VREF, and the lower plate of the second capacitor in the second capacitor array 120 is switched to the reference low voltage VGND, and after the main comparator 130 outputs a corresponding comparison result according to a pair of differential voltages generated by the upper plates of the second differential capacitor, the voltages of the lower plates of the two first capacitors in the first capacitor array 110 and the second capacitor array 120 are switched (for example, the lower plate of the second capacitor in the first capacitor array 110 is switched to the reference low voltage VGND, and the lower plate of the second capacitor in the second capacitor array 120 is switched to the reference high voltage VREF), so that the upper plate of the second differential capacitor generates a pair of differential voltages to be measured which is smaller than 1 LSB. Further, the process of obtaining the voltage difference information to be measured specifically includes: the differential voltage to be measured is input into the time domain comparator 140, the differential voltage to be measured controls the currents of the two second oscillators in the time domain comparator 140 to be different, the two second oscillators oscillate, the two counters in the time domain comparator 140 record the oscillation times of the two second oscillators respectively, when the oscillation times of the two second oscillators respectively reach the preset times, the time domain comparator 140 outputs two rising edge signals to the time-to-time converter 150 respectively, the phase difference between the two rising edge signals to be measured is positively related to the differential voltage to be measured, the two rising edge signals to be measured enable the two first oscillators in the time-to-time converter 150 to oscillate, when the oscillation times of the two first oscillators are identical, the corresponding oscillation times indicate the phase difference information to be measured, and the time-to-time converter 150 outputs the corresponding voltage difference information to be measured based on the phase difference information to be measured.

As an embodiment, referring to fig. 1, a bottom plate of each capacitor is connected to a single-pole four-throw switch, in the first capacitor array 110 and the second capacitor array 120, a plurality of single-pole four-throw switches are denoted by K1 to Kn, a first port of all the single-pole four-throw switches in the first capacitor array 110 is connected in parallel to a reference high voltage VREF, a second port is connected in parallel to a reference low voltage VGND, a third port is connected in parallel to a common mode voltage VCM, and a fourth port is connected in parallel to a first input voltage Vin; all the single-pole four-throw switches in the second capacitor array 120 are connected in parallel with a first port and then connected with a reference high voltage VREF, a second port and then connected with a reference low voltage VGND, a third port and then connected with a common mode voltage VCM, and a fourth port and then connected with a second input voltage Vip; it can be appreciated that in the actual calibration process, the voltages of the upper and lower plates of each capacitor can be switched between the reference high voltage VREF, the reference low voltage VGND and the common mode voltage VCM by controlling each single pole four throw switch, wherein the reference low voltage VGND can be obtained by grounding. In addition, it should be noted that the first input voltage Vin and the second input voltage Vip are a pair of differential signals that need to be quantized when the SAR ADC is operating normally, and the first input voltage Vin and the second input voltage Vip do not need to be connected in the process of capacitance mismatch calibration.

Further, the upper plate of each capacitor in the first capacitor array 110 and the positive input end of the main comparator 130 are connected to the common mode voltage VCM through the first common mode switch P1, and the upper plate of each capacitor in the second capacitor array 120 and the negative input end of the main comparator 130 are connected to the common mode voltage VCM through the second common mode switch P2; it will be appreciated that during the actual calibration process, the voltages at the upper plate of each capacitor and the positive and negative inputs of the main comparator 130 may be switched to the common mode voltage VCM or float by controlling the first and second common mode switches P1 and P2, and for a single capacitor, when the upper plate is connected to the common mode voltage VCM and the lower plate is grounded (i.e., referenced to the low voltage VGND), the voltage difference across it is reset to the common mode voltage VCM.

As an embodiment, referring to fig. 1, the capacitance mismatch calibration circuit may further include a successive approximation register 160 in addition to the above-listed structure, where the successive approximation register 160 is electrically connected to the output end of the main comparator 130, and in an actual calibration process, the successive approximation register 160 may output a corresponding digital signal according to the output result of the main comparator 130 and control the switching of the single-pole four-throw switch connected to the lower plate of each capacitor, and since the output result of the main comparator 130 refers to the capacitance mismatch information, the digital signal output by the successive approximation register 160 also indicates the capacitance mismatch information, which is merely different in signal form.

The above embodiments are only preferred implementations of the present application and are not the only limitations on the content of capacitance mismatch calibration circuits; in this regard, those skilled in the art can flexibly set according to the actual application scenario on the basis of the above embodiments. It should be noted that, the time domain comparator 140 of the present application is only used to quantify the voltage difference of the upper plate of the capacitor, the comparator (i.e. the main comparator 130) of the SAR ADC operating normally uses a high-speed dynamic comparator so as to increase the speed of the SAR ADC, but the time domain comparator 140 may also be used as a comparator of the SAR ADC operating normally, and the time domain comparator 140 has the advantages that the accuracy thereof may vary with the magnitude of the input voltage difference, and since it is composed of an inverter chain, it is very suitable for the application of the low-voltage domain, and the time domain comparator 140 has the disadvantage that the speed thereof is relatively slow, so the time domain comparator 140 used as a comparator of the SAR ADC operating normally may be applied in the application of low voltage, low power consumption, and medium low speed. It should be further noted that, the application measures the voltage difference information of 1LSB and 2LSB, and may actually only measure the voltage difference information of 1LSB and then generate the function relation passing through the origin, but this method actually increases the error, because the functions measured by these two methods are not necessarily consistent due to the process error, and the functions made by measuring the voltage difference information of 1LSB and 2LSB are more accurate.

In addition, the above-mentioned capacitance mismatch calibration circuit corresponds to a capacitance mismatch calibration method, and fig. 2 is a flow chart of the capacitance mismatch calibration method, and the capacitance mismatch calibration method of the present application includes steps 201 to 204 (S201 to S204, for short), that is: s201, by switching the voltages of the upper and lower polar plates of each capacitor, the upper polar plate of the first potential difference capacitor generates a first pair of differential voltages of 1LSB, and the first pair of differential voltages are quantized by the time domain comparator 140 and the time-to-digital converter 150 to obtain first voltage difference information of 1 LSB; s202, by switching the voltages of the upper and lower electrode plates of each capacitor, the upper electrode plate of the first potential difference capacitor generates a second pair of differential voltages of 2LSB, the second pair of differential voltages is quantized by the time domain comparator 140 and the time-to-digital converter 150 to obtain second voltage difference information of 2LSB, and a linear function relation between the differential voltage generated by the upper electrode plate of the first potential difference capacitor and the oscillation times of the first oscillator in the time-to-digital converter 150 is obtained through the first voltage difference information and the second voltage difference information; s203, switching the voltages of the upper and lower electrode plates of each capacitor, and after the main comparator 130 outputs a corresponding comparison result according to a pair of differential voltages generated by the upper electrode plates of the second differential capacitors, by switching the voltages of the lower electrode plates of the two first capacitors in the first capacitor array 110 and the second capacitor array 120, the upper electrode plates of the second differential capacitors generate a pair of differential voltages to be tested smaller than 1LSB, and the differential voltages to be tested are quantized by the time domain comparator 140 and the time-to-digital converter 150 to obtain corresponding voltage difference information to be tested; s204, according to the voltage difference information to be measured and the weights of the two first-bit capacitors in the first capacitor array 110 and the second capacitor array 120, the actual weights of the two second-bit capacitors in the first capacitor array 110 and the second capacitor array 120 are reversely deduced, and so on until the actual weights of the capacitors are obtained. It should be noted that, for the inexhaustibility in the description of the capacitance mismatch calibration method, reference should be made to the foregoing description of the capacitance mismatch calibration circuit.

It can be understood that in the conventional scheme, the voltage change of the lower electrode plate of all low-order capacitors is preset, the original comparator is not used in the calibration stage, the voltage difference of the upper electrode plate of the capacitor is theoretically 1LSB, but due to process mismatch, the voltage difference of the upper electrode plate of the capacitor can reach tens of LSBs or higher, the time spent for measuring the voltage difference is longer, the dynamic power consumption can be increased by tens of times or higher, and the measured voltage difference is far larger than the originally acquired voltage difference, so that the measurement deviation is increased and the accuracy is reduced. Through the implementation of the above embodiment of the present application, the lower plate of the capacitor to be tested is firstly switched from the common mode level to the reference high voltage VREF and the reference low voltage VGND respectively, then the polarity of the upper plate voltage is firstly judged by the comparator (i.e. the main comparator 130) required by the normal operation of the SAR ADC before the time domain comparator 140 and the time-to-digital converter 150 operate, the output result is controlled by the SAR logic circuit to switch the lower plate switch (i.e. the single-pole four-throw switch) of the capacitor with one bit smaller, then the judgment result of the comparator is used to control the lower plate of the capacitor with one bit smaller, the process is repeated until reaching the LSB capacitor, in the process, the upper plate voltage of the capacitor array approaches more and more to 1LSB voltage, finally the result that the voltage difference of the upper plate is less than 1LSB is reached, the time required by the judgment time of the main comparator 130 is far less than the time required by the time domain comparator 140 and the time-to-digital converter 150 to quantize the large voltage difference, and then the time domain comparator 140 and the time-to-digital converter 150 measure the small difference voltage is required by measuring the time-to reduce the small difference voltage, and the required time is greatly reduced, and the dynamic measurement accuracy is greatly improved.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two; wherein the software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the process or function described herein may be implemented in whole or in part in a computer program product comprising one or more computer instructions that when loaded and executed on a computer, cause the process or function to be described in whole or in part, as a general purpose computer, special purpose computer, computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., such as a cable, optical fiber, digital subscriber line, etc.) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices such as servers, data centers, etc. that can be integrated by one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk), etc.

It should be noted that, several embodiments shown in the foregoing description of the present application are described in a progressive manner, and each embodiment focuses on the difference from other embodiments, where the same or similar parts between the embodiments refer to each other; in addition, for the method embodiment, similar to the product embodiment, the two descriptions have the defects mutually referring to each other. It should also be noted that in the text description of the present application, relational terms such as first and second are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Further, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus; moreover, without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

Furthermore, by implementing a number of embodiments of the present application, as illustrated above, one skilled in the art can make or use the present application. Various modifications to the embodiments of the present application, as described above, will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments not shown without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown above, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The capacitor mismatch calibration circuit for the SAR ADC is characterized by comprising a first capacitor array, a second capacitor array, a main comparator, a time domain comparator and a time-to-digital converter, wherein the first capacitor array and the second capacitor array respectively comprise a plurality of capacitors connected in parallel, the number of the capacitors between the first capacitor array and the second capacitor array is the same, upper polar plates of the capacitors in the first capacitor array are connected in parallel and then are connected with a positive input end of the main comparator, upper polar plates of the capacitors in the second capacitor array are connected in parallel and then are connected with a negative input end of the main comparator, the capacitors in the first capacitor array and the capacitors in the second capacitor array are sequentially increased according to the direction away from the main comparator, the number of bits of each corresponding capacitor in the first capacitor array and the second capacitor array respectively form a differential capacitor, and the number of bits of each differential capacitor is connected with the capacitors in parallel and then are connected with the capacitors in the first capacitor array and the second capacitor array; the calibration flow of the capacitance mismatch calibration circuit comprises the following steps:

The upper polar plate of the first potential difference capacitor generates a first pair of differential voltages of 1LSB by switching the voltages of the upper polar plate and the lower polar plate of each capacitor, and the first pair of differential voltages are quantized by the time domain comparator and the time-to-digital converter to obtain first voltage difference information of 1 LSB; the voltage switching of the upper polar plate and the lower polar plate of the capacitor comprises any one of common-mode voltage, reference high voltage and reference low voltage;

the voltages of the upper polar plate and the lower polar plate of each capacitor are switched, so that the upper polar plate of the first potential difference capacitor generates a second pair of differential voltages of 2LSB, and the second pair of differential voltages are quantized by the time domain comparator and the time-to-digital converter to obtain second voltage difference information of 2 LSB; obtaining a linear function relation between a differential voltage generated by an upper polar plate of a first potential difference capacitor and the oscillation times of a first oscillator in the time-to-digital converter through the first voltage difference information and the second voltage difference information;

switching the voltages of the upper and lower polar plates of each capacitor, outputting a corresponding comparison result by the main comparator according to a pair of differential voltages generated by the upper polar plates of the second bit differential capacitor, and enabling the upper polar plates of the second bit differential capacitor to generate a pair of differential voltages to be tested, which are smaller than 1LSB, by switching the voltages of the lower polar plates of the two first bit capacitors in the first capacitor array and the second capacitor array, wherein the differential voltages to be tested are quantized by the time domain comparator and the time-to-digital converter to obtain corresponding voltage difference information to be tested;

And reversely pushing out the actual weights of the two second capacitors in the first capacitor array and the second capacitor array according to the voltage difference information to be detected and the weights of the two first capacitors in the first capacitor array and the second capacitor array, and the like until the actual weights of the capacitors are obtained.

2. The capacitive mismatch calibration circuit according to claim 1, wherein the process of generating the first pair of differential voltages comprises: after resetting all the upper and lower electrode plates of the capacitors to a common mode voltage, disconnecting a switch for enabling the upper electrode plate of each capacitor to be connected to the common mode voltage, switching the lower electrode plate of the first capacitor in the first capacitor array to a reference high voltage, and switching the lower electrode plate of the first capacitor in the second capacitor array to a reference low voltage, so that the upper electrode plate of the first differential capacitor generates a first pair of differential voltages of 1 LSB.

3. The capacitance mismatch calibration circuit according to claim 2, wherein the first oscillator in the time-to-digital converter comprises two and the time domain comparator comprises two counters and two second oscillators; the process of obtaining the first voltage difference information specifically includes: the first pair of differential voltages are input into the time domain comparator, the first pair of differential voltages control currents in the two second oscillators to be different in size, the two second oscillators are made to oscillate, the two counters record oscillation times of the two second oscillators respectively, when the oscillation times of the two second oscillators respectively reach preset times, the time domain comparator respectively outputs two first rising edge signals to the time-to-time converter, the phase difference between the two first rising edge signals is positive relative to the first pair of differential voltages, the two first rising edge signals enable the two first oscillators in the time-to-time converter to oscillate, when the oscillation times of the two first oscillators are identical, the corresponding oscillation times indicate first phase difference information, and the time-to-time converter outputs corresponding first phase difference information based on the first phase difference information.

4. The capacitive mismatch calibration circuit according to claim 1, wherein the process of generating the second pair of differential voltages comprises: and switching the lower electrode plate of the first capacitor in the first capacitor array to a reference low voltage, switching the lower electrode plate of the first capacitor in the second capacitor array to a reference high voltage, resetting the upper electrode plate and the lower electrode plate of the other capacitors to a common mode voltage, switching off a switch for enabling the upper electrode plate of each capacitor to be connected with the common mode voltage, switching the lower electrode plate of the first capacitor in the first capacitor array to the reference high voltage, and switching the lower electrode plate of the first capacitor in the second capacitor array to the reference low voltage, so that the upper electrode plate of the first capacitor generates a second pair of differential voltages of 2 LSB.

5. The capacitance mismatch calibration circuit according to claim 4, wherein the first oscillator in the time-to-digital converter comprises two and the time domain comparator comprises two counters and two second oscillators; the process of obtaining the second voltage difference information specifically includes: the second pair of differential voltages is input into the time domain comparator, the second pair of differential voltages controls currents in the two second oscillators to be different in size, the two second oscillators are made to oscillate, the two counters record oscillation times of the two second oscillators respectively, when the oscillation times of the two second oscillators respectively reach preset times, the time domain comparator respectively outputs two second rising edge signals to the time-to-digital converter, the phase difference between the two second rising edge signals is positive relative to the second pair of differential voltages, the two second rising edge signals enable the two first oscillators in the time-to-digital converter to oscillate, when the oscillation times of the two first oscillators are identical, the corresponding oscillation times indicate second phase difference information, and the time-to-digital converter outputs corresponding second voltage difference information based on the second phase difference information.

6. The capacitive mismatch calibration circuit according to claim 1, wherein the process of generating the differential voltage to be measured specifically comprises: after all the upper and lower electrode plates of the capacitors are reset to the common mode voltage, a switch for enabling the upper electrode plate of each capacitor to be connected to the common mode voltage is disconnected, then the lower electrode plate of the second capacitor in the first capacitor array is switched to the reference high voltage, the lower electrode plate of the second capacitor in the second capacitor array is switched to the reference low voltage, and after the main comparator outputs a corresponding comparison result according to a pair of differential voltages generated by the upper electrode plates of the second differential capacitors, the voltages of the lower electrode plates of the two first capacitors in the first capacitor array and the second capacitor array are switched, so that the upper electrode plates of the second differential capacitors generate a pair of differential voltages to be tested, which are smaller than 1 LSB.

7. The capacitance mismatch calibration circuit according to claim 6, wherein the first oscillator in the time-to-digital converter comprises two and the time-domain comparator comprises two counters and two second oscillators; the process for obtaining the voltage difference information to be detected specifically comprises the following steps: the differential voltage to be measured is input into the time domain comparator, the differential voltage to be measured controls the currents in the two second oscillators to be different in size, the two second oscillators are made to oscillate, the two counters are used for respectively recording the oscillation times of the two second oscillators, when the oscillation times of the two second oscillators respectively reach preset times, the time domain comparator is used for respectively outputting two rising edge signals to be measured to the time-to-digital converter, the phase difference between the two rising edge signals to be measured is positive to the differential voltage to be measured, the two rising edge signals to be measured enable the two first oscillators in the time-to-digital converter to oscillate, when the oscillation times of the two first oscillators are identical, the corresponding oscillation times indicate phase difference information to be measured, and the time-to-digital converter is used for outputting corresponding voltage difference information to be measured based on the phase difference information to be measured.

8. The capacitance mismatch calibration circuit according to claim 1, wherein a bottom plate of each of the capacitors is connected to a single-pole four-throw switch, a first port of all of the single-pole four-throw switches in the first capacitor array is connected in parallel to a reference high voltage, a second port is connected in parallel to a reference low voltage, a third port is connected in parallel to a common mode voltage, a fourth port is connected in parallel to a first input voltage, a first port of all of the single-pole four-throw switches in the second capacitor array is connected in parallel to a reference high voltage, a second port is connected in parallel to a reference low voltage, a third port is connected in parallel to a common mode voltage, and a fourth port is connected in parallel to a second input voltage; the upper polar plate of each capacitor in the first capacitor array and the positive input end of the main comparator are connected with a common mode voltage through a first common mode change-over switch, and the upper polar plate of each capacitor in the second capacitor array and the negative input end of the main comparator are connected with the common mode voltage through a second common mode change-over switch; the first input voltage and the second input voltage are a pair of differential signals which are required to be quantized when the SAR ADC works normally, and the first input voltage and the second input voltage do not need to be connected in the process of capacitance mismatch calibration.

9. The capacitance mismatch calibration circuit according to claim 8, further comprising a successive approximation register, an output of the main comparator being connected to the successive approximation register, the successive approximation register being configured to output a corresponding digital signal according to an output of the main comparator and to control switching of the single-pole, four-throw switch connected to a lower plate of each of the capacitors; wherein the output of the primary comparator indicates capacitance mismatch information.

10. A capacitance mismatch calibration method for a SAR ADC, applied to the capacitance mismatch calibration circuit of any one of claims 1 to 9, comprising:

the upper polar plate of the first potential difference capacitor generates a first pair of differential voltages of 1LSB by switching the voltages of the upper polar plate and the lower polar plate of each capacitor, and the first pair of differential voltages are quantized by the time domain comparator and the time-to-digital converter to obtain first voltage difference information of 1 LSB; the voltage switching of the upper polar plate and the lower polar plate of the capacitor comprises any one of common-mode voltage, reference high voltage and reference low voltage;

the voltages of the upper polar plate and the lower polar plate of each capacitor are switched, so that the upper polar plate of the first potential difference capacitor generates a second pair of differential voltages of 2LSB, and the second pair of differential voltages are quantized by the time domain comparator and the time-to-digital converter to obtain second voltage difference information of 2 LSB; obtaining a linear function relation between a differential voltage generated by an upper polar plate of a first potential difference capacitor and the oscillation times of a first oscillator in the time-to-digital converter through the first voltage difference information and the second voltage difference information;

Switching the voltages of the upper and lower polar plates of each capacitor, outputting a corresponding comparison result by the main comparator according to a pair of differential voltages generated by the upper polar plates of the second bit differential capacitor, and enabling the upper polar plates of the second bit differential capacitor to generate a pair of differential voltages to be tested, which are smaller than 1LSB, by switching the voltages of the lower polar plates of the two first bit capacitors in the first capacitor array and the second capacitor array, wherein the differential voltages to be tested are quantized by the time domain comparator and the time-to-digital converter to obtain corresponding voltage difference information to be tested;

and reversely pushing out the actual weights of the two second capacitors in the first capacitor array and the second capacitor array according to the voltage difference information to be detected and the weights of the two first capacitors in the first capacitor array and the second capacitor array, and the like until the actual weights of the capacitors are obtained.