CN112366274B - N-type semiconductor intercalation pentacene organic field effect transistor and application - Google Patents

N-type semiconductor intercalation pentacene organic field effect transistor and application Download PDF

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CN112366274B
CN112366274B CN202011153410.1A CN202011153410A CN112366274B CN 112366274 B CN112366274 B CN 112366274B CN 202011153410 A CN202011153410 A CN 202011153410A CN 112366274 B CN112366274 B CN 112366274B
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pentacene
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康利民
王一如
殷江
夏奕东
刘治国
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Nanjing University
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/466—Lateral bottom-gate IGFETs comprising only a single gate
    • H—ELECTRICITY
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    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
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    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/468—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics
    • H10K10/471—Insulated gate field-effect transistors [IGFETs] characterised by the gate dielectrics the gate dielectric comprising only organic materials
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    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/60—Organic compounds having low molecular weight
    • H10K85/615—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene
    • H10K85/623—Polycyclic condensed aromatic hydrocarbons, e.g. anthracene containing five rings, e.g. pentacene
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Abstract

In the organic field effect transistor device with the structure of gate electrode/insulating layer/polymer dielectric film/pentacene/source (drain) electrode, an n-type semiconductor film intercalation is arranged between the insulating layer and the polymer dielectric film; the thickness of the n-type semiconductor intercalation is 1-200nm; the hole barrier height at the interface between pentacene and polymer medium is reduced by induced electrons at the interface in the n-type semiconductor intercalation, so that the programming/erasing working voltage of the pentacene organic semiconductor transistor is effectively reduced; the hole barrier height at the interface of pentacene and polymer medium is regulated to a reasonable range by regulating the number of n-type carriers in the n-type semiconductor intercalation, so that the pentacene organic field effect transistor device has lower working voltage, faster programming/erasing speed, good programming/erasing reliability and data holding capacity.

Description

N-type semiconductor intercalation pentacene organic field effect transistor and application
Technical Field
The invention belongs to the technical field of organic semiconductor storage, and particularly relates to a method for improving the working performance of a pentacene organic field effect transistor by utilizing n-type semiconductor intercalation and application thereof.
Background
Non-volatile electronic devices based on organic field effect transistors have gained much attention over the past two decades [ 1,2 ] due to their application prospects in the fields of radio frequency identification tags to flexibility and large area displays. In order to facilitate practical application of organic field effect devices, much effort has been spent on research into charge trapping materials such as p-type channel materials, n-type channel materials, and polymers. As one of the most potential p-type channel materials, pentacene (pentacene), a planar molecular structure with 5 benzene rings, has been widely used in the research of organic semiconductor field effect devices. Studies have shown that pentacene organic field effect transistors with Polystyrene (PS), poly (2-vinyl naphthalene) (PVN), poly-alpha-methyl styrene (P alpha MS) and the like as charge trapping media show a large storage window [ 3 ] in the transfer characteristic curves at higher operating voltages. In pentacene organic field effect transistor devices using pαms as the charge storage medium, baeg et al performed a program operation on the device using a pulse voltage of 200V/1 μs and an erase operation on the device using a pulse of-100V/1 μs [ 1 ]. In pentacene organic field effect devices with styrene-poly 4-vinylpyridine block copolymers (PS-b-P4 VP) as the charge-trapping medium, the program operation was performed by Leong et al using a pulse voltage of-30V/1 s and the erase operation was performed using a pulse of 100V/30s [ 4 ]. The development of programming/erasing operations on pentacene organic field effect devices with pulse voltages having such high pulse amplitudes or such long pulse widths does not meet industry standards for modern electronic device applications. Thus, pentacene organic field effect transistor devices using polymer thin films as charge trapping media have not been practically used so far.
Various basic studies have been conducted against pentacene organic field effect transistor devices using polymer thin films as charge trapping media. Theoretical and experimental results [ 5,6 ] both indicate that there are positively charged defects in the pentacene film near the interface at the pentacene/polymer interface that are related to external environmental factors (e.g., hydrogen and oxygen, etc.), the positively charged bulk density is as high as 4 x 10 18 cm -3 【7】 A. The invention relates to a method for producing a fibre-reinforced plastic composite The positively charged defect layer is about 1.5nm thick and the thin layer has no semiconductor properties already due to defect formation. The positive charge of the thin layer forms an electric field which points to the p-type semiconductor pentacene film and plays a role in blocking the migration of holes (holes) in the pentacene film into the polymer film, the positively charged defect layer plays a role of a positive charge barrier, and the existence of the positive charge barrier leads to high working voltage of the pentacene organic field effect memory device taking the polymer film as a charge trapping medium.
The invention relates to a method for improving the working performance of pentacene organic field effect transistor, which comprises the steps of arranging an n-type semiconductor film transition layer between a polymer medium and pentacene in an organic field effect transistor device with a structure of a gate electrode/an insulating layer/a polymer medium film/pentacene/a source electrode and a drain electrode; the thickness of the n-type semiconductor transition layer is 1-100nm; the n-type semiconductor film is a crystalline film, a semi-crystalline film, or an amorphous film. The hole barrier height at the interface of pentacene and the charge trapping medium is reduced by induced electrons at the interface in the n-type semiconductor transition layer, so that the programming/erasing working voltage of the pentacene organic semiconductor transistor is effectively reduced; positive space charge areas formed by ionized donors in the n-type semiconductor transition layer prevent positive charges (holes) captured in the polymer medium film from escaping into the pentacene film, so that the programming/erasing reliability and the data retention capability of the pentacene organic semiconductor transistor device are improved, and the working performance of the pentacene organic field effect transistor is improved.
Reference is made to:
1.Baeg,K.,-J,Noh,Y.Y.,Ghim,J.,Kang,S.J.,Lee,H.Kim,D.Y.,Organic Non-volatile Memory Based on Pentancene Field-Effect Transistors Using a Polymeric Gate Electret.,Adv.Mater.18,3179-3183(2006).
2.Dimitrakopoulos,C.D.&Malenfant,P.R.Adv.Mater.14,99-117(2002).
3.Baeg,K.,J.,Noh Y.Y.,Ghim J.,Lim B.,Kim D.Y.,Polarity Effects of Polymer Gate Electrets on Non-Volatile Organic Field-Effect Transistor Memory,Adv.Funct.Mater.18,3678-3685(2008).
4.Leong,W.L.,Mathews,N.,Mhaisalkar,S.,Lam Y.M.,Chen,T.,Lee,S.,Micellar poly(styrene-b-4-vinypyridine)-nanoparticle hybrid system for non-volatile organic transistor memory,J.Mater.Chem.19,7354-7361(2009).
5.Knipp,D,Street,R.A.,Volkel,A.and Ho,J.,Pentacene thin film transistors on inorganic dielectrics:Morphology,structural properties,and electronic transport,J.Appl.Phys.93,347-355(2003).
6.Northrup J.E.,Chabinyc M.L.,Gap states in organic semiconductors:Hydrogen-and Oxygen-induced states in pentacene,Phys.Rev.B 68,041202(R):1-4(2003).
7.Kalb,W.L.,Mattenberger,K.and Batlogg,B.,Oxygen-related traps in pentacene thin films:Energetic position and implications for transistor performance,Phys.Rev.B,78,035334:1-11(2008).
disclosure of Invention
The present invention is directed to a method for improving the operation performance of pentacene organic field effect transistor by using n-type semiconductor intercalation, which is used for promoting the practical application. In the chinese patent of CN201911336850.8, a method for improving the performance of pentacene organic field effect transistor memory devices by introducing an n-type semiconductor transition layer at the pentacene/polymer interface is proposed. On the basis of the method, a method for improving the performance of the pentacene organic field effect transistor memory device through the indirect intercalation of the n-type semiconductor is further provided.
The technical scheme of the invention is that the method for improving the performance of the pentacene organic field effect transistor memory device by introducing n-type semiconductor intercalation at the interface of a polymer/insulating layer comprises the following steps: gate electrode/insulating layer/polymer dielectric film/pentacene/source (drain) electrode; in the invention, an n-type semiconductor film intercalation layer is added between an insulating layer and a polymer dielectric film; the grid electrode 1 is a conductor with resistivity less than 0.005 omega-cm; the insulating layer dielectric film 2 is an insulator; the n-type semiconductor film 3 is an n-type inorganic semiconductor film or an n-type organic semiconductor film; the polymer medium film 4 is a charge trapping medium, and the polymer medium is preferably Polystyrene (PS), poly (2-vinyl naphthalene) (PVN), poly alpha-methyl styrene (Palpha MS) or the like, but is not limited to the above materials, and the thickness is 1-100nm; pentacene 5 has a thickness of 1-100nm; the source-drain electrode 6 has a thickness of 50-200nm.
The pentacene organic field effect transistor structure is a bottom gate structure, and is a gate electrode, an insulating layer, an n-type semiconductor film, a polymer dielectric film, a pentacene/a source (drain) electrode from bottom to top; or a top gate structure, which is a source (drain) electrode/pentacene/polymer dielectric film/n-type semiconductor film/insulating layer/gate electrode from bottom to top; the two structures are essentially indistinguishable and therefore both structures are within the scope of the present invention.
The n-type semiconductor film is an n-type inorganic semiconductor film including zinc selenide (ZnSe), zinc sulfide (ZnS), zinc oxide (ZnO), indium Gallium Zinc Oxide (IGZO), or oxygen-deficient oxide film, or oxygen-deficient composite oxide film such as TiO 1-δ ,ZrHfO 2-δ Etc.; the preparation method comprises magnetron sputtering, thermal evaporation or electron beam evaporation, and the thickness of the film is 1-200nm, and the film is crystalline film or amorphous film.
The N-type semiconductor thin film may also be an N-type organic semiconductor thin film, and is specifically classified into an N-type small molecule thin film and an N-type polymer thin film, such as N-N "-di-3-N-pentylidene-3, 4,9, 10-perylene diimide (PTCDI-C13), N-N" -di-N-tridecyl-3, 4,9, 10-perylene diimide (EP-PDI), N-N "-diphenyl-1, 4,5, 8-Nediimide (NDI), etc., but is not limited to the above-mentioned organic thin films; the n-type semiconductor film is a crystalline film, a semi-crystalline film, or an amorphous film. The n-type organic semiconductor thin film preparation method includes a solution method such as spin-coating, sol-gel, spray-coating, screen-printing, ink-jet printing, thermal evaporation, or other similar physical and chemical thin film preparation methods; the thickness of the material is 1-100nm.
The n-type semiconductor film can also be two n-type semiconductor composite structure films; an n-type inorganic semiconductor film is prepared on the surface of the n-type organic semiconductor film, or an n-type polymer film is prepared on the surface of the n-type organic semiconductor film; the thickness of the n-type organic semiconductor film in the composite structure film is 0.5-60nm, the thickness of the n-type inorganic semiconductor film is 0.5-60nm, but the thickness of the composite structure film is 1-100nm.
The pentacene can be prepared by solution method such as spin-coating, sol-gel, spray coating, screen printing, ink-jet printing, thermal evaporation, or other similar physical and chemical film preparation methods; the thickness range is 1-50nm.
The polymer medium film has the function of capturing charges, and the polymer medium is preferably PS, PVN or any other organic film with charge capturing capability, but is not limited to the organic film, and the thickness of the organic film ranges from 1nm to 100nm.
The dielectric film of the insulating layer may be an insulator such as silicon dioxide, aluminum oxide, or the like, which functions to block charges trapped by the polymer from escaping to the gate electrode.
The gate electrode may be a metal, conductive nitride or conductive oxide material; the gate electrode of the bottom gate type field effect transistor can also be made of semiconductor materials such as n-type heavily doped high-conductivity silicon or p-type heavily doped high-conductivity silicon; the gate electrode of the bottom gate field effect transistor may also be a flexible, conductively coated substrate.
The pentacene organic field effect transistor memory device obtained by the method has the structure that: from bottom to top, respectively, a gate electrode/an insulating layer/an n-type semiconductor thin film intercalation/a polymer dielectric thin film/a pentacene/a source (drain) electrode; the structure of the organic field effect transistor device is top gate type, and the structure is a source (drain) electrode/pentacene/polymer dielectric film/n-type semiconductor film intercalation/insulating layer/gate electrode from bottom to top respectively.
In pentacene films at the pentacene/polymer medium interface, there are positively charged defects at the pentacene grain boundaries near the interface that are related to external environmental factors (such as hydrogen, or oxygen, or moisture, etc.), the bulk density of the positive charges can be as high as 4 x 10 18 /cm 3 . The positively charged defect layer has a thickness of about 1.5nm, which defect layer already has no semiconductor properties due to the formation of defects. The electric field direction formed by positive charges points to the p-type semiconductor pentacene film, plays a role in blocking the migration of holes (holes) in the pentacene film into the polymer film, and the positively charged defect layer plays a role of positive charge barrier. It is the presence of this positive charge barrier that results in a high operating voltage for pentacene organic field effect devices with polymer films as charge trapping media.
After the n-type semiconductor intercalation is introduced, induced charges are generated in the n-type semiconductor film due to the electrostatic action of the pentacene with positive interface layer near the interface, electrons in the n-type semiconductor film are attracted to the film interface near the polymer medium, and thus high-density electrons are accumulated; while the ionized donor inside the n-type semiconductor film forms a positively charged space charge region. The accumulation of high concentration electrons at the polymer/n-type semiconductor interface greatly reduces the total positive charge electric field intensity at the pentacene/polymer medium interface, thereby greatly reducing the height of the hole barrier at the pentacene/polymer medium interface. The great reduction of the hole barrier height at the interface of pentacene and polymer medium enables the working voltage for driving hole carriers from pentacene to enter the polymer or for driving hole carriers from the polymer to return to pentacene to be effectively reduced, namely the programming/erasing voltage of the organic semiconductor field effect transistor device is effectively reduced; the hole potential barrier height at the interface of pentacene and polymer medium can be regulated to a reasonable range by regulating the number of n-type carriers in the n-type semiconductor intercalation, so that the pentacene organic field effect transistor device has good programming/erasing reliability and data retention capacity, and the working performance of the pentacene organic field effect transistor is improved.
The invention has the beneficial effects that: in an organic field effect transistor device with a structure of a gate electrode/an insulating layer/a polymer medium film/a pentacene/source (drain) electrode, an n-type semiconductor intercalation film is added between the insulating layer and the polymer medium film, and the height of a hole barrier at the interface between pentacene and the polymer medium is reduced through high-density induced electrons at the interface between the n-type semiconductor intercalation film and the polymer medium, so that the programming/erasing working voltage of the pentacene organic semiconductor transistor is effectively reduced; the hole barrier height at the interface of pentacene and polymer medium is adjusted to a reasonable range by adjusting the number of n-type carriers in the n-type semiconductor intercalation, so that the pentacene organic field effect transistor device has good programming/erasing reliability and data retention capacity, and the working performance of the pentacene organic field effect transistor is improved.
The invention is based on the original device structure of gate electrode/insulating layer/polymer dielectric film/pentacene/source (drain); the chinese patent of CN201911336850.8 is an intercalation between a thin film of polymeric medium and pentacene; the invention is intercalated between the insulating layer and the polymer dielectric film, the intercalation positions are different, the finally obtained device has different structures and different effects, mainly has better regulation and control performance and higher response speed, and can improve the performance of the device.
Drawings
Fig. 1: an organic field effect transistor structure schematic diagram based on a method for improving the working performance of a pentacene organic field effect transistor by utilizing n-type semiconductor intercalation, wherein 1 is a gate electrode, 2 is an insulating layer medium, 3 is n-type semiconductor intercalation, 4 is a polymer medium film, 5 is pentacene, and 6 is a source electrode and a drain electrode;
fig. 2: the transfer characteristic curve of a ZnO intercalated pentacene organic field effect transistor is increased, wherein the charge trapping medium is poly (2-vinyl naphthalene) (PVN), and the organic semiconductor layer is pentacene;
fig. 3: a transfer characteristic curve of a pentacene organic field effect transistor without ZnO intercalation, wherein the charge trapping medium is poly (2-vinyl naphthalene) (PVN), and the organic semiconductor layer is pentacene;
fig. 4: the anti-fatigue characteristic curve of a ZnO intercalated pentacene organic field effect transistor is increased, wherein the charge trapping medium is poly (2-vinyl naphthalene) (PVN), and the organic semiconductor layer is pentacene;
fig. 5: the erasing and writing retention characteristic curve of a ZnO intercalated pentacene organic field effect transistor is increased, wherein the charge trapping medium is poly (2-vinyl naphthalene) (PVN), and the organic semiconductor layer is pentacene;
fig. 6: transfer characteristic curve of pentacene organic field effect transistor with IGZO intercalation is increased, wherein the growth parameter of IGZO is Ar:O 2 =15:1, growth time 1min, thickness 10nm, charge trapping medium poly (2-vinylnaphthalene) (PVN), organic semiconductor layer pentacene;
fig. 7: the erasing and writing maintaining characteristic curve of the pentacene organic field effect transistor with the IGZO intercalation is increased, wherein the growth parameter of the IGZO is Ar:O 2 Time of growth =15:1For 1min, the thickness is 10nm, the charge trapping medium is poly (2-vinyl naphthalene) (PVN), and the organic semiconductor layer is pentacene;
fig. 8: transfer characteristic curve of pentacene organic field effect transistor with IGZO intercalation is increased, wherein the growth parameter of IGZO is Ar:O 2 =15:1, growth time 2min, thickness 20nm, charge trapping medium poly (2-vinylnaphthalene) (PVN), organic semiconductor layer pentacene;
fig. 9: the erasing and writing maintaining characteristic curve of the pentacene organic field effect transistor with the IGZO intercalation is increased, wherein the growth parameter of the IGZO is Ar:O 2 =15:1, growth time 2min, thickness 20nm, charge trapping medium poly (2-vinylnaphthalene) (PVN), organic semiconductor layer pentacene;
fig. 10: transfer characteristic curve of pentacene organic field effect transistor with IGZO intercalation is increased, wherein the growth parameter of IGZO is Ar:O 2 =15:0.5, growth time 1min, thickness 10nm, charge trapping medium poly (2-vinylnaphthalene) (PVN), organic semiconductor layer pentacene;
fig. 11: the erasing and writing maintaining characteristic curve of the pentacene organic field effect transistor with the IGZO intercalation is increased, wherein the growth parameter of the IGZO is Ar:O 2 =15:0.5, growth time 1min, thickness 10nm, charge trapping medium poly (2-vinylnaphthalene) (PVN), organic semiconductor layer pentacene;
Detailed Description
Example 1
The structure of the traditional pentacene organic field effect transistor is a gate electrode/an insulating layer/a polymer dielectric film/a pentacene/source (drain) electrode, and an n-type semiconductor film intercalation is arranged between the insulating layer and the polymer dielectric;
the n-type semiconductor intercalation can be an n-type inorganic semiconductor film or an n-type organic semiconductor film;
the preparation method of the n-type inorganic semiconductor film comprises a magnetron sputtering method, a thermal evaporation method or an electron beam evaporation method, and the thickness of the n-type inorganic semiconductor film is in the range of 1-200nm. The preparation method of the n-type organic semiconductor intercalation comprises a solution method, such as spin-coating, sol-gel, spray-coating, screen-printing, ink-jet printing, thermal evaporation, or other similar physical and chemical film preparation methods; the thickness range is 1-100nm;
the n-type semiconductor intercalation can also be two n-type semiconductor composite structure films; an n-type inorganic semiconductor film is prepared on the surface of the n-type organic semiconductor film, or an n-type polymer film is prepared on the surface of the n-type organic semiconductor film; the thickness of the n-type organic semiconductor film in the composite structure film is 0.5-60nm, the thickness of the n-type inorganic semiconductor film is 0.5-60nm, but the thickness of the composite structure film is 1-100nm.
The polymer medium film has charge capturing effect, and the polymer medium is preferably PS, PVN, but not limited to, and the preparation method comprises solution method, such as spin-coating, sol-gel, spray coating, silk-screen printing, ink-jet printing, thermal evaporation, or other similar physical and chemical film preparation methods, and the thickness of the film ranges from 1nm to 100nm;
the electrode, source electrode and drain electrode can be metal, conductive nitride or conductive oxide material, and the preparation method comprises physical deposition method such as radio frequency magnetron sputtering method, electron beam evaporation method, etc., or chemical deposition method such as atomic layer deposition method (ALD method); the gate electrode of the bottom gate type field effect transistor can also be n-type heavily doped high-conductivity silicon or p-type heavily doped high-conductivity silicon and the like; the gate electrode of the bottom gate field effect transistor may also be a flexible, conductively coated substrate.
Taking fig. 1 as an example, the implementation method is illustrated. In FIG. 1, 1 is a <100> -crystal orientation heavily doped p-Si gate electrode with resistivity less than 0.005 Ω·cm; 2 is silicon dioxide with the thickness of 90nm;3 is zinc oxide (ZnO) with the thickness of 10nm;4 is poly (2-vinyl naphthalene) (PVN) with a thickness of 40nm;5 is pentacene with the thickness of 40nm;6 is a copper source-drain electrode with the thickness of 100nm;
the specific preparation process comprises the following steps: thermal oxidation of SiO at 90nm 2 Covered p-SAnd (3) ultrasonically cleaning the substrate for 10 minutes by using acetone, ethanol and deionized water in sequence, and drying the substrate by using a nitrogen gun for standby.
Zinc oxide (ZnO) of 10nm was grown on the above p-Si substrate using a magnetron sputtering method.
Since O atoms are easy to be deleted in the preparation process, the ZnO film grown by using the magnetron sputtering method is an n-type semiconductor, and the ZnO film is in n-type semiconductor characteristic due to the deficiency of O components.
Next, a 40nm PVN charge-trapping medium was grown on the ZnO-grown substrate using spin-coating.
Then, pentacene of 40nm was grown on the substrate on which the charge trapping medium was grown using vacuum thermal evaporation.
A copper (Cu) electrode with a side length of 300 μm and a thickness of 100nm was grown on the sample of pentacene grown by vacuum thermal evaporation.
Scribing a corner of the device with a diamond knife until p-Si is leaked out, and taking the corner as a gate electrode;
the Keithley 4200 (4200-SCS) semiconductor analysis system is used for testing the electrical performance of the prepared device, and the performance parameters such as the output characteristic, transfer characteristic, erasing speed, fatigue resistance and retention performance of the device are analyzed through the response relation between the test current and the applied voltage;
the device realizes the switching process as follows: when the device works, a certain voltage is applied between two adjacent Cu electrodes of the device, namely the source electrode and the drain electrode, if the gate voltage is not available or is very small, the current in pentacene between the source electrode and the drain electrode is usually very small, the current characteristic is similar to that of an insulator, and the device is in an off state; when a high enough voltage is applied to the gate electrode, a conducting channel is generated at the interface of pentacene, which is close to the insulating layer, and the current between the source electrode and the drain electrode is rapidly increased, so that the device is conducted and becomes an on state; the device thus implements a switching process.
FIG. 2 is a graph showing the transfer characteristic of the pentacene organic field effect transistor with ZnO intercalation added in example 1, wherein the source-drain voltage is-5V, the test range of the erasing and scanning voltage is + -10V to + -30V, the memory window in the transfer characteristic is seen to be rapidly enlarged along with the voltage increase, and when the erasing and scanning voltage is + -30V, the window exceeds 30V, and the on-state and off-state are distinguished obviously.
FIG. 3 shows the transfer characteristic of pentacene organic field effect transistor without ZnO intercalation, wherein the source-drain voltage is-5V, the test range of erasing and scanning voltage is + -15V to + -40V, and when the erasing and scanning voltage is less than + -25V, the transfer characteristic has almost no deviation between the programming and erasing curves, and then the curve memory window becomes larger slowly with the increase of the gate voltage. When the erasing and writing scanning voltage is + -35V, the window is still smaller than 10V, and the on state and the off state are not obvious.
As can be seen from comparison of fig. 2 and fig. 3, after ZnO intercalation is added, the window of the device is significantly enlarged, and the erasing capability is significantly improved.
FIG. 4 is a graph showing the fatigue resistance of the pentacene organic field effect transistor of example 1 with ZnO intercalation, wherein the write pulse is 30V/1s, the erase pulse is-30V/1 s, the gate voltage is-5V, and the read voltage is 0V. It can be seen that the initial switching current ratio of the device is 1.0X10 6 After 10000 times of erasing, the switching current ratio of the device is still 1.0 multiplied by 10 2 This indicates that the erasure fatigue characteristics of the device are good.
FIG. 5 is a retention characteristic of a pentacene organic field effect transistor with ZnO intercalation of example 1, in which the write pulse is 30V/1s, the erase pulse is-30V/1 s, the gate voltage is-5V, the read voltage is 0V, and the retention characteristic is 1X 10 4 The s-post switching ratio is 1.8X10 4 Indicating that the retention characteristics of the device are excellent.
Example 2
The difference between this example and example 1 is that the n-type semiconductor intercalation 3 is Indium Gallium Zinc Oxide (IGZO) with a thickness of 10nm, the preparation method still adopts magnetron sputtering method, and the flow ratio of argon to oxygen adopted in the sputtering is Ar:O 2 =15:1, growth time was 1min.
FIG. 6 is a graph showing the transfer characteristics of the pentacene organic field effect transistor with IGZO intercalation added in example 2, wherein the source-drain voltage is-5V, the test range of the erasing and scanning voltage is + -15V to + -35V, the window can be seen to be rapidly enlarged along with the increase of the erasing and scanning voltage, when the erasing and scanning voltage is + -35V, the erasing window exceeds 30V, and the on-state and off-state are distinguished obviously.
As can be seen from a comparison between fig. 6 and fig. 3, after IGZO intercalation is added, the erasing window of the device is significantly enlarged, and the erasing capability is significantly improved.
FIG. 7 shows the erase and retention characteristics of a pentacene organic field effect transistor with IGZO intercalation of example 2, wherein the write pulse is 35V/1s, the erase voltage is-25V/1 s, the gate voltage is-5V, the read voltage is 0V, and the voltage is 1×10 4 The s-post switching ratio is 3.8X10 1 Indicating good erase and write retention characteristics of the device.
Example 3
The difference between this example and example 1 is that the n-type semiconductor thin film intercalation 3 is Indium Gallium Zinc Oxide (IGZO) with a thickness of 20nm, the preparation method still adopts a magnetron sputtering method, and the flow ratio of argon to oxygen adopted in the sputtering is Ar:O 2 =15:1, growth time was 2min. The parameters used in the growth process were exactly the same as in example 2 except for the growth time, so that the carrier concentration was exactly the same as in example 2, and the increase in thickness increased the total carrier number compared to example 2.
FIG. 8 is a graph showing the erasure transfer characteristics of the pentacene organic field effect transistor with the IGZO intercalation added in example 3, wherein the source-drain voltage is-5V, the erasure scan voltage test range is + -15V to + -35V, the window is seen to be rapidly enlarged along with the increase of the erasure scan voltage, when the erasure scan voltage is + -35V, the erasure window exceeds 40V, and the on-state and off-state distinction is obvious.
As can be seen from a comparison between fig. 8 and fig. 6, the erasing window in example 3 is larger than that in example 2, and it is understood that the memory window of the device is larger as the number of carriers is increased. This is because the more n-type carriers in the IGZO intercalation, the more negative charges are accumulated at the IGZO/PVN interface, the more the barrier at the pentacene/PVN interface is lowered, and the more the device erasure capability is improved.
Fig. 9 is a holding characteristic curve of the pentacene organic field effect transistor of example 3 with the addition of the IGZO intercalation, in which the write pulse is 35V/1s, the erase voltage is-25V/1 s, the gate voltage is-5V, the read voltage is 0V, the switching ratio is already less than 10 after 2000s, and the device holding property is poor.
As can be seen from a comparison of fig. 9 and 7, the erasure holding characteristics in example 3 are inferior to those in example 2, because the larger the number of n-type carriers in IGZO intercalation, the more negative charges are accumulated at the IGZO/PVN interface, the more the potential barrier of the pentacene/PVN interface is lowered, and holes trapped by PVN are more likely to spontaneously return into pentacene.
From the above, it is known that, when the n-type carrier concentration of the IGZO intercalation is kept unchanged, the thicker the IGZO intercalation, the larger the number of n-type carriers, but the larger the erasing window of the device, the retaining property of the device is also lowered, so that a proper thickness must be selected to enable the device to have a larger erasing window and good retaining property.
Example 4
The difference between this example and example 1 is that the n-type semiconductor thin film intercalation 3 is Indium Gallium Zinc Oxide (IGZO) with a thickness of 10nm, the preparation method still adopts a magnetron sputtering method, and the flow ratio of argon to oxygen adopted in the sputtering is Ar:O 2 =15:0.5, growth time was 1min. The parameters adopted in the growth process are identical to those in example 2 except for the argon-oxygen ratio, so the thickness is unchanged; and the lower oxygen ratio used in example 3 results in a higher number of oxygen vacancies in the IGZO film, thereby resulting in a higher carrier concentration than in example 2 and an increased carrier number than in example 2.
Fig. 10 is a transfer characteristic curve of the pentacene organic field effect transistor with the IGZO intercalation added in example 4, wherein the source-drain voltage is-5V, the test range of the erase-scan voltage is + -15V to + -35V, it can be seen that the window rapidly becomes larger with the increase of the erase-scan voltage, and when the erase-scan voltage is + -35V, the window exceeds 35V, and the on-state and off-state distinction is obvious.
As can be seen from a comparison between fig. 10 and fig. 6, the erasing window in example 4 is larger than that in example 2, and it is understood that the memory window of the device is larger as the number of carriers is increased. This is because the greater the number of n-type carriers in the IGZO intercalation, the greater the negative charge accumulated at the IGZO/PVN interface, the greater the barrier drop at the pentacene/PVN interface, and the improved device erasure capability.
FIG. 11 is a graph showing the retention characteristics of the pentacene organic field effect transistor of example 4 with the addition of the IGZO intercalation, wherein the write pulse is 35V/1s, the erase voltage is-25V/1 s, the gate voltage is-5V, the read voltage is 0V, the switching ratio is already less than 10 after 2000s, and the retention of the device is poor.
As can be seen from a comparison of fig. 11 and fig. 7, the erasure holding characteristic in example 4 is inferior to that in example 2, because the larger the number of n-type carriers in IGZO intercalation, the more negative charges are accumulated at the IGZO/PVN interface, the more the potential barrier of the pentacene/PVN interface is lowered, and holes trapped by PVN are more likely to spontaneously return into pentacene.
From the above, it is known that, when the thickness of the IGZO intercalation is kept unchanged, the higher the n-type carrier concentration of the IGZO intercalation is, the larger the number of n-type carriers is, but the larger the erasing window of the device is, but the holding characteristic of the device is also lowered, so that the device must be selected to have a larger erasing window and good holding characteristic at the same time.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explanation of the principles of the present invention and are in no way limiting of the invention. Accordingly, any modification, equivalent replacement, improvement, etc. made without departing from the spirit and scope of the present invention should be included in the scope of the present invention. Furthermore, the appended claims are intended to cover all such changes and modifications that fall within the scope and boundary of the appended claims, or equivalents of such scope and boundary.

Claims (10)

1. A method for improving the working performance of pentacene organic field effect transistor by using n-type semiconductor intercalation, the structure of the organic field effect transistor device is bottom gate type: from bottom to top, gate electrode/insulating layer/polymer dielectric film/pentacene/source or drain electrode, respectively; the structure of the organic field effect transistor device is a top gate type structure, which is a source or drain electrode/pentacene/polymer dielectric film/insulating layer/gate electrode from bottom to top, and is characterized in that an n-type semiconductor film intercalation is added between the insulating layer and the polymer dielectric film; the gate electrode is a conductor with resistivity less than 0.005 omega-cm, the insulating layer medium is an insulator, and the n-type semiconductor film is an n-type inorganic semiconductor film or an n-type organic semiconductor film; the polymer medium film is a charge trapping medium and has a thickness of 1-100nm; pentacene has a thickness of 1-100nm; the thickness of the source electrode or the drain electrode is 50-200nm; the n-type semiconductor film is an n-type inorganic semiconductor film, and the n-type inorganic semiconductor film comprises zinc selenide, zinc sulfide, zinc oxide, indium gallium zinc oxide IGZO, an oxygen-deficient oxide film or an oxygen-deficient composite oxide film;
the preparation method of the n-type inorganic semiconductor film comprises a magnetron sputtering method, a thermal evaporation method or an electron beam evaporation method, wherein the thickness of the n-type inorganic semiconductor film ranges from 1nm to 200nm, and the n-type inorganic semiconductor film is a crystalline film or an amorphous film;
the n-type semiconductor film can accumulate high density electrons near the interface of the polymer medium film, which is caused by electrostatic induction phenomenon due to positively charged interface layer existing at the position of pentacene near the interface of the polymer medium film; and the total positive charge electric field at the pentacene/polymer interface is greatly reduced due to the accumulation of high-density electrons at the polymer/n-type semiconductor interface, so that the hole barrier height at the interface between pentacene and a polymer medium is greatly reduced.
2. The method according to claim 1, wherein the composite oxide film is ZrHfO 2-δ 。
3. The method according to claim 1, wherein the N-type semiconductor film is an N-type organic semiconductor film and is an N-type small molecule film comprising N-N "-di-3-N-pentylalkyl-3, 4,9, 10-perylene diimide PTCDI-C13, N-N" -di-N-tridecyl-3, 4,9, 10-perylene diimide EP-PDI or N-N "-diphenyl-1, 4,5, 8-Nediimide (NDI).
4. The method of claim 3, wherein the n-type semiconductor film is an n-type semiconductor crystalline film, a semi-crystalline film, or an amorphous film.
5. The method according to claim 3, wherein the method for preparing an n-type organic semiconductor thin film comprises a solution method comprising a spin coating method, a sol-gel method, a spray coating method or a screen printing method, an inkjet printing method or a thermal evaporation method, and the thickness of the n-type organic semiconductor thin film ranges from 1 to 100nm.
6. The method of claim 1, wherein the n-type semiconductor thin film is a two-type semiconductor composite structure thin film; an n-type inorganic semiconductor film is prepared on the surface of an n-type organic semiconductor film, or an n-type polymer film is prepared on the surface of an n-type organic semiconductor film.
7. The method according to claim 6, wherein the n-type organic semiconductor film in the composite film has a thickness of 0.5 to 60nm and the n-type inorganic semiconductor film has a thickness of 0.5 to 60nm.
8. The method of claim 1, wherein the polymer medium is a polystyrene, poly (2-vinyl naphthalene) (PVN) or poly-alpha-methyl styrene (pαms) organic film having a thickness of 1-100nm.
9. The method of claim 8, wherein the polymer medium film preparation method comprises a solution method, and the solution method is a spin coating method, a sol-gel method, a spray coating method, a screen printing method or an inkjet printing method.
10. Pentacene organic field effect transistor memory device obtainable by the method according to one of the claims 1 to 9, characterized in that the structure of the organic field effect transistor device is bottom gate: from bottom to top, respectively, a gate electrode/an insulating layer/an n-type semiconductor thin film intercalation/a polymer dielectric thin film/pentacene/a source or drain electrode; the structure of the organic field effect transistor device is top gate type, and the structure is source or drain electrode/pentacene/polymer dielectric film/n-type semiconductor film intercalation/insulating layer/gate electrode from bottom to top.
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