CN112366205B - Semiconductor device and preparation method thereof - Google Patents

Semiconductor device and preparation method thereof Download PDF

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Publication number
CN112366205B
CN112366205B CN202011240548.5A CN202011240548A CN112366205B CN 112366205 B CN112366205 B CN 112366205B CN 202011240548 A CN202011240548 A CN 202011240548A CN 112366205 B CN112366205 B CN 112366205B
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oxide layer
thickness
oxide
forming
semiconductor device
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CN112366205A (en
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刘思敏
徐伟
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention discloses a semiconductor device and a preparation method thereof, wherein a step structure is formed firstly, and then a first oxide layer, a second oxide layer, a third oxide layer and a fourth oxide layer which cover the step structure are sequentially formed, wherein the first oxide layer and the third oxide layer are both high-density plasma oxides, and the second oxide layer and the fourth oxide layer are both ethyl orthosilicate. By means of multiple alternate deposition of HDP CVD and PE CVD, the hole filling capacity of the HDP CVD can be brought into full play, and meanwhile, the material consumption of the HDP CVD is reduced, so that the wafer warping condition is improved on the premise that filling is not affected, and the cost can be reduced.

Description

Semiconductor device and preparation method thereof
Technical Field
The present invention relates generally to electronic devices and, more particularly, to a semiconductor device and a method of manufacturing the same.
Background
The NAND memory device is a nonvolatile memory product having low power consumption, light weight, and excellent performance, and is widely used in electronic products.
NAND devices of a planar structure have been approaching the limit of practical expansion, and in order to further improve the memory capacity and reduce the memory cost per bit, 3D NAND memory devices have been proposed. In the 3D NAND memory device structure, a mode of vertically stacking a plurality of layers of gates is adopted, the central area of a stacking layer is a core area, the edge area of the stacking layer is a step area, the core area is used for forming memory units, a conductive layer in the stacking layer is used as a grid line of each layer of memory units, and the grid line is led out through contact on the step, so that the stacking type 3D NAND memory device is realized.
With the increasing number of layers, the delay effect caused in the read-write process becomes more and more obvious because the transmission distance is longer and the resistance is increased. In order to reduce the hysteresis effect, a step region is designed at the middle position of the chip by the 3DNAND with a higher layer number, and the hysteresis effect is correspondingly reduced due to the reduction of the current transmission path. Due to the change of the position of the step area, the design appearance of the step area is also changed, and new challenges are brought to the filling of the step area.
Disclosure of Invention
The invention aims to provide a novel filling method for a stepped area, which is used for reducing the stress of the stepped area, further reducing the situation that a wafer is warped and reducing the cost.
In one aspect, an embodiment of the present invention provides a semiconductor, including:
a substrate;
a stack of alternating layers of insulating and conductor layers on the substrate, the stack comprising an array region and a stepped region adjacent to the array region in a first lateral direction parallel to the substrate, the stepped region having at least one step structure in the first lateral direction;
a first oxide layer covering the step structure;
the second oxidation layer is positioned on the surface of the first oxidation layer;
a third oxide layer positioned on the surface of the second oxide layer, wherein the third oxide layer is made of the same material as the first oxide layer;
and the fourth oxide layer is positioned on the surface of the third oxide layer, and the material of the fourth oxide layer is the same as that of the second oxide layer.
Preferably, the thickness of the second oxide layer is greater than that of the first oxide layer, the thickness of the fourth oxide layer is greater than that of the third oxide layer, and the surface of the fourth oxide layer is at least flush with the stack surface of the array region.
Further preferably, the first oxide layer and the third oxide layer include a high-density plasma oxide formed by high-density plasma chemical vapor deposition, and the second oxide layer and the fourth oxide layer include tetraethoxysilane formed by plasma-enhanced chemical vapor deposition.
Further preferably, the thickness of the first oxide layer is 300-500 nm.
Further preferably, the second oxide layer and the third oxide layer have a first opening and a second opening, respectively, which are enlarged upward at the top of the step structure.
In another aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate;
forming a stack of alternately stacked insulating layers and sacrificial layers on the substrate, the stack including an array region and a stepped region adjacent to the array region in a first lateral direction parallel to the substrate, the stepped region having at least one step structure in the first lateral direction;
forming a first oxide layer covering the step structure;
forming a second oxide layer on the surface of the first oxide layer;
forming a third oxide layer on the surface of the second oxide layer, wherein the third oxide layer is made of the same material as the first oxide layer;
and forming a fourth oxide layer on the surface of the third oxide layer, wherein the fourth oxide layer and the second oxide layer are made of the same material.
Preferably, the thickness of the second oxide layer is greater than that of the first oxide layer, the thickness of the fourth oxide layer is greater than that of the third oxide layer, and the surface of the fourth oxide layer is at least flush with the stack surface of the array region.
Further preferably, the step of forming the first oxide layer and the third oxide layer includes: depositing a high-density plasma oxide by adopting a high-density plasma chemical vapor deposition process; a step of forming the second oxide layer and the fourth oxide layer, including: and depositing the ethyl orthosilicate by adopting a plasma enhanced chemical vapor deposition process.
Further preferably, the thickness of the first oxide layer is 300-500 nm.
Further preferably, the step of forming the second oxide layer further includes: etching the second oxide layer to form a first opening which is expanded upwards on the top of the step structure; the step of forming the third oxide layer further includes: and forming a second opening which is expanded upwards on the top of the step structure by controlling the deposition etching ratio in the high-density plasma chemical vapor deposition.
The invention has the beneficial effects that: the semiconductor device comprises an array region and a step region adjacent to the array region, wherein the step region is provided with at least one step structure, and a first oxide layer, a second oxide layer, a third oxide layer and a fourth oxide layer which cover the step structure are sequentially formed, wherein the first oxide layer and the third oxide layer are made of the same material, and the second oxide layer and the fourth oxide layer are made of the same material. Because a very deep groove is formed at the deepest step of the step region, the step structure can be filled more easily by a multi-deposition method, the filling effect is ensured, and simultaneously the dosage of the first oxide layer and the third oxide layer can be reduced, so that the warping degree of the wafer is reduced.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a semiconductor device provided by an embodiment of the present invention at a-a1 in fig. 1;
fig. 3 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention at B-B1 in fig. 2;
fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 5a to 5c are schematic structural diagrams of a semiconductor device provided by an embodiment of the invention in a manufacturing process.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
As used herein, the term "semiconductor device" refers to a semiconductor device having a vertically oriented array structure on a laterally oriented substrate such that the array structure extends in a vertical direction relative to the substrate. As used herein, the term "first lateral direction" refers to a direction parallel to the substrate, denoted by "X"; the direction perpendicular to "X" is denoted by "Y" in the drawings, and the direction perpendicular to the substrate is denoted by "Z" in the drawings.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention, and fig. 2 is a schematic cross-sectional view of the semiconductor device at a-a1 in fig. 1 according to an embodiment of the present invention. The semiconductor device includes a substrate 10 and a stack 20 on the substrate 10, the stack 20 being formed by alternately laminating insulating layers 201 and conductor layers 202. The stack 20 comprises an array region 21 and a step region 22 adjacent to said array region 21 in a first lateral direction (X) parallel to the substrate 10.
In the present embodiment, there are a plurality of array regions 21 and a step region 22 located between two adjacent array regions 21, and the step region 22 has at least one step structure 221 in the X direction, and only two array regions 21 and the step region 22 located between two array regions 21 are shown in the figure.
In the present embodiment, the stepped region 22 has two step structures 221 opposing in the X direction. Since the step structure 221 of the stepped region 22 in fig. 2 is not a regular stair structure, the structure is complicated, and the specific structure of the filling layer 222 of the stepped region 22 is not shown. As shown in fig. 2, a very deep trench is formed between two opposite step structures 221, where filling is most difficult, and therefore the following description focuses on the specific structure of the filling layer 222 of the step region 22 at B-B1 in fig. 2.
In some embodiments, it is also possible that the step region 22 is located at the edge of the substrate 10 and the array region 21 is located in the middle of the substrate 10. In the case that the step region 22 of the present embodiment is located in the middle, one array region 21 and one step structure 221 may be arranged at intervals, and the number of the step structures 221 of the step region 22 is not limited in the embodiment of the present invention.
It should be noted that, in fig. 1, the step region 22 does not extend in the Y direction, but the etching is not performed at the edge in the Y direction, that is, the step region 22 does not include edges at both sides, so that the step structure 221 shown in fig. 2 is not formed at the edge position. Therefore, the cross section at B-B1 in fig. 2 is also a stacked structure of the insulating layer 201 and the conductor layer 202 on both sides in the Y direction.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a semiconductor device provided in the embodiment of the invention at B-B1 in fig. 2. The semiconductor device further includes a first oxide layer 40 covering the step structure 221, a second oxide layer 50 located on the surface of the first oxide layer 40, a third oxide layer 60 located on the surface of the second oxide layer 50, wherein the third oxide layer 60 is made of the same material as the first oxide layer 40, and a fourth oxide layer 70 located on the surface of the third oxide layer 60, and the fourth oxide layer 70 is made of the same material as the second oxide layer 50.
Preferably, the thickness of the second oxide layer 50 is greater than that of the first oxide layer 40, the thickness of the fourth oxide layer 70 is greater than that of the third oxide layer 60, and the surface of the fourth oxide layer 70 is at least flush with the surface of the stack 20 of the array region 21, i.e. completely fills the step region 22.
Preferably, the first oxide layer 40 and the third oxide layer 60 may include a High Density Plasma oxide (HDP OX) formed by a High Density Plasma Chemical Vapor Deposition (HDPCVD), and the second oxide layer 50 and the fourth oxide layer 70 may include tetraethyl orthosilicate (TEOS) formed by a Plasma Enhanced Chemical Vapor Deposition (PECVD), wherein the thickness of the High Density Plasma oxide is less than that of the tetraethyl orthosilicate.
Because the high-density plasma chemical vapor deposition has higher cost, but the high-density plasma chemical vapor deposition has good pore filling capability, the obtained high-density plasma oxide has higher compactness and higher stress. In the embodiment, the thickness of the first oxide layer 40 is in the range of 300-500nm, which not only ensures the uniformity of the upper and lower thickness in the deep hole, but also reduces the usage amount of the high-density plasma oxide, thereby reducing the stress and improving the wafer warpage without affecting the filling.
In the present embodiment, the second oxide layer 50 has a first opening 51 that is enlarged upward at the top of the step structure 221. The third oxide layer 60 on the upper surface of the second oxide layer 50 also has a second opening 61 that is enlarged upward. The first opening 51 and the second opening 61 are formed by an etching process to ensure that no gap is formed in the recess and to facilitate deposition of the upper layer.
The semiconductor device provided by the embodiment of the invention comprises a substrate 10 and a stack 20, wherein the stack 20 comprises an array region 21 and a step region 22 adjacent to the array region 21, the step region 22 has at least one step structure 221, and a first oxide layer 40 covering the step structure 221, a second oxide layer 50 located on the surface of the first oxide layer 40, a third oxide layer 60 located on the surface of the second oxide layer 50, and a fourth oxide layer 70 located on the surface of the third oxide layer 60, wherein the third oxide layer 60 and the first oxide layer 40 are made of the same material, and the fourth oxide layer 70 and the second oxide layer 50 are made of the same material. The filling layer is formed by circularly depositing the two materials, so that the filling effect can be ensured, the using amount of the first oxidation layer 40 and the third oxidation layer 60 can be reduced, and the warping condition of the wafer can be improved.
Referring to fig. 4 and fig. 5a to 5c, fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 5a to 5c are schematic structural diagrams of the semiconductor device according to the embodiment of the present invention during a manufacturing process. The manufacturing method may be used for manufacturing the above semiconductor device, and thus the structure numbers of the above semiconductor device are continued, the manufacturing method of the semiconductor device includes steps S1-S6.
Please refer to steps S1-S2 in fig. 4 and fig. 2 first.
Step S1: a substrate 10 is provided.
In the present embodiment, the substrate 10 is a semiconductor substrate, and may be, for example, Silicon (Si), Germanium (Ge), Silicon Germanium (SiGe), Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. In some embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide; but also a stacked structure such as silicon, silicon germanium, etc.
Step S2: a stack of alternating layers of insulating layers 201 and sacrificial layers is formed on the substrate 10, the stack comprising an array region 21 and a step region 22 adjacent to the array region 21 in a first lateral direction (X) parallel to the substrate 10, the step region 22 having at least one step structure 221 in the first lateral direction (X).
In this embodiment, the insulating layer 201 may be a dielectric material such as silicon oxide, hafnium oxide, aluminum oxide, or tantalum oxide, and the sacrificial layer may be silicon nitride or other conductive material. The insulating layer 201 and the sacrificial layer have different etch selectivity. The sacrificial layer is removed in a subsequent process and replaced with a conductive layer 202 as shown in fig. 2 at a corresponding location. The Deposition methods of the insulating Layer 201 and the sacrificial Layer can be, but not limited to, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or High Density Plasma Chemical Vapor Deposition (HDPCVD).
With continuing reference to step S3 in FIG. 4 and FIG. 5a, FIG. 5a shows a schematic cross-sectional view at the deepest portion B-B1 of the step structure 221.
Step S3: a first oxide layer 40 is formed covering the step structure 221.
Preferably, the first oxide layer 40 is a high density plasma oxide, and a thin layer of the high density plasma oxide with a thickness of 300nm to 50nm can be deposited by a high density plasma chemical vapor deposition process. Because of the strong hole-filling capability of the HDP-CVD process, the thickness of the material that can be deposited in the deep hole is uniform, and some corners of the stepped region 22 can be rounded without generating gaps. In addition, compared with the step region 22 which is completely filled by the high-density plasma chemical vapor deposition process, the amount of the high-density plasma oxide can be reduced, so that the cost is saved, the stress can be reduced, and the wafer warping condition is further reduced. Wherein the material of the high density plasma oxide may be SiO2。
Please refer to step S4 in fig. 4 and fig. 5a-5 b.
Step S4: a second oxide layer 50 is formed on the surface of the first oxide layer 40.
Preferably, the second oxide layer 50 is tetraethyl orthosilicate. The ethyl orthosilicate may be deposited using a plasma enhanced chemical vapor deposition process, the thickness of the ethyl orthosilicate being about 3-4 μm. In some embodiments, other lower cost deposition processes may be used to form the second oxide layer 50, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, and the like, as mentioned above.
In this embodiment, as shown in fig. 5a, the tetraethoxysilane 50' is deposited, and then the second oxide layer 50 is formed (as shown in fig. 5 b) by performing an etching process when no pinch-off or void occurs, so that the generation of a gap is avoided, and the first opening 51 which is enlarged upward is formed to facilitate a subsequent deposition process.
Please refer to step S5 in fig. 4 and fig. 5 c.
Step S5: and forming a third oxide layer 60 on the surface of the second oxide layer 50, wherein the third oxide layer 60 is made of the same material as the first oxide layer 40.
In the present embodiment, the third oxide layer 60 is formed repeatedly by using the high density plasma chemical vapor deposition process, and the thickness is about 2-4 μm. The third oxide layer 60 is made of the same material as the first oxide layer 40 and is also a high density plasma oxide. The most significant advantage of the high density plasma chemical vapor deposition method is deep hole filling, and in the semiconductor industry, the deposition etching ratio is generally adopted as an index for the filling capacity of a balanced high density plasma chemical vapor deposition process. By controlling the deposition etch ratio at the corners, it is desirable to keep the top of the corners open throughout the deposition process to allow reactants to enter the recesses and fill from the bottom. That is, by controlling the deposition-etch ratio to 1, the hole-filling capability is maximized and the second opening 61 is formed to be enlarged upward as shown in fig. 5 c.
Please refer to step S6 in fig. 4 and fig. 3.
Step S6: and forming a fourth oxide layer 70 on the surface of the third oxide layer 60, wherein the fourth oxide layer 70 is made of the same material as the second oxide layer 50.
The deposition of ethyl orthosilicate by high density plasma chemical vapor deposition process is continued to form a first oxide layer 70 having a thickness of about 4-6 μm.
In this embodiment, the thickness of the second oxide layer 50 is greater than the thickness of the first oxide layer 40, and the thickness of the fourth oxide layer 70 is greater than the thickness of the third oxide layer 50, after the step S6 is completed, the surface of the fourth oxide layer is at least flush with the surface of the stack 20 of the array region 21, that is, the step region 22 is filled with the first oxide layer 40, the second oxide layer 50, the third oxide layer 60, and the fourth oxide layer 70.
Finally, the method for manufacturing a semiconductor device further comprises: the sacrificial layer 203 in fig. 5c is replaced with a conductor layer 202 as shown in fig. 3.
In the method for manufacturing a semiconductor device according to the embodiment of the present invention, the step structure 221 is formed first, and then the first oxide layer 40, the second oxide layer 50, the third oxide layer 60, and the fourth oxide layer 70 covering the step structure 221 are formed in sequence, where the first oxide layer 40 and the third oxide layer 60 are both high-density plasma oxides, and the second oxide layer 50 and the fourth oxide layer 70 are both tetraethoxysilane. By means of multiple alternate deposition of HDP CVD and PE CVD, the hole filling capacity of the HDP CVD can be brought into full play, and meanwhile, the material consumption of the HDP CVD is reduced, so that the wafer warping condition is improved on the premise that filling is not affected, and the cost can be reduced.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (10)

1. A semiconductor device, comprising:
a substrate;
a stack of alternating layers of insulating and conductor layers on the substrate, the stack comprising an array region and a stepped region adjacent to the array region in a first lateral direction parallel to the substrate, the stepped region having at least one step structure in the first lateral direction;
a first oxide layer covering the step structure;
the second oxidation layer is positioned on the surface of the first oxidation layer;
a third oxide layer positioned on the surface of the second oxide layer, wherein the third oxide layer is made of the same material as the first oxide layer;
a fourth oxide layer located on the surface of the third oxide layer, wherein the fourth oxide layer and the second oxide layer are made of the same material;
the pore filling performance of the first oxide layer and the third oxide layer is greater than that of the second oxide layer and the fourth oxide layer; the stress of the first oxide layer and the stress of the third oxide layer are larger than the stress of the second oxide layer and the stress of the fourth oxide layer.
2. The semiconductor device according to claim 1, wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer, a thickness of the fourth oxide layer is greater than a thickness of the third oxide layer, and a surface of the fourth oxide layer is at least flush with a stack surface of the array region.
3. The semiconductor device of claim 1, wherein the first and third oxide layers comprise high density plasma oxide formed using high density plasma chemical vapor deposition, and wherein the second and fourth oxide layers comprise ethyl orthosilicate formed using plasma enhanced chemical vapor deposition.
4. The semiconductor device as claimed in claim 1, wherein the thickness of the first oxide layer is 300-500 nm.
5. The semiconductor device according to claim 2, wherein the second oxide layer and the third oxide layer have a first opening and a second opening, respectively, which are enlarged upward, on top of the step structure.
6. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a stack of alternately stacked insulating layers and sacrificial layers on the substrate, the stack including an array region and a stepped region adjacent to the array region in a first lateral direction parallel to the substrate, the stepped region having at least one step structure in the first lateral direction;
forming a first oxide layer covering the step structure;
forming a second oxide layer on the surface of the first oxide layer;
forming a third oxide layer on the surface of the second oxide layer, wherein the third oxide layer is made of the same material as the first oxide layer;
forming a fourth oxide layer on the surface of the third oxide layer, wherein the fourth oxide layer and the second oxide layer are made of the same material;
the pore filling performance of the first oxide layer and the third oxide layer is greater than that of the second oxide layer and the fourth oxide layer; the stress of the first oxide layer and the stress of the third oxide layer are larger than the stress of the second oxide layer and the stress of the fourth oxide layer.
7. The method according to claim 6, wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer, a thickness of the fourth oxide layer is greater than a thickness of the third oxide layer, and a surface of the fourth oxide layer is at least flush with a stack surface of the array region.
8. The method according to claim 6, wherein the step of forming the first oxide layer and the third oxide layer comprises: depositing a high-density plasma oxide by adopting a high-density plasma chemical vapor deposition process; a step of forming the second oxide layer and the fourth oxide layer, including: and depositing the ethyl orthosilicate by adopting a plasma enhanced chemical vapor deposition process.
9. The method as claimed in claim 6, wherein the thickness of the first oxide layer is 300-500 nm.
10. The method according to claim 8, wherein the step of forming the second oxide layer further comprises: etching the second oxide layer to form a first opening which is expanded upwards on the top of the step structure; the step of forming the third oxide layer further includes: and forming a second opening which is expanded upwards on the top of the step structure by controlling the deposition etching ratio in the high-density plasma chemical vapor deposition.
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