CN112350738A - Joint decoding method and system for accelerating soft decoding based on bit flipping algorithm - Google Patents

Joint decoding method and system for accelerating soft decoding based on bit flipping algorithm Download PDF

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CN112350738A
CN112350738A CN202011051282.XA CN202011051282A CN112350738A CN 112350738 A CN112350738 A CN 112350738A CN 202011051282 A CN202011051282 A CN 202011051282A CN 112350738 A CN112350738 A CN 112350738A
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冯全源
刘家明
程简
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Southwest Jiaotong University
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    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H03M13/2951—Iterative decoding using iteration stopping criteria
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
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Abstract

The invention discloses a joint decoding method and a system for accelerating soft decoding based on a bit flipping algorithm, wherein the method comprises the steps of obtaining the likelihood ratio and check matrix information of a FLASH channel, updating a variable matrix by adopting a sum-product algorithm, updating the check matrix by adopting the sum-product algorithm, and judging whether the dispersion degree of the difference value of the likelihood ratio of the variable matrix is greater than a preset threshold value or not; if so, terminating the soft decoding in advance, otherwise, updating the variable matrix and the check matrix again, performing bit flipping iteration on the updated hard decision input sequence by adopting a bit flipping algorithm, and outputting a decoding result. According to the invention, the soft decoding module is terminated in advance, the decoding process is advanced to the hard decoding realizable range, and then the hard decoding is used for iterative decoding, so that the iterative delay of the soft decoding can be further reduced, and the whole decoding time is further reduced; the invention realizes the effective reduction of the delay of soft decoding under the condition of keeping the original chip area not to be greatly increased.

Description

Joint decoding method and system for accelerating soft decoding based on bit flipping algorithm
Technical Field
The invention relates to the technical field of FLASH controller decoding, in particular to a joint decoding method and system for accelerating soft decoding based on a bit flipping algorithm.
Background
With the continuous progress of process nodes, the chip size of FLASH is continuously reduced, the influence of interference noise between FLASH memory cells is more serious, the reliability problem of FLASH is more and more concerned, some error control technologies are also emerged on the market to correct the transmission accuracy, such as a series of error correction methods of BCH codes, RS codes and the like, but the error correction capability of the error control technologies is limited, so that the error correction methods are gradually eliminated at present, and the LDPC codes have better error correction characteristics, so that the error correction requirements of FLASH memories are better met.
As the error correction requirement further increases, the hard decoding method represented by the bit flipping decision method is gradually replaced by some soft decoding algorithms, and the LLR obtaining method based on threshold voltage sensing also becomes the main way for the flash memory controller to obtain LLR information.
However, the design of the flash memory control chip often needs to consider the PPA index factor, and the soft decoding circuit often has a higher decoding delay than the hard decoding circuit, which brings a large influence on the overall performance. How to reduce the delay of soft decoding while performing soft decoding is a key issue at present.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a joint decoding method and system for accelerating soft decoding based on a bit flipping algorithm.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that:
in a first aspect, the present invention provides a joint decoding method for accelerating soft decoding based on a bit flipping algorithm, comprising the following steps:
s1, acquiring the likelihood ratio and check matrix information of the FLASH channel;
s2, updating the check node matrix by using a sum-product algorithm;
s3, updating the variable node matrix by a sum-product algorithm according to the updated check node matrix in the step S2, and updating the hard decision input sequence according to the information reliability index;
s4, judging whether the discrete degree of the variable node matrix likelihood ratio difference is greater than a preset threshold value or not; if yes, terminating the soft decoding in advance, and performing step S5; otherwise, returning to the step S2;
and S5, performing bit flipping iteration on the updated hard decision input sequence by adopting a bit flipping algorithm, and outputting a decoding result.
The beneficial effect of this scheme is: aiming at the problem that the current LDPC soft decoding algorithm has larger decoding delay, the invention adopts a method for assisting the soft decoding algorithm to accelerate decoding iteration based on a bit flipping algorithm, and the decoding process is advanced to a hard decoding realizable range by stopping a soft decoding module in advance, and then the hard decoding is used for iterative decoding, because the decoding time of the hard decoding is far shorter than that of the soft decoding, the iterative delay of the soft decoding can be further reduced, and the whole decoding time is further reduced; the invention realizes the effective reduction of the delay of soft decoding under the condition of keeping the original chip area not to be greatly increased.
Further, before the step S1, the method further includes the steps of:
and obtaining a hard decision input sequence z ═ z1, z2, a.
The beneficial effects of the further scheme are as follows: the input sequence is efficiently encoded so that the entire sequence can be efficiently decoded and corrected by using the LDPC decoding method.
Further, the likelihood ratio information of the FLASH channel in step S1 is represented as:
P0＝{p1，p2，……，pi}
P1＝1-P0
here, P0 represents the probability that each bit is 0, and P1 represents the probability that each bit is 1.
The beneficial effects of the further scheme are as follows: the situation of error codes of a channel and the possibility of error codes of each variable node are estimated by obtaining the likelihood ratio information, and the node with high error possibility is given higher weight, so that the decoding accuracy is effectively improved.
Further, the step S2 specifically includes the following sub-steps:
s2-1, calculating an initial check node matrix according to the channel likelihood ratio and the check matrix in the step S1;
and S2-2, updating the check node matrix by adopting a sum-product decoding algorithm according to the variable node matrix updated in the S3.
The beneficial effects of the further scheme are as follows:
further, the calculation formula of the initial check node matrix in step S2-1 is as follows:
Figure BDA0002709636620000031
Rij 1＝1-Rij 0
the update formula of the check node matrix in the step S2-2 is as follows:
Figure BDA0002709636620000032
Rij 1＝1-Rij 0
wherein R isij 0The conditional probability that the ith check equation is satisfied under the condition that the jth information bit is 0 is represented; rij 1The conditional probability that the ith check equation is satisfied under the condition that the jth information bit is 1 is shown; n (i) a local symbol information set representing a parity z constraint; qji 1The probability that the jth information bit is 1 under the condition that other check nodes except the ith check node provide information is shown; n (i) \\ j indicates that n (i) does not contain a subset of j; hjA column vector of the check matrix is represented.
The beneficial effects of the further scheme are as follows: by calculating or updating the check node matrix, the likelihood ratio information and the variable node matrix information are effectively acquired by each check node, and the error probability of each variable node of the channel can be updated and corrected by comparing the hard decision sequence z with the error probability of each node.
Further, the check matrix in step S3 is represented as:
Figure BDA0002709636620000041
Figure BDA0002709636620000042
wherein Q isji 0The probability that the jth information bit is 0 under the condition that other check nodes except the ith check node provide information is represented; pj represents the probability that the jth information bit in P0 is 0, and M (j) represents the check set of the check nodes; m (j) \\ i indicates that a subset of M (j) does not contain i.
The beneficial effects of the further scheme are as follows: by acquiring the updated check node matrix, the probability of the variable node connected with each check node is updated, so that the variable nodes connected with the check nodes are influenced by the check nodes, and the acquired probability is more accurate.
Further, the step S3 of updating the hard decision input sequence according to the information reliability index specifically includes:
setting an information reliability index of
Figure BDA0002709636620000043
Figure BDA0002709636620000044
Figure BDA0002709636620000045
Wherein x represents an information reliability index, Qj 0Represents Qji 0The sum of the row vectors; qj 1Represents Qji 1The sum of the row vectors;
judging whether the value of the information reliability index x is less than 1; if yes, updating the hard decision input sequence zi to 1; otherwise, updating the hard decision input sequence zi to 0.
The beneficial effects of the further scheme are as follows: and through the summation of the probability information of all the check nodes, the probability condition of each variable node is quantized, and then through the comparison of the probabilities of all the variable nodes being 0 or 1, the bit information which is not expected to meet the probability in the hard decision sequence z is overturned. Probability information generated by iteration is effectively utilized, so that the accuracy of the hard decision sequence z obtained after decoding is higher.
Further, the calculation formula of the degree of dispersion of the variance matrix likelihood ratio difference in step S4 is:
Figure BDA0002709636620000051
where M denotes the number of rows of the check matrix.
The beneficial effects of the further scheme are as follows: the invention carries out estimation of a decoding process and conversion of an algorithm mode according to the likelihood ratio discrete degree, adopts the total standard deviation to carry out statistics and calculation, and adopts single-precision floating point number of IEEE 754 standard to carry out operation, thereby having higher precision.
Further, the step S5 specifically includes the following sub-steps:
s5-1, calculating syndrome vector according to the updated hard decision input sequence and check matrix by using bit flipping algorithm, and expressing as
s＝z*HT
Wherein H represents a check matrix;
s5-2, calculating a turning function expressed as
Figure BDA0002709636620000052
Wherein fi represents the number of the ith variable node which does not meet the check, hj，iRepresenting a check matrix row vector;
turning over the hard decision input sequence which does not meet the check number and has the most number;
s5-3, calculating a new syndrome vector according to the reversed hard decision input sequence and the check matrix;
s5-4, judging whether the new syndrome vector is equal to 0; if yes, stopping decoding and outputting a decoding result; otherwise, the process returns to step S5-2.
The beneficial effects of the further scheme are as follows: the invention adopts a bit flipping algorithm to replace the decoding process of the second half of the soft decoding algorithm, and terminates in advance, so that the whole decoding delay is reduced, and the power consumption of the whole chip in decoding is reduced; and the adjoint sub-vector s can effectively detect the correctness of the hard decision sequence z and control the iteration to end, and when s is an all-zero vector, the bit flipping iteration is completed.
In a second aspect, the present invention further provides a decoding system applying the above method, including:
the sum-product decoding algorithm core is used for soft decoding in the early stage of decoding and comprises a check node processing module, a variable node processing module, an interactive information storage module and a discrete degree detection module; controlling each module to enable alternately through a state machine;
a variable node processing module for updating the variable node matrix and enabling the variable node matrix Q for the first timeji 0、Qji 1Carrying out initialization; when not firstly enabled, the node matrix R is checkedij 0、Rij 1Iteratively updating variable node matrix Qji 0、Qji 1Meanwhile, the updated result is operated to obtain an information reliability index x, and an output result is judged;
a check node processing module for checking the check node matrix Rij 0、Rij 1Updating, and checking the node processing module to pass Qji 0、Qji 1Matrix iterative update Rij 0、Rij 1A matrix;
a cross information storage module for storing real matrix data Qji 0、Qji 1、Rij 0、Rij 1Receiving data from the variable node processing module and the check node processing module, and updating the matrix data;
the discrete degree detection module is used for detecting the likelihood ratio discrete degree of the variable node matrix, converting a decoding algorithm according to the discrete degree and outputting an effective conversion enabling signal;
the bit flipping algorithm core is used for carrying out hard decoding at the later decoding stage and comprises a flipping function operation module and a most value searching module;
the overturning function operation module is used for performing column-by-column operation on an overturning function fi;
the maximum value searching module is used for searching the maximum value in the turnover function, accumulating the fi line by adopting an accumulator, comparing the accumulated fi value with the maximum value of the previous round in the maximum value register, updating the maximum value register and outputting the column address and the maximum value of the maximum value register;
the channel likelihood ratio/data information storage module is used for acquiring FLASH channel likelihood ratio information and quantized data subjected to hard decision under the condition of decoding the coded data and storing the FLASH channel likelihood ratio information and the quantized data into an SRAM (static random access memory); simultaneously acquiring effective address information, enabling signals, input decision sequences and likelihood ratio information, and outputting decoded sequences;
the check matrix module is used for storing the information of the check matrix H;
the state machine control module is used for controlling the switching of the decoding algorithm, selecting a decoding mode through the conversion enabling of the identification sum product decoding algorithm core and starting an enabling signal of the corresponding decoding core; a counter module is arranged in the decoding device to control the enabling times so as to control the decoding iteration times, when the counter reaches the maximum iteration times, the decoding is stopped, the output enabling and the counter are controlled by the stopping enabling, and when the stopping enabling is effective, the whole decoding process is ended;
a decoding termination checking module for detecting whether the two algorithms have met termination conditions, i.e. syndrome vector s is equal to zero vector; if the vector is zero, sending out termination enable, and stopping iteration; otherwise, the iteration is continued.
The beneficial effect of this scheme is: the two-stage combined decoding method based on bit flipping algorithm accelerated soft decoding is designed in a circuit stage, and the characteristics of high parallelism and assembly line of the circuit are utilized, so that the whole algorithm has wider application under the circuit architecture; meanwhile, the state machine is adopted to control the decoding process and switch the decoding method, and the enable signal is used to control the decoding core, so that the method has higher replaceability and robustness.
Drawings
FIG. 1 is a schematic flow chart of a joint decoding method for accelerating soft decoding based on a bit flipping algorithm according to the present invention;
fig. 2 is a schematic diagram of a bit flipping iteration flow in embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of a joint decoding system for accelerating soft decoding based on a bit flipping algorithm according to the present invention;
FIG. 4 is a diagram of the internal architecture of the parallel packet system of the bit flipping algorithm core in the joint decoding system of the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
Example 1
As shown in fig. 1, an embodiment of the present invention provides a joint decoding method for accelerating soft decoding based on a bit flipping algorithm, including the following steps S1 to S5:
s1, acquiring the likelihood ratio and check matrix information of the FLASH channel;
in this embodiment, before decoding, the present invention obtains a hard decision input sequence z ═ z1, z2, a.
Assuming that the number of symbols is i, likelihood ratio (LLR) information of the FLASH channel is acquired, and expressed as:
P0＝{p1，p2，……，pi}
P1＝1-P0
here, P0 represents the probability that each bit is 0, and P1 represents the probability that each bit is 1.
S2, updating the check node matrix by using a sum-product algorithm;
in this embodiment, step S2 specifically includes the following sub-steps:
s2-1, calculating an initial check node matrix according to the channel likelihood ratio and the check matrix in the step S1;
step S2 is entered for the first time, and the invention calculates an initial check node matrix according to the channel likelihood ratio pi and the check matrix H in step S1, and the calculation formula is:
Figure BDA0002709636620000091
Rij 1＝1-Rij 0
and S2-2, updating the check node matrix by adopting a sum-product decoding algorithm according to the variable node matrix updated in the S3.
Step S2 is not entered for the first time, and the invention updates the check node matrix by the sum-product decoding algorithm according to the content of the updated variable node matrix in S3, wherein the updating formula is as follows:
Figure BDA0002709636620000092
Rij 1＝1-Rij 0
wherein R isij 0The conditional probability that the ith check equation is satisfied under the condition that the jth information bit is 0 is represented; rij 1The conditional probability that the ith check equation is satisfied under the condition that the jth information bit is 1 is shown; n is a radical of(i) A local symbol information set representing a parity z constraint; qji 1The probability that the jth information bit is 1 under the condition that other check nodes except the ith check node provide information is shown; n (i) \\ j indicates that n (i) does not contain a subset of j; hjA column vector of the check matrix is represented.
S3, updating the variable node matrix by a sum-product algorithm according to the updated check node matrix in the step S2, and updating the hard decision input sequence according to the information reliability index;
in this embodiment, the check node matrix R updated in step S2 is used in the inventionij 0And Rij 1Updating variable node matrix Q by sum-product algorithmji 0And Qji 1Expressed as:
Figure BDA0002709636620000101
Figure BDA0002709636620000102
wherein Q isji 0Representing a variable node matrix, representing the probability that the jth information bit is 0 under the condition that other check nodes except the ith check node provide information; qji 1Representing a variable node matrix, representing the probability that the jth information bit is 1 under the condition that other check nodes except the ith check node provide information; pj represents the probability that the jth bit in P0 is 0, and M (j) represents the check set of check nodes; m (j) \\ i indicates that a subset of M (j) does not contain i.
Simultaneously setting the information reliability index x as
Figure BDA0002709636620000103
Figure BDA0002709636620000104
Figure BDA0002709636620000105
Wherein x represents an information reliability index, Qj 0Represents Qji 0The sum of the row vectors; qj 1Represents Qji 1The sum of the row vectors;
and then, updating the hard decision input sequence z according to the information reliability index x as a decision condition, wherein the hard decision input sequence z is represented as:
Figure BDA0002709636620000111
namely judging whether the value of the information reliability index x is less than 1; if yes, updating the hard decision input sequence zi to 1; otherwise, updating the hard decision input sequence zi to 0.
S4, judging whether the discrete degree of the variable node matrix likelihood ratio difference is greater than a preset threshold value or not; if yes, terminating the soft decoding in advance, and performing step S5; otherwise, returning to the step S2;
in this embodiment, in the update iteration process of the variable node matrix and the check node matrix, the variable node matrix Q is calculated at each iterationji 0And Qji 1Judging whether the discrete degree L of the variable node matrix likelihood ratio difference is greater than a preset threshold value, wherein the calculation formula of the discrete degree of the variable node matrix likelihood ratio difference is as follows:
Figure BDA0002709636620000112
wherein M represents the number of rows of the check matrix; the preset threshold is set at 0.4765.
When the discrete degree L of the variable node matrix likelihood ratio difference is greater than 0.4765, terminating the soft decoding in advance, and performing step S5; otherwise, the process returns to step S2-2.
And S5, performing bit flipping iteration on the updated hard decision input sequence by adopting a bit flipping algorithm, and outputting a decoding result.
In this embodiment, as shown in fig. 2, step S5 specifically includes the following sub-steps:
s5-1, calculating an adjoint sub-vector S expressed as
s＝z*HT
S5-2, calculating a turning function fi expressed as
Figure BDA0002709636620000121
Wherein fi represents the number of the ith variable node which does not meet the check, hj，iRepresenting a check matrix row vector;
turning over the hard decision input sequence which does not meet the maximum check number (namely the maximum value of fi);
s5-3, calculating a new syndrome vector S according to the reversed hard decision input sequence and the check matrix;
s5-4, judging whether the new syndrome vector S is equal to 0; if yes, stopping decoding and outputting a decoding result; otherwise, the process returns to step S5-2.
Example 2
An embodiment of the present invention further provides a decoding system using the soft decoding method based on the soft decoding method, as shown in fig. 3 and 4, including:
the sum-product decoding algorithm core is used for soft decoding in the early stage of decoding and comprises a check node processing module, a variable node processing module, an interactive information storage module and a discrete degree detection module; controlling each module to enable alternately through a state machine;
a variable node processing module for updating the variable node matrix and enabling the variable node matrix Q for the first timeji 0、Qji 1Carrying out initialization; when not first enabled, pass check node matrixRij 0、Rij 1Iteratively updating variable node matrix Qji 0、Qji 1Meanwhile, the updated result is operated to obtain an information reliability index x, and an output result is judged;
a check node processing module for checking the check node matrix Rij 0、Rij 1Updating, and checking the node processing module to pass Qji 0、Qji 1Matrix iterative update Rij 0、Rij 1A matrix;
a cross information storage module for storing 4 sets of real matrix data Qji 0、Qji 1、Rij 0、Rij 1Receiving data from the variable node processing module and the check node processing module, and updating the matrix data;
the discrete degree detection module is used for detecting the likelihood ratio discrete degree of the variable node matrix, converting a decoding algorithm according to the discrete degree and outputting an effective conversion enabling signal;
the bit flipping algorithm core is used for carrying out hard decoding at the later decoding stage and comprises a flipping function operation module and a most value searching module;
the turnover function operation module is used for calculating the turnover function F, and adopts 8 groups of parallel operation architectures, so that the decoding delay is effectively reduced, and the decoding efficiency is improved; due to the quasi-cyclic characteristic of the H matrix, the row vector H of the check matrixi，jThrough the cyclic shift module, the column-by-column operation of the turning function fi can be realized;
the maximum value searching module is used for searching the maximum value in the turnover function, accumulating the fi line by adopting an accumulator, comparing the accumulated fi value with the maximum value of the previous round in the maximum value register, updating the maximum value register and outputting the column address and the maximum value of the maximum value register;
the channel likelihood ratio/data information storage module is used for acquiring FLASH channel likelihood ratio information and quantized data subjected to hard decision under the condition of decoding the coded data and storing the FLASH channel likelihood ratio information and the quantized data into an SRAM (static random access memory); simultaneously acquiring effective address information, enabling signals, input decision sequences and likelihood ratio information, and outputting decoded sequences;
the check matrix module is used for storing the information of the check matrix H;
the state machine control module is used for controlling the switching of the decoding algorithm, selecting a decoding mode through the conversion enabling of the identification sum product decoding algorithm core and starting an enabling signal of the corresponding decoding core; a counter module is arranged in the decoding device to control the enabling times so as to control the decoding iteration times, when the counter reaches the maximum iteration times, the decoding is stopped, the output enabling and the counter are controlled by the stopping enabling, and when the stopping enabling is effective, the whole decoding process is ended;
a decoding termination checking module for detecting whether the two algorithms have met termination conditions, i.e. syndrome vector s is equal to zero vector; if the vector is zero, sending out termination enable, and stopping iteration; otherwise, the iteration is continued.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principle and the implementation mode of the invention are explained by applying specific embodiments in the invention, and the description of the embodiments is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.

Claims (10)

1. A joint decoding method for accelerating soft decoding based on a bit flipping algorithm is characterized by comprising the following steps:
s1, acquiring the likelihood ratio and check matrix information of the FLASH channel;
s2, updating the check node matrix by using a sum-product algorithm;
s3, updating the variable node matrix by a sum-product algorithm according to the updated check node matrix in the step S2, and updating the hard decision input sequence according to the information reliability index;
s4, judging whether the discrete degree of the variable node matrix likelihood ratio difference is greater than a preset threshold value or not; if yes, terminating the soft decoding in advance, and performing step S5; otherwise, returning to the step S2;
and S5, performing bit flipping iteration on the updated hard decision input sequence by adopting a bit flipping algorithm, and outputting a decoding result.
2. The joint decoding method for accelerating soft decoding based on bit flipping algorithm of claim 1, wherein said step S1 further comprises, before starting, the steps of:
and obtaining a hard decision input sequence z ═ z1, z2, … … and zi, and obtaining a check matrix for coding.
3. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm of claim 2, wherein the likelihood ratio information of the FLASH channel in the step S1 is expressed as:
P0＝{p1，p2，……，pi}
P1＝1-P0
here, P0 represents the probability that each bit is 0, and P1 represents the probability that each bit is 1.
4. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm of claim 3, wherein the step S2 specifically comprises the following sub-steps:
s2-1, calculating an initial check node matrix according to the channel likelihood ratio and the check matrix in the step S1;
and S2-2, updating the check node matrix by adopting a sum-product decoding algorithm according to the variable node matrix updated in the S3.
5. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm of claim 4, wherein the calculation formula of the initial check node matrix in the step S2-1 is:
Figure FDA0002709636610000021
Rij 1＝1-Rij 0
the update formula of the check node matrix in the step S2-2 is as follows:
Figure FDA0002709636610000022
Rij 1＝1-Rij 0
wherein R isij 0The conditional probability that the ith check equation is satisfied under the condition that the jth information bit is 0 is represented; rij 1The conditional probability that the ith check equation is satisfied under the condition that the jth information bit is 1 is shown; n (i) a local symbol information set representing a parity z constraint; qji 1The probability that the jth information bit is 1 under the condition that other check nodes except the ith check node provide information is shown; n (i) \\ j indicates that n (i) does not contain a subset of j; hjA column vector of the check matrix is represented.
6. The joint decoding method for accelerating soft decoding based on bit flipping algorithm of claim 5, wherein the check matrix in step S3 is represented as:
Figure FDA0002709636610000023
Figure FDA0002709636610000024
wherein Q isji 0The probability that the jth information bit is 0 under the condition that other check nodes except the ith check node provide information is represented; pj represents the probability that the jth information bit in P0 is 0, and M (j) represents the check set of the check nodes; m (j) \\ i indicates that a subset of M (j) does not contain i.
7. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm of claim 6, wherein the updating the hard decision input sequence according to the information reliability indicator in step S3 specifically comprises:
setting an information reliability index of
Figure FDA0002709636610000031
Figure FDA0002709636610000032
Figure FDA0002709636610000033
Wherein x represents an information reliability index, Qj 0Represents Qji 0The sum of the row vectors; qj 1Represents Qji 1The sum of the row vectors;
judging whether the value of the information reliability index x is less than 1; if yes, updating the hard decision input sequence zi to 1; otherwise, updating the hard decision input sequence zi to 0.
8. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm of claim 7, wherein the calculation formula of the degree of dispersion of the likelihood ratio difference of the variable matrix in the step S4 is:
Figure FDA0002709636610000034
where M denotes the number of rows of the check matrix.
9. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm of claim 8, wherein the step S5 specifically comprises the following sub-steps:
s5-1, calculating syndrome vector according to the updated hard decision input sequence and check matrix by using bit flipping algorithm, and expressing as
s＝z*HT
Wherein H represents a check matrix;
s5-2, calculating a turning function expressed as
Figure FDA0002709636610000041
Wherein fi represents the number of the ith variable node which does not meet the check, hj，iRepresenting a check matrix row vector;
turning over the hard decision input sequence which does not meet the check number and has the most number;
s5-3, calculating a new syndrome vector according to the reversed hard decision input sequence and the check matrix;
s5-4, judging whether the new syndrome vector is equal to 0; if yes, stopping decoding and outputting a decoding result; otherwise, the process returns to step S5-2.
10. A joint decoding system applying the method of any of claims 1 to 9, comprising:
the sum-product decoding algorithm core is used for soft decoding in the early stage of decoding and comprises a check node processing module, a variable node processing module, an interactive information storage module and a discrete degree detection module; controlling each module to enable alternately through a state machine;
a variable node processing module for updating the variable node matrix and enabling the variable node matrix Q for the first timeji 0、Qji 1Carrying out initialization; when not firstly enabled, the node matrix R is checkedij 0、Rij 1Iteratively updating variable node matrix Qji 0、Qji 1Meanwhile, the updated result is operated to obtain an information reliability index x, and judgment is carried outOutputting a result;
a check node processing module for checking the check node matrix Rij 0、Rij 1Updating, and checking the node processing module to pass Qji 0、Qji 1Matrix iterative update Rij 0、Rij 1A matrix;
a cross information storage module for storing real matrix data Qji 0、Qji 1、Rij 0、Rij 1Receiving data from the variable node processing module and the check node processing module, and updating the matrix data;
the discrete degree detection module is used for detecting the likelihood ratio discrete degree of the variable node matrix, converting a decoding algorithm according to the discrete degree and outputting an effective conversion enabling signal;
the bit flipping algorithm core is used for carrying out hard decoding at the later decoding stage and comprises a flipping function operation module and a most value searching module;
the overturning function operation module is used for performing column-by-column operation on an overturning function fi;
the maximum value searching module is used for searching the maximum value in the turnover function, accumulating the fi line by adopting an accumulator, comparing the accumulated fi value with the maximum value of the previous round in the maximum value register, updating the maximum value register and outputting the column address and the maximum value of the maximum value register;
the channel likelihood ratio/data information storage module is used for acquiring FLASH channel likelihood ratio information and quantized data subjected to hard decision under the condition of decoding the coded data and storing the FLASH channel likelihood ratio information and the quantized data into an SRAM (static random access memory); simultaneously acquiring effective address information, enabling signals, input decision sequences and likelihood ratio information, and outputting decoded sequences;
the check matrix module is used for storing the information of the check matrix H;
the state machine control module is used for controlling the switching of the decoding algorithm, selecting a decoding mode through the conversion enabling of the identification sum product decoding algorithm core and starting an enabling signal of the corresponding decoding core; a counter module is arranged in the decoding device to control the enabling times so as to control the decoding iteration times, when the counter reaches the maximum iteration times, the decoding is stopped, the output enabling and the counter are controlled by the stopping enabling, and when the stopping enabling is effective, the whole decoding process is ended;
a decoding termination checking module for detecting whether the two algorithms have met termination conditions, i.e. syndrome vector s is equal to zero vector; if the vector is zero, sending out termination enable, and stopping iteration; otherwise, the iteration is continued.
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