CN112350738B - Combined decoding method and system for accelerating soft decoding based on bit flipping algorithm - Google Patents

Combined decoding method and system for accelerating soft decoding based on bit flipping algorithm Download PDF

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CN112350738B
CN112350738B CN202011051282.XA CN202011051282A CN112350738B CN 112350738 B CN112350738 B CN 112350738B CN 202011051282 A CN202011051282 A CN 202011051282A CN 112350738 B CN112350738 B CN 112350738B
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冯全源
刘家明
程简
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Southwest Jiaotong University
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    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding
    • H03M13/2951—Iterative decoding using iteration stopping criteria
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1108—Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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    • H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
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Abstract

The invention discloses a joint decoding method and a system for accelerating soft decoding based on a bit flipping algorithm, wherein the method comprises the steps of obtaining likelihood ratio and check matrix information of a FLASH channel, adopting a sum-product algorithm to update a variable matrix, adopting the sum-product algorithm to update the check matrix, and judging whether the discrete degree of the likelihood ratio difference value of the variable matrix is larger than a preset threshold value; if yes, the soft decoding is terminated in advance, otherwise, the variable matrix and the check matrix are updated again, the bit inversion algorithm is adopted to carry out bit inversion iteration on the updated hard decision input sequence, and a decoding result is output. The soft decoding module is terminated in advance, the decoding process is advanced to the range of hard decoding realization, and then the hard decoding is used for iterative decoding, so that the iterative delay of the soft decoding can be further reduced, and the overall decoding time is further reduced; the invention effectively reduces the delay of soft decoding under the condition of keeping the original chip area not to be greatly increased.

Description

Combined decoding method and system for accelerating soft decoding based on bit flipping algorithm
Technical Field
The invention relates to the technical field of FLASH controller decoding, in particular to a joint decoding method and system for accelerating soft decoding based on a bit flipping algorithm.
Background
With the continuous progress of process nodes, the chip size of FLASH is continuously reduced, the influence of interference noise among FLASH units is more serious, the reliability problem of FLASH is more and more required to be focused, and a series of error correction methods such as BCH codes, RS codes and the like are also emerging on the market to correct the transmission accuracy, but due to limited error correction capability, LDPC codes are gradually eliminated at present, and due to better error correction characteristics, the LDPC codes are more in line with the error correction requirements of the FLASH memory.
As the error correction demand further increases, the hard decoding method represented by the bit flip decision method is gradually replaced by some soft decoding algorithms, and the LLR acquisition method based on threshold voltage sensing is also a way for the flash memory controller to mainly acquire the LLR information.
However, because PPA index factors are often required to be considered in the design of the flash memory control chip, the soft decoding circuit often has higher decoding delay compared with the hard decoding circuit, and the overall performance is greatly affected. How to reduce the delay of soft coding while performing soft coding is currently the main issue key.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a joint decoding method and a system for accelerating soft decoding based on a bit flipping algorithm.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
in a first aspect, the present invention provides a joint decoding method for accelerating soft decoding based on a bit flipping algorithm, including the following steps:
s1, obtaining likelihood ratio and check matrix information of a FLASH channel;
s2, updating the check node matrix by adopting a sum-product algorithm;
s3, updating the variable node matrix by adopting a sum-product algorithm according to the updated check node matrix in the step S2, and updating the hard decision input sequence according to the information reliability index;
s4, judging whether the degree of dispersion of the likelihood ratio difference value of the variable node matrix is larger than a preset threshold value or not; if yes, the soft decoding is terminated in advance, and step S5 is carried out; otherwise, returning to the step S2;
s5, performing bit-flipping iteration on the updated hard-decision input sequence by adopting a bit-flipping algorithm, and outputting a decoding result.
The beneficial effect of this scheme is: aiming at the problem that the conventional LDPC soft decoding algorithm has larger decoding delay, the method for assisting the soft decoding algorithm to accelerate decoding iteration based on the bit flipping algorithm is adopted, the decoding process is advanced to a hard decoding realization range by stopping the soft decoding module in advance, and then the hard decoding is used for iterative decoding, and the decoding time of the hard decoding is far less than that of the soft decoding, so that the iteration delay of the soft decoding can be further reduced, and the overall decoding time is further reduced; the invention effectively reduces the delay of soft decoding under the condition of keeping the original chip area not to be greatly increased.
Further, before the step S1 starts, the method further includes the steps of:
a hard decision input sequence z= { z1, z2, &..once., zi }, and a check matrix is acquired for encoding.
The beneficial effect of this further scheme is: the input sequence is efficiently encoded so that the entire sequence can be efficiently decoded and corrected by employing the LDPC decoding method.
Further, the likelihood ratio information of the FLASH channel in the step S1 is expressed as:
P0＝{p1，p2，……，pi}
P1＝1-P0
where P0 represents the probability that each bit is 0, and P1 represents the probability that each bit is 1.
The beneficial effect of this further scheme is: the likelihood ratio information is obtained to estimate the situation that the channel has error codes and the possibility that each variable node has error codes, so that the node with higher error probability is given greater weight, and the decoding accuracy is effectively improved.
Further, the step S2 specifically includes the following sub-steps:
s2-1, calculating an initial check node matrix according to the channel likelihood ratio and the check matrix in the step S1;
s2-2, updating the check node matrix by adopting a sum-product decoding algorithm according to the variable node matrix updated in the step S3.
The beneficial effect of this further scheme is:
further, the calculation formula of the initial check node matrix in the step S2-1 is as follows:
Figure BDA0002709636620000031
R ij 1 ＝1-R ij 0
the update formula of the check node matrix in the step S2-2 is as follows:
Figure BDA0002709636620000032
R ij 1 ＝1-R ij 0
wherein R is ij 0 Representing conditional probability that the ith check equation satisfies in the case where the jth information bit is 0; r is R ij 1 Representing conditional probability that the ith check equation satisfies in the case where the jth information bit is 1; n (i) represents a local symbol information set that verifies the z constraint; q (Q) ji 1 Representing a probability that the jth information bit is 1 in the case that other check nodes except the ith check node provide information; n (i) \j represents a subset of N (i) that does not contain j; h j Representing the column vector of the check matrix.
The beneficial effect of this further scheme is: by calculating or updating the check node matrix, the likelihood ratio information and the variable node matrix information are effectively acquired by each check node, and by comparing the hard decision sequence z with the error probability of each node, the error probability of each variable node of the channel can be updated and corrected.
Further, the check matrix in the step S3 is expressed as:
Figure BDA0002709636620000041
Figure BDA0002709636620000042
/>
wherein Q is ji 0 Representing a probability that the jth information bit is 0 in the case that other check nodes except the ith check node provide information; pj represents the probability that the jth information bit in P0 is 0, M (j) represents the check set of the check node; m (j) \i represents a subset of M (j) that does not contain i.
The beneficial effect of this further scheme is: the probability of the variable node connected with each check node is updated by acquiring the updated check node matrix, so that the variable node connected with each check node is influenced by the check node, and the acquired probability is more accurate.
Further, in the step S3, updating the hard decision input sequence according to the information reliability index specifically includes:
setting the information reliability index as
Figure BDA0002709636620000043
Figure BDA0002709636620000044
Figure BDA0002709636620000045
Wherein x represents an information reliability index, Q j 0 Represents Q ji 0 A sum of the row vectors; q (Q) j 1 Represents Q ji 1 A sum of the row vectors;
judging whether the value of the information reliability index x is smaller than 1; if yes, updating the hard decision input sequence zi to be 1; otherwise the update hard decision input sequence zi is 0.
The beneficial effect of this further scheme is: and the probability information of all check nodes is summed, the probability condition of each variable node is quantized, and then bit information expected by the non-conforming probability in the hard decision sequence z is turned over by comparing the probability of each variable node being 0 or 1. Probability information generated by iteration is effectively utilized, so that the accuracy of the hard decision sequence z obtained after decoding is higher.
Further, the calculation formula of the discrete degree of the variable matrix likelihood ratio difference in the step S4 is as follows:
Figure BDA0002709636620000051
where M represents the number of rows of the check matrix.
The beneficial effect of this further scheme is: the invention carries out the estimation of the decoding process and the conversion of the algorithm mode according to the discrete degree of the likelihood ratio, adopts the total standard deviation to carry out statistics and calculation, adopts the single-precision floating point number of the IEEE 754 standard to carry out operation, and has higher precision.
Further, the step S5 specifically includes the following sub-steps:
s5-1, calculating an accompanying sub-vector according to the updated hard decision input sequence and the check matrix by adopting a bit flipping algorithm, and representing the sub-vector as
s＝z*H T
Wherein H represents a check matrix;
s5-2, calculating a roll-over function expressed as
Figure BDA0002709636620000052
Wherein fi represents the number of unsatisfied check of the ith variable node, h j，i Representing a check matrix row vector;
turning over the hard decision input sequence which does not meet the maximum number of checks;
s5-3, calculating a new accompanying subvector according to the turned hard decision input sequence and the check matrix;
s5-4, judging whether the new accompanying subvector is equal to 0; if yes, stopping decoding and outputting a decoding result; otherwise, returning to the step S5-2.
The beneficial effect of this further scheme is: the invention adopts a bit-flipping algorithm mode to replace the decoding process of the latter half of the soft decoding algorithm to terminate in advance, so that the overall decoding delay is reduced, and the power consumption of the whole chip in decoding is reduced; and the correctness of the hard decision sequence z can be effectively detected by the accompanying sub-vector s and the control iteration is finished, and when s is an all-zero vector, the bit flipping iteration is finished.
In a second aspect, the present invention further provides a decoding system applying the above method, including:
the product decoding algorithm core is used for performing soft decoding in the early stage of decoding and comprises a check node processing module, a variable node processing module, an interaction information storage module and a discrete degree detection module; controlling each module to be enabled alternately through a state machine;
the variable node processing module is used for updating the variable node matrix and when the variable node matrix is enabled for the first time, updating the variable node matrix Q ji 0 、Q ji 1 Initializing; when not enabled for the first time, through the check node matrix R ij 0 、R ij 1 Iterative update variable node matrix Q ji 0 、Q ji 1 Meanwhile, calculating the updated result to obtain an information reliability index x, and judging and outputting the result;
the check node processing module is used for checking the check node matrix R ij 0 、R ij 1 Updating, checking the node processing module through Q ji 0 、Q ji 1 Matrix iterative update R ij 0 、R ij 1 A matrix;
a cross information storage module for storing real matrix data Q ji 0 、Q ji 1 、R ij 0 、R ij 1 Receiving data from the variable node processing module and the check node processing module, and updating the matrix data;
the discrete degree detection module is used for detecting the discrete degree of the likelihood ratio of the variable node matrix, converting a decoding algorithm according to the discrete degree and outputting an effective conversion enabling signal;
the bit flipping algorithm core is used for performing hard decoding in the later decoding stage and comprises a flipping function operation module and a maximum value searching module;
the turnover function operation module is used for performing column-by-column operation on the turnover function fi;
the maximum value searching module is used for searching the maximum value in the turnover function, accumulating fi row by adopting an accumulator, comparing the fi with the maximum value of the previous round in the maximum value register, updating the maximum value register, and outputting the column address and the maximum value of the maximum value register;
the channel likelihood ratio/data information storage module is used for acquiring FLASH channel likelihood ratio information and quantized data subjected to hard decision under the condition that the coded data are decoded, and storing the FLASH channel likelihood ratio information and the quantized data into the SRAM; simultaneously acquiring effective address information, an enabling signal, an input decision sequence and likelihood ratio information, and outputting a decoded sequence;
the check matrix module is used for storing the information of the check matrix H;
the state machine control module is used for controlling the switching of the decoding algorithm, selecting a decoding mode by identifying and integrating the conversion enabling of the decoding algorithm cores, and starting an enabling signal of the corresponding decoding core; a counter module is arranged in the decoder to control the enabled times so as to control the decoding iteration times, when the counter reaches the maximum iteration times, the decoding is stopped, the output enabling and the counter are controlled by the stopping enabling, and when the stopping enabling is effective, the whole decoding process is ended;
the decoding termination checking module is used for detecting whether two algorithms meet the termination condition, namely the companion sub-vector s is equal to the zero vector; if the zero vector is the zero vector, sending out termination enabling, and stopping iteration; otherwise, iteration is continued.
The beneficial effect of this scheme is: the two-stage combined decoding method based on the bit-flipping algorithm for accelerating the soft decoding is designed at a circuit stage, and the characteristics of high parallelism and assembly line of the circuit are utilized, so that the whole algorithm has wider application under the circuit architecture; meanwhile, a state machine is adopted to control the decoding flow and switch the decoding method, and an enabling signal is used to control the decoding core, so that the method has higher replaceability and robustness.
Drawings
FIG. 1 is a flow chart of a joint decoding method for accelerating soft decoding based on a bit flipping algorithm;
FIG. 2 is a schematic diagram of a bit flipping iteration process in embodiment 1 of the present invention;
FIG. 3 is a schematic diagram of a joint decoding system for accelerating soft decoding based on a bit flipping algorithm according to the present invention;
fig. 4 is a schematic diagram of the internal architecture of a parallel packet system with a bit flipping algorithm core in the joint decoding system according to the present invention.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
Example 1
As shown in fig. 1, the embodiment of the present invention provides a joint decoding method for accelerating soft decoding based on a bit flipping algorithm, which includes steps S1 to S5 as follows:
s1, obtaining likelihood ratio and check matrix information of a FLASH channel;
in this embodiment, before decoding, the present invention obtains a hard decision input sequence z= { z1, z2, &..once., zi }, and obtains a check matrix H for encoding.
Assuming that the number of symbols is i, likelihood ratio (LLR) information of the FLASH channel is obtained, expressed as:
P0＝{p1，p2，……，pi}
P1＝1-P0
where P0 represents the probability that each bit is 0, and P1 represents the probability that each bit is 1.
S2, updating the check node matrix by adopting a sum-product algorithm;
in this embodiment, the step S2 specifically includes the following sub-steps:
s2-1, calculating an initial check node matrix according to the channel likelihood ratio and the check matrix in the step S1;
step S2 is carried out for the first time, the initial check node matrix is calculated according to the channel likelihood ratio pi and the check matrix H in the step S1, and the calculation formula is as follows:
Figure BDA0002709636620000091
R ij 1 ＝1-R ij 0
s2-2, updating the check node matrix by adopting a sum-product decoding algorithm according to the variable node matrix updated in the step S3.
Step S2 is not carried out for the first time, the invention adopts a sum-product decoding algorithm to update the check node matrix according to the content of the variable node matrix updated in the step S3, and the update formula is as follows:
Figure BDA0002709636620000092
R ij 1 ＝1-R ij 0
wherein R is ij 0 Representing conditional probability that the ith check equation satisfies in the case where the jth information bit is 0; r is R ij 1 Representing conditional probability that the ith check equation satisfies in the case where the jth information bit is 1; n (i) represents a local symbol information set that verifies the z constraint; q (Q) ji 1 Representing a probability that the jth information bit is 1 in the case that other check nodes except the ith check node provide information; n (i) \j represents a subset of N (i) that does not contain j; h j Representing the column vector of the check matrix.
S3, updating the variable node matrix by adopting a sum-product algorithm according to the updated check node matrix in the step S2, and updating the hard decision input sequence according to the information reliability index;
in this embodiment, the present invention is based on the updated check node matrix R in step S2 ij 0 And R is ij 1 Updating variable node matrix Q by adopting sum-product algorithm ji 0 And Q ji 1 Expressed as:
Figure BDA0002709636620000101
Figure BDA0002709636620000102
wherein Q is ji 0 Representing a variable node matrix, and representing the probability that the j-th information bit is 0 under the condition that other check nodes except the i-th check node provide information; q (Q) ji 1 Representing a variable node matrix, and representing the probability of 1 of the j-th information bit under the condition that other check nodes except the i-th check node provide information; pj represents the probability that the jth bit in P0 is 0, M (j) represents the check set of the check node; m (j) \i represents a subset of M (j) that does not contain i.
Simultaneously setting the information reliability index x as
Figure BDA0002709636620000103
Figure BDA0002709636620000104
Figure BDA0002709636620000105
Wherein x represents an information reliability index, Q j 0 Represents Q ji 0 A sum of the row vectors; q (Q) j 1 Represents Q ji 1 A sum of the row vectors;
and then, according to the information reliability index x as a judgment condition, updating the hard judgment input sequence z, which is expressed as:
Figure BDA0002709636620000111
namely judging whether the value of the information reliability index x is smaller than 1; if yes, updating the hard decision input sequence zi to be 1; otherwise the update hard decision input sequence zi is 0.
S4, judging whether the degree of dispersion of the likelihood ratio difference value of the variable node matrix is larger than a preset threshold value or not; if yes, the soft decoding is terminated in advance, and step S5 is carried out; otherwise, returning to the step S2;
in this embodiment, in the process of performing update iteration of the variable node matrix and the check node matrix, the variable node matrix Q is calculated in each iteration ji 0 And Q ji 1 Judging whether the discrete degree L of the likelihood ratio difference value of the variable node matrix is larger than a preset threshold value, wherein the calculation formula of the discrete degree L of the likelihood ratio difference value of the variable node matrix is as follows:
Figure BDA0002709636620000112
wherein M represents the number of rows of the check matrix; the preset threshold is set to 0.4765.
When the discrete degree L of the variable node matrix likelihood ratio difference value is larger than 0.4765, the soft decoding is terminated in advance, and step S5 is carried out; otherwise, returning to the step S2-2.
S5, performing bit-flipping iteration on the updated hard-decision input sequence by adopting a bit-flipping algorithm, and outputting a decoding result.
In this embodiment, as shown in fig. 2, step S5 specifically includes the following sub-steps:
s5-1, calculating an accompanying sub-vector S according to the updated hard decision input sequence z and the check matrix H by adopting a bit flipping algorithm, and representing as
s＝z*H T
S5-2, calculating a turnover function fi, expressed as
Figure BDA0002709636620000121
Wherein fi represents the number of unsatisfied check of the ith variable node, h j，i Representing a check matrix row vector;
turning over the hard decision input sequence which does not meet the most verification number (i.e. the maximum value of fi);
s5-3, calculating a new accompanying sub-vector S according to the turned hard decision input sequence and the check matrix;
s5-4, judging whether the new accompanying sub-vector S is equal to 0; if yes, stopping decoding and outputting a decoding result; otherwise, returning to the step S5-2.
Example 2
The embodiment of the invention further provides a decoding system applying the method based on the soft decoding method, as shown in fig. 3 and 4, comprising:
the product decoding algorithm core is used for performing soft decoding in the early stage of decoding and comprises a check node processing module, a variable node processing module, an interaction information storage module and a discrete degree detection module; controlling each module to be enabled alternately through a state machine;
the variable node processing module is used for updating the variable node matrix and when the variable node matrix is enabled for the first time, updating the variable node matrix Q ji 0 、Q ji 1 Initializing; when not enabled for the first time, through the check node matrix R ij 0 、R ij 1 Iterative update variable node matrix Q ji 0 、Q ji 1 Meanwhile, calculating the updated result to obtain an information reliability index x, and judging and outputting the result;
the check node processing module is used for checking the check node matrix R ij 0 、R ij 1 Updating and checking node processing moduleBlock pass Q ji 0 、Q ji 1 Matrix iterative update R ij 0 、R ij 1 A matrix;
a cross information storage module for storing 4 groups of real matrix data Q ji 0 、Q ji 1 、R ij 0 、R ij 1 Receiving data from the variable node processing module and the check node processing module, and updating the matrix data;
the discrete degree detection module is used for detecting the discrete degree of the likelihood ratio of the variable node matrix, converting a decoding algorithm according to the discrete degree and outputting an effective conversion enabling signal;
the bit flipping algorithm core is used for performing hard decoding in the later decoding stage and comprises a flipping function operation module and a maximum value searching module;
the turnover function operation module is used for calculating a turnover function F, adopts 8 groups of parallel operation frameworks, effectively reduces decoding delay and improves decoding efficiency; due to the characteristic of quasi-cyclic H matrix, the row vector H of the check matrix i，j Through the cyclic shift module, the column-by-column operation of the turnover function fi can be realized;
the maximum value searching module is used for searching the maximum value in the turnover function, accumulating fi row by adopting an accumulator, comparing the fi with the maximum value of the previous round in the maximum value register, updating the maximum value register, and outputting the column address and the maximum value of the maximum value register;
the channel likelihood ratio/data information storage module is used for acquiring FLASH channel likelihood ratio information and quantized data subjected to hard decision under the condition that the coded data are decoded, and storing the FLASH channel likelihood ratio information and the quantized data into the SRAM; simultaneously acquiring effective address information, an enabling signal, an input decision sequence and likelihood ratio information, and outputting a decoded sequence;
the check matrix module is used for storing the information of the check matrix H;
the state machine control module is used for controlling the switching of the decoding algorithm, selecting a decoding mode by identifying and integrating the conversion enabling of the decoding algorithm cores, and starting an enabling signal of the corresponding decoding core; a counter module is arranged in the decoder to control the enabled times so as to control the decoding iteration times, when the counter reaches the maximum iteration times, the decoding is stopped, the output enabling and the counter are controlled by the stopping enabling, and when the stopping enabling is effective, the whole decoding process is ended;
the decoding termination checking module is used for detecting whether two algorithms meet the termination condition, namely the companion sub-vector s is equal to the zero vector; if the zero vector is the zero vector, sending out termination enabling, and stopping iteration; otherwise, iteration is continued.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The principles and embodiments of the present invention have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.

Claims (8)

1. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm is characterized by comprising the following steps:
s1, obtaining likelihood ratio and check matrix information of a FLASH channel;
s2, updating the check node matrix by adopting a sum-product algorithm;
s3, updating the variable node matrix by adopting a sum-product algorithm according to the updated check node matrix in the step S2, and updating the hard decision input sequence according to the information reliability index; wherein updating the hard decision input sequence according to the information reliability index specifically comprises:
setting the information reliability index as
Figure QLYQS_1
Figure QLYQS_2
Figure QLYQS_3
Wherein x represents an information reliability index, Q j 0 Represents Q ji 0 A sum of the row vectors; q (Q) j 1 Represents Q ji 1 The sum of the row vectors, pj represents the probability that the jth information bit in P0 is 0, P0 represents the probability that each bit is 0, R ij 0 Representing the conditional probability that the ith check equation satisfies, R, in the case where the jth information bit is 0 ij 1 Representing the conditional probability that the ith check equation satisfies in the case where the jth information bit is 1, M (j) represents the check set of check nodes, Q ji 0 Representing the probability that the jth information bit is 0 in the case that other check nodes except the ith check node provide information, Q ji 1 Representing a probability that the jth information bit is 1 in the case that other check nodes except the ith check node provide information;
judging whether the value of the information reliability index x is smaller than 1; if yes, updating the hard decision input sequence zi to be 1; otherwise, updating the hard decision input sequence zi to 0;
s4, judging whether the degree of dispersion of the likelihood ratio difference value of the variable node matrix is larger than a preset threshold value or not; if yes, the soft decoding is terminated in advance, and step S5 is carried out; otherwise, returning to the step S2; the calculation formula of the discrete degree of the variable matrix likelihood ratio difference value is as follows:
Figure QLYQS_4
wherein M represents the number of rows of the check matrix;
s5, performing bit-flipping iteration on the updated hard-decision input sequence by adopting a bit-flipping algorithm, and outputting a decoding result.
2. The joint decoding method for accelerating soft decoding based on a bit flipping algorithm according to claim 1, wherein the step S1 further comprises the steps of:
a hard decision input sequence z= { z1, z2, &..once., zi }, and a check matrix is acquired for encoding.
3. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm according to claim 2, wherein the likelihood ratio information of the FLASH channel in step S1 is expressed as:
P0＝{p1，p2，……，pi}
P1＝1-P0
where P0 represents the probability that each bit is 0, and P1 represents the probability that each bit is 1.
4. The joint decoding method for accelerating soft decoding based on bit flipping algorithm according to claim 3, wherein said step S2 specifically comprises the following sub-steps:
s2-1, calculating an initial check node matrix according to the channel likelihood ratio and the check matrix in the step S1;
s2-2, updating the check node matrix by adopting a sum-product decoding algorithm according to the variable node matrix updated in the step S3.
5. The joint decoding method for accelerating soft decoding based on a bit flipping algorithm according to claim 4, wherein the calculation formula of the initial check node matrix in step S2-1 is:
Figure QLYQS_5
R ij 1 ＝1-R ij 0
the update formula of the check node matrix in the step S2-2 is as follows:
Figure QLYQS_6
R ij 1 ＝1-R ij 0
wherein R is ij 0 Representing conditional probability that the ith check equation satisfies in the case where the jth information bit is 0; r is R ij 1 Representing conditional probability that the ith check equation satisfies in the case where the jth information bit is 1; n (i) represents a local symbol information set that verifies the z constraint; q (Q) ji 1 Representing a probability that the jth information bit is 1 in the case that other check nodes except the ith check node provide information; n (i) \j represents a subset of N (i) that does not contain j; h j Representing the column vector of the check matrix.
6. The joint decoding method for accelerating soft decoding based on a bit flipping algorithm according to claim 5, wherein the check matrix in step S3 is expressed as:
Figure QLYQS_7
Figure QLYQS_8
wherein Q is ji 0 Representing a probability that the jth information bit is 0 in the case that other check nodes except the ith check node provide information; pj represents the probability that the jth information bit in P0 is 0, M (j) represents the check set of the check node; m (j) \i represents a subset of M (j) that does not contain i.
7. The joint decoding method for accelerating soft decoding based on the bit flipping algorithm as claimed in claim 6, wherein said step S5 specifically comprises the following sub-steps:
s5-1, calculating an accompanying sub-vector according to the updated hard decision input sequence and the check matrix by adopting a bit flipping algorithm, and representing the sub-vector as
s＝z*H T
Wherein H represents a check matrix;
s5-2, calculating a roll-over function expressed as
Figure QLYQS_9
Wherein fi represents the number of unsatisfied check of the ith variable node, h j，i Representing a check matrix row vector;
turning over the hard decision input sequence which does not meet the maximum number of checks;
s5-3, calculating a new accompanying subvector according to the turned hard decision input sequence and the check matrix;
s5-4, judging whether the new accompanying subvector is equal to 0; if yes, stopping decoding and outputting a decoding result; otherwise, returning to the step S5-2.
8. A joint decoding system employing the method of claim 7, comprising:
the product decoding algorithm core is used for performing soft decoding in the early stage of decoding and comprises a check node processing module, a variable node processing module, an interaction information storage module and a discrete degree detection module; controlling each module to be enabled alternately through a state machine;
the variable node processing module is used for updating the variable node matrix and when the variable node matrix is enabled for the first time, updating the variable node matrix Q ji 0 、Q ji 1 Initializing; when not enabled for the first time, through the check node matrix R ij 0 、R ij 1 Iterative update variable node matrix Q ji 0 、Q ji 1 Meanwhile, calculating the updated result to obtain an information reliability index x, and judging and outputting the result;
the check node processing module is used for checking the check node matrix R ij 0 、R ij 1 Updating, checking the node processing module through Q ji 0 、Q ji 1 Matrix iterative update R ij 0 、R ij 1 A matrix;
a cross information storage module for storing real matrix data Q ji 0 、Q ji 1 、R ij 0 、R ij 1 Receiving data from the variable node processing module and the check node processing module, and updating the matrix data;
the discrete degree detection module is used for detecting the discrete degree of the likelihood ratio of the variable node matrix, converting a decoding algorithm according to the discrete degree and outputting an effective conversion enabling signal;
the bit flipping algorithm core is used for performing hard decoding in the later decoding stage and comprises a flipping function operation module and a maximum value searching module;
the turnover function operation module is used for performing column-by-column operation on the turnover function fi;
the maximum value searching module is used for searching the maximum value in the turnover function, accumulating fi row by adopting an accumulator, comparing the fi with the maximum value of the previous round in the maximum value register, updating the maximum value register, and outputting the column address and the maximum value of the maximum value register;
the channel likelihood ratio/data information storage module is used for acquiring FLASH channel likelihood ratio information and quantized data subjected to hard decision under the condition that the coded data are decoded, and storing the FLASH channel likelihood ratio information and the quantized data into the SRAM; simultaneously acquiring effective address information, an enabling signal, an input decision sequence and likelihood ratio information, and outputting a decoded sequence;
the check matrix module is used for storing the information of the check matrix H;
the state machine control module is used for controlling the switching of the decoding algorithm, selecting a decoding mode by identifying and integrating the conversion enabling of the decoding algorithm cores, and starting an enabling signal of the corresponding decoding core; a counter module is arranged in the decoder to control the enabled times so as to control the decoding iteration times, when the counter reaches the maximum iteration times, the decoding is stopped, the output enabling and the counter are controlled by the stopping enabling, and when the stopping enabling is effective, the whole decoding process is ended;
the decoding termination checking module is used for detecting whether two algorithms meet the termination condition, namely the companion sub-vector s is equal to the zero vector; if the zero vector is the zero vector, sending out termination enabling, and stopping iteration; otherwise, iteration is continued.
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