CN112350574B - Digital fixed on-time controller suitable for DC converter - Google Patents
Digital fixed on-time controller suitable for DC converter Download PDFInfo
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- CN112350574B CN112350574B CN201910722287.1A CN201910722287A CN112350574B CN 112350574 B CN112350574 B CN 112350574B CN 201910722287 A CN201910722287 A CN 201910722287A CN 112350574 B CN112350574 B CN 112350574B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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Abstract
A digital fixed on-time controller suitable for a DC converter comprises a current sensing circuit, a voltage sensing circuit and a control circuit, wherein the current sensing circuit senses the stored energy of the DC converter to generate a sensing voltage; a half-amplitude detector that detects a peak-to-peak value of the sensing voltage to thereby generate a half-amplitude voltage; a DC voltage detector, in the energy storage circuit providing stored energy, detecting a DC voltage across the effective series resistor, thereby generating a DC voltage; an arithmetic device which adds the sensing voltage and the half-amplitude voltage and subtracts the direct-current voltage and a preset reference signal; and a pulse width modulation generator for generating a switching control signal according to the result of the arithmetic device. The technical scheme provided by the invention can effectively improve the output voltage offset.
Description
Technical Field
The present invention relates to a direct current (DC-to-DC) converter, and more particularly, to a DC converter with offset cancellation.
Background
A power converter (power converter) is an electronic circuit that converts electrical energy from one form to another. A direct current (DC-to-DC) converter is one type of power converter for converting a DC source from one voltage level to another. In a dc converter, an inductor is usually disposed between a switching circuit and an output node to store energy.
The dc converter usually uses an analog current sensing circuit to sense the inductor current, so as to control the switching of the switching circuit. For a constant on-time (COT) dc converter, a ripple-based analog control is used to compare a sensed inductor current with a reference voltage, so as to generate a control signal for controlling the switching of a switching circuit. However, this mechanism generates an output voltage offset error, thereby reducing the regulation performance of the dc converter.
Therefore, it is desirable to provide a novel dc converter to improve the output voltage offset.
Disclosure of Invention
In view of the foregoing, an objective of the embodiments of the present invention is to provide a direct current (DC-to-DC) converter with output voltage offset cancellation, and particularly a digital fixed on-time controller suitable for a DC converter, which can effectively cancel the output voltage offset.
According to an embodiment of the present invention, a digital fixed on-time controller for a dc converter includes a current sensing circuit, a half-amplitude detector, a dc voltage detector, an arithmetic device, and a pwm generator. The current sensing circuit senses the stored energy of the DC converter to generate a sensing voltage. The half-amplitude detector detects a peak-to-peak half of the sensing voltage, thereby generating a half-amplitude voltage. The dc voltage detector detects a dc voltage across the effective series resistor in the energy storage circuit providing stored energy, thereby generating a dc voltage. The arithmetic device adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and a preset reference signal. The PWM generator generates a switching control signal according to the result of the arithmetic device.
Preferably, the half-amplitude detector comprises: a rising edge triggered latch circuit, triggered at the rising edge of the switching control signal or digital switching voltage to latch the sensing voltage, thereby generating a minimum value; a falling edge trigger latch circuit which is triggered to latch the sensing voltage at the falling edge of the switching control signal or the digital switching voltage, thereby generating a maximum value; an adder for subtracting the minimum value from the maximum value, thereby generating a peak-to-peak value; and a divide-by-two device for dividing the peak-to-peak value by 2, thereby generating the half-amplitude voltage.
Preferably, the dc voltage detector comprises: a delay element for delaying the switching control signal or the digital switching voltage by half a turn-on period to obtain a delayed switching control signal or a digital switching voltage; a rising edge triggered latch circuit triggered at a rising edge of the delayed switching control signal or digital switching voltage to latch the sensing voltage, thereby generating an intermediate value; and an adder for subtracting the digital output voltage of the DC converter from the intermediate value, thereby generating the DC voltage.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; and a first arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage, thereby generating a first signal which is fed to a first input node of the comparator; the predetermined reference signal is used as a second signal, which is fed to the second input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; and a second arithmetic means for adding the predetermined reference signal and the DC voltage and subtracting the half-amplitude voltage, thereby generating a second signal which is fed to a second input node of the comparator; wherein the sensing voltage is provided as a first signal which is fed to a first input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; a first arithmetic means for adding the sensing voltage and the half-amplitude voltage, thereby generating a first signal which is fed to a first input node of the comparator; and a second arithmetic device for adding the predetermined reference signal and the DC voltage, thereby generating a second signal which is fed to a second input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; a first arithmetic device for subtracting the dc voltage from the sensed voltage, thereby generating a first signal, which is fed to a first input node of the comparator; and a second arithmetic device for subtracting the half-amplitude voltage from the predetermined reference signal, thereby generating a second signal, which is fed to a second input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
According to an embodiment of the present invention, a digital fixed on-time controller for a dc converter includes: a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage; a valley detector for detecting a valley value of the sensing voltage, thereby generating a valley voltage; a comparator having a first input node and a second input node; a first arithmetic device for adding the sensing voltage and the digital output voltage of the dc converter, thereby generating a first signal which is fed to a first input node of the comparator; a second arithmetic device for adding the valley voltage and a predetermined reference signal, thereby generating a second signal, which is fed to a second input node of the comparator; and a PWM generator for generating a switching control signal according to the comparison result of the comparator.
Preferably, the valley detector comprises: the rising edge triggers the latch circuit, which is triggered to latch the sensing voltage at the rising edge of the switching control signal or digital switching voltage, thereby generating the valley voltage.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
By the technical scheme, the invention at least has the following advantages: the digital fixed conduction time controller applicable to the direct current converter can effectively offset the output voltage offset.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1A shows a circuit diagram of a dc converter with output voltage offset cancellation.
Fig. 1B shows a circuit diagram of a dc converter with output voltage offset cancellation.
Fig. 2A shows a block diagram of a digital fixed on time (COT) controller according to a first embodiment of the present invention.
Fig. 2B shows a detailed block diagram of the valley detector of fig. 2A.
Fig. 2C shows a block diagram of a digital fixed on-time (COT) controller according to a first alternative embodiment of the present invention.
Fig. 3A shows a block diagram of a digital fixed on time (COT) controller according to a second embodiment of the present invention.
Fig. 3B shows a detailed block diagram of the half-amplitude detector of fig. 3A.
Fig. 3C shows a detailed block diagram of the dc voltage detector of fig. 3A.
Fig. 3D shows a block diagram of a digital fixed on time (COT) controller according to a second alternative embodiment of the present invention.
Fig. 4A shows a block diagram of a digital fixed on-time (COT) controller according to a third embodiment of the present invention.
Fig. 4B shows a block diagram of a digital fixed on-time (COT) controller according to a third alternative embodiment of the present invention.
Fig. 5A shows a block diagram of a digital fixed on time (COT) controller according to a fourth embodiment of the invention.
Fig. 5B shows a block diagram of a digital fixed on-time (COT) controller according to a fourth alternative embodiment of the present invention.
Fig. 6A shows a block diagram of a digital fixed on time (COT) controller according to a fifth embodiment of the invention.
Fig. 6B shows a block diagram of a digital fixed on-time (COT) controller according to a fifth alternative embodiment of the present invention.
[ description of main element symbols ]
100: the dc converter 200: DC converter
11: the switching circuit 111: power supply
12: energy storage circuit 13: analog-to-digital converter
13A: the first analog-to-digital converter 13B: a second analog-to-digital converter
14: the driver 15: digital fixed on-time controller
151: current sensing circuit 1511: high-pass filter
1512: low-pass filter 1513: first adder
1521: valley detector 15211: rising edge triggered latch circuit
1524: the first arithmetic device 1525: second arithmetic device
1526: half-amplitude detector 15261: rising edge triggered latch circuit
15262: falling edge triggered latch circuit 15263: adder
15264: a divide-by-two device 1527: DC voltage detector
15271: the rising edge triggered latch circuit 15272: delay element
15273: the adder 153: comparator with a comparator circuit
154: pulse width modulation generator Mp: first switching device
Mn: second switching device L: inductor
RL: effective series resistor C: capacitor with a capacitor element
RC: effective series resistor Vx: switching voltage/switching node
Vx [ n ]: digital switching voltage Vo: output voltage/output node
Vin: input voltage IL: inductive current
Vo [ n ]: digital output voltage S: switching control signal
Vref: reference signal Vvalley[n]: trough voltage
Vs [ n ]: sense voltage Vpp/2[ n ]: half amplitude voltage
Vdc [ n ]: direct voltage
Detailed Description
Fig. 1A shows a circuit diagram of a direct current (DC-TO-DC) CONVERTER 100 with output voltage offset cancellation, disclosed in U.S. application No. 16/153,467, currently U.S. patent No. 10,291,121, entitled "DC CONVERTER and digital fixed ON-TIME CONTROLLER (DC-TO-DC CONVERTER AND A DIGITAL ON-TIME CONTROLLER thermal), filed ON 5.10.2018 by the present applicant. The dc converter 100 may include a switching circuit 11 for generating a switching voltage Vx. The switching circuit 11 may include a first switching device Mp and a second switching device Mn connected in series between the power source 111 and the ground. The power supply 111 provides an input voltage Vin. The switching voltage Vx is located at a switching node Vx between the first switching device Mp and the second switching device Mn.
The dc converter 100 may include an energy storage circuit 12 that receives a switching voltage Vx to generate a regulated output voltage Vo for provision to a load. Wherein the energy storage circuit 12 may include an inductor L and an effective series resistor RL connected in series between the switching node Vx and the output node Vo; and a capacitor C and an effective series resistor RC connected in series between the output node Vo and ground.
The DC converter 100 may include an analog-to-digital converter (ADC)13 for generating an equivalent digital output voltage Vo [ n ] of the (analog) output voltage Vo. The dc converter 100 may include a driver 14 (e.g., an amplifier) that generates a driving signal to drive the switching circuit 11. The driver 14 generates a driving signal to drive the first switching device Mp, and generates an inverted driving signal to drive the second switching device Mn.
The dc converter 100 may include a digital constant on-time (DCOT) controller 15 that receives the digital output voltage Vo [ n ] to generate a switching control signal S, which is fed to the driver 14. The digital fixed on-time controller 15 generates a fixed on-time (COT) switching control signal according to the stored energy of the energy storage circuit 12 (e.g., the inductor current IL flowing through the inductor L).
Fig. 1B shows a circuit diagram of a direct current (DC-to-DC) converter 200 with output voltage offset cancellation, which is disclosed in the aforementioned U.S. patent application of the present applicant. The dc converter 200 of fig. 1B is similar to the dc converter 100 of fig. 1A, and the differences will be explained below. In FIG. 1B, the first ADC 13A generates an equivalent digital output voltage Vo [ n ] of the (analog) output voltage Vo, and the second ADC 13B generates an equivalent digital switching voltage Vx [ n ] of the (analog) switching voltage Vx. Thus, the digital fixed on-time controller 15 of the second embodiment generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in the first embodiment.
Fig. 2A shows a block diagram of a digital fixed on time (COT) controller 15 according to a first embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may comprise a first arithmetic device 1524 for adding the sensing voltage Vs [ n ] (of the current sensing circuit 151)]And a digital output voltage Vo [ n ]]Thus generating a first signal that is fed to a first input node (e.g., the positive (+) input node) of the comparator 153. The constant on-time controller 15 of the present embodiment may comprise a valley detector 1521 for detecting the sensing voltage Vs [ n ]]Thus generating a valley voltage Vvalley[n]. Fig. 2B shows a detailed block diagram of the valley detector 1521 of fig. 2A. The valley detector 1521 may include a latch circuit 15211 triggered by a rising edge of the switching control signal S to latch (or sample) the sensing voltage Vs [ n ]]Thus generating a trough voltage Vvalley[n]。
The constant on-time controller 15 of this embodiment may include a second arithmetic device 1525 for adding the valley voltage Vvalley[n]And a preset reference signal Vref, thereby generating a second signal that is fed to a second input node (e.g., a negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153, the first arithmetic device 1524 and the second arithmetic device 1525 form the arithmetic device of the present embodimentAnd (4) placing. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ]]+Vo[n])-(Vref+Vvalley[n])
Fig. 2C shows a block diagram of a digital fixed on-time (COT) controller 15 according to a first alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 2A. The Low Pass Filter (LPF)1512 and the valley detector 1521 of the current sensing circuit 151 of FIG. 2C are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 2A.
Fig. 3A shows a block diagram of a digital fixed on time (COT) controller 15 according to a second embodiment of the present invention. The constant on-time controller 15 of the present embodiment may comprise a semi-amplitude detector 1526 for detecting a half of a peak-to-peak value of the sensing voltage Vs [ n ] (of the current sensing circuit 151), thereby generating a semi-amplitude voltage Vpp/2[ n ]. Fig. 3B shows a detailed block diagram of the half-amplitude detector 1526 of fig. 3A. The half-amplitude detector 1526 may comprise a rising edge triggered latch circuit 15261, which is triggered to latch (or sample) the sensing voltage Vs [ n ] at the rising edge of the switching control signal S, thereby generating a minimum value. The half-amplitude detector 1526 may include a falling edge triggered latch circuit 15262 that latches (or samples) the sensing voltage Vs [ n ] upon a falling edge of the switching control signal S, thereby generating a maximum value. The half-amplitude detector 1526 may include an adder 15263 for subtracting the minimum value from the maximum value, thereby generating a peak-to-peak value. The half-amplitude detector 1526 may include a divided-by-two (d-by-2) device 15264 for dividing the peak-to-peak value by 2, thereby generating a half-amplitude voltage Vpp/2[ n ].
The fixed on-time controller 15 of the present embodiment may include a Direct Current (DC) voltage detector 1527 for detecting the effective series resistance R across the energy storage circuit 12 that provides the stored energy of the DC converterLD.c. voltage (i.e., R)LIL(DC)) Thus generating a DC voltage Vdc [ n ]]. FIG. 3C shows the DC voltage of FIG. 3AThe detector 1527 is a detailed block diagram. The dc voltage detector 1527 may comprise a rising edge triggered latch circuit 15271, which is triggered to latch (or sample) the sensing voltage Vs [ n ] at the rising edge of the delayed switching control signal S]Thus producing an intermediate value representing the inductor L and the effective series resistor RLThe dc voltage of the node between. The delayed switching control signal S is obtained by delaying the switching control signal S by half of the on period by the delay element 15272. The DC voltage detector 1527 may include an adder 15273 for subtracting the digital output voltage Vo [ n ] from the intermediate value]Thus generating a DC voltage Vdc [ n ]]。
The fixed on-time controller 15 of the present embodiment may comprise a first arithmetic device 1524 for adding the sensing voltage Vs [ n ] and the half-amplitude voltage Vpp/2[ n ] and subtracting the DC voltage Vdc [ n ], thereby generating a first signal, which is fed to a first input node (e.g., positive (+) input node) of the comparator 153. The reference signal Vref is preset as a second signal, which is fed to a second input node (e.g., a negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153 and the first arithmetic device 1524 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ] + Vpp/2[ n ] -Vdc [ n ]) -Vref [ n ] -
Fig. 3D shows a block diagram of a digital fixed on-time (COT) controller 15 according to a second alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 3A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 3D are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 3A.
Fig. 4A shows a block diagram of a digital fixed on-time (COT) controller 15 according to a third embodiment of the present invention. In the present embodiment, the sensing voltage Vs [ n ] (of the current sensing circuit 151) serves as a first signal, which is fed to a first input node (e.g., a positive (+) input node) of the comparator 153. The constant on-time controller 15 of the present embodiment may comprise a second arithmetic device 1525 for adding the reference signal Vref and the DC voltage Vdc [ n ] (of the DC voltage detector 1527) and subtracting the half-amplitude voltage Vpp/2[ n ] (of the half-amplitude detector 1526) to generate a second signal, which is fed to the second input node (e.g., the negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal Vs [ n ] - (Vref-Vpp/2[ n ] + Vdc [ n ])
Fig. 4B shows a block diagram of a digital fixed on-time (COT) controller 15 according to a third alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 4A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 4B are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 4A.
Fig. 5A shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fourth embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may comprise a first arithmetic device 1524 for adding the sensing voltage Vs [ n ] (of the current sensing circuit 151) and the half-amplitude voltage Vpp/2[ n ] (of the half-amplitude detector 1526) to generate a first signal, which is fed to a first input node (e.g., the positive (+) input node) of the comparator 153. The fixed on-time controller 15 of the present embodiment may comprise a second arithmetic device 1525 for adding the reference signal Vref and the dc voltage Vdc [ n ] (of the dc voltage detector 1527) to generate a second signal, which is fed to a second input node (e.g., a negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153, the first arithmetic device 1524 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ] + Vpp/2[ n ]) - (Vref + Vdc [ n ])
Fig. 5B shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fourth alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 5A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 5B are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 5A.
Fig. 6A shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fifth embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may comprise a first arithmetic device 1524 for subtracting the dc voltage Vdc [ n ] (of the dc voltage detector 1527) from the sensing voltage Vs [ n ], thereby generating a first signal, which is fed to a first input node (e.g., positive (+) input node) of the comparator 153. The fixed on-time controller 15 of the present embodiment may comprise a second arithmetic device 1525 for subtracting the half-amplitude voltage Vpp/2[ n ] (of the half-amplitude detector 1526) from the reference signal Vref, thereby generating a second signal, which is fed to a second input node (e.g., the negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153, the first arithmetic device 1524 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ] -Vdc [ n ]) - (Vref-Vpp/2[ n ])
Fig. 6B shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fifth alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 6A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 6B are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 5A.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (13)
1. A digital fixed on-time controller for a dc converter, comprising:
a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage;
a half-amplitude detector that detects a half of a peak-to-peak value of the sensing voltage, thereby generating a half-amplitude voltage;
a dc voltage detector that detects a dc voltage across the effective series resistor in an energy storage circuit that provides the stored energy, thereby generating a dc voltage;
an arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage and a preset reference signal; and
a pulse width modulation generator for generating a switching control signal according to a result of the arithmetic device;
wherein the arithmetic device comprises:
a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; and
a first arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage, thereby generating a first signal which is fed to a first input node of the comparator;
the predetermined reference signal is used as a second signal, which is fed to the second input node of the comparator.
2. The digital fixed on-time controller of claim 1, wherein the half-amplitude detector comprises:
a rising edge triggered latch circuit, triggered at the rising edge of the switching control signal or digital switching voltage to latch the sensing voltage, thereby generating a minimum value;
a falling edge trigger latch circuit which is triggered to latch the sensing voltage at the falling edge of the switching control signal or the digital switching voltage, thereby generating a maximum value;
an adder for subtracting the minimum value from the maximum value, thereby generating a peak-to-peak value; and
divide-by-two means for dividing the peak-to-peak value by 2, thereby generating the half-amplitude voltage.
3. The digital fixed on-time controller of claim 1, wherein the dc voltage detector comprises:
a delay element for delaying the switching control signal or the digital switching voltage by half a turn-on period to obtain a delayed switching control signal or a digital switching voltage;
a rising edge triggered latch circuit triggered at a rising edge of the delayed switching control signal or digital switching voltage to latch the sensing voltage, thereby generating an intermediate value; and
an adder for subtracting the digital output voltage of the DC converter from the intermediate value, thereby generating the DC voltage.
4. The digital fixed on-time controller of claim 1, wherein the first input node is a positive input node and the second input node is a negative input node.
5. A digital fixed on-time controller for a dc converter, comprising:
a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage;
a half-amplitude detector that detects a half of a peak-to-peak value of the sensing voltage, thereby generating a half-amplitude voltage;
a dc voltage detector that detects a dc voltage across the effective series resistor in an energy storage circuit that provides the stored energy, thereby generating a dc voltage;
an arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage and a preset reference signal; and
a pulse width modulation generator for generating a switching control signal according to a result of the arithmetic device;
wherein the arithmetic device comprises:
a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; and
a second arithmetic device for adding the predetermined reference signal and the DC voltage and subtracting the half-amplitude voltage, thereby generating a second signal, which is fed to a second input node of the comparator;
wherein the sensing voltage is provided as a first signal which is fed to a first input node of the comparator.
6. The digital fixed on-time controller of claim 5, wherein the first input node is a positive input node and the second input node is a negative input node.
7. A digital fixed on-time controller for a dc converter, comprising:
a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage;
a half-amplitude detector that detects a half of a peak-to-peak value of the sensing voltage, thereby generating a half-amplitude voltage;
a dc voltage detector that detects a dc voltage across the effective series resistor in an energy storage circuit that provides the stored energy, thereby generating a dc voltage;
an arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage and a preset reference signal; and
a pulse width modulation generator for generating a switching control signal according to a result of the arithmetic device;
wherein the arithmetic device comprises:
a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator;
a first arithmetic means for adding the sensing voltage and the half-amplitude voltage, thereby generating a first signal which is fed to a first input node of the comparator; and
a second arithmetic device for adding the predetermined reference signal and the DC voltage, thereby generating a second signal, which is fed to a second input node of the comparator.
8. The digital fixed on-time controller of claim 7, wherein the first input node is a positive input node and the second input node is a negative input node.
9. A digital fixed on-time controller for a dc converter, comprising:
a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage;
a half-amplitude detector that detects a half of a peak-to-peak value of the sensing voltage, thereby generating a half-amplitude voltage;
a dc voltage detector that detects a dc voltage across the effective series resistor in an energy storage circuit that provides the stored energy, thereby generating a dc voltage;
an arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage and a preset reference signal; and
a pulse width modulation generator for generating a switching control signal according to a result of the arithmetic device;
wherein the arithmetic device comprises:
a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator;
a first arithmetic device for subtracting the dc voltage from the sensed voltage, thereby generating a first signal, which is fed to a first input node of the comparator; and
second arithmetic means for subtracting the half-amplitude voltage from the predetermined reference signal, thereby generating a second signal, which is fed to a second input node of the comparator.
10. The digital fixed on-time controller of claim 9, wherein the first input node is a positive input node and the second input node is a negative input node.
11. A digital fixed on-time controller for a dc converter, comprising:
a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage;
a valley detector for detecting a valley value of the sensing voltage, thereby generating a valley voltage;
a comparator having a first input node and a second input node;
a first arithmetic device for adding the sensing voltage and the digital output voltage of the dc converter, thereby generating a first signal which is fed to a first input node of the comparator;
a second arithmetic device for adding the valley voltage and a predetermined reference signal, thereby generating a second signal, which is fed to a second input node of the comparator; and
a PWM generator for generating a switching control signal according to the comparison result of the comparator.
12. The digital fixed on-time controller of claim 11, wherein the valley detector comprises:
the rising edge triggers the latch circuit, which is triggered to latch the sensing voltage at the rising edge of the switching control signal or digital switching voltage, thereby generating the valley voltage.
13. The digital fixed on-time controller of claim 11, wherein the first input node is a positive input node and the second input node is a negative input node.
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