CN112350574A - Digital fixed on-time controller suitable for DC converter - Google Patents

Digital fixed on-time controller suitable for DC converter Download PDF

Info

Publication number
CN112350574A
CN112350574A CN201910722287.1A CN201910722287A CN112350574A CN 112350574 A CN112350574 A CN 112350574A CN 201910722287 A CN201910722287 A CN 201910722287A CN 112350574 A CN112350574 A CN 112350574A
Authority
CN
China
Prior art keywords
voltage
input node
comparator
generating
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910722287.1A
Other languages
Chinese (zh)
Other versions
CN112350574B (en
Inventor
胡恺育
蔡建泓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Himax Technologies Ltd
NCKU Research and Development Foundation
Original Assignee
Himax Technologies Ltd
NCKU Research and Development Foundation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Himax Technologies Ltd, NCKU Research and Development Foundation filed Critical Himax Technologies Ltd
Priority to CN201910722287.1A priority Critical patent/CN112350574B/en
Publication of CN112350574A publication Critical patent/CN112350574A/en
Application granted granted Critical
Publication of CN112350574B publication Critical patent/CN112350574B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A digital fixed on-time controller suitable for a DC converter comprises a current sensing circuit, a voltage sensing circuit and a control circuit, wherein the current sensing circuit senses the stored energy of the DC converter to generate a sensing voltage; a half-amplitude detector that detects a peak-to-peak value of the sensing voltage to thereby generate a half-amplitude voltage; a DC voltage detector, in the energy storage circuit providing stored energy, detecting a DC voltage across the effective series resistor, thereby generating a DC voltage; an arithmetic device which adds the sensing voltage and the half-amplitude voltage and subtracts the direct-current voltage and a preset reference signal; and a pulse width modulation generator for generating a switching control signal according to the result of the arithmetic device. The technical scheme provided by the invention can effectively improve the output voltage offset.

Description

Digital fixed on-time controller suitable for DC converter
Technical Field
The present invention relates to a direct current (DC-to-DC) converter, and more particularly, to a DC converter with offset cancellation.
Background
A power converter (power converter) is an electronic circuit that converts electrical energy from one form to another. A direct current (DC-to-DC) converter is one type of power converter for converting a DC source from one voltage level to another. In a dc converter, an inductor is usually disposed between a switching circuit and an output node to store energy.
The dc converter usually uses an analog current sensing circuit to sense the inductor current, so as to control the switching of the switching circuit. For a constant on-time (COT) dc converter, a ripple-based analog control is used to compare a sensed inductor current with a reference voltage, so as to generate a control signal for controlling the switching of a switching circuit. However, this mechanism generates an output voltage offset error, thereby reducing the regulation performance of the dc converter.
Therefore, it is desirable to provide a novel dc converter to improve the output voltage offset.
Disclosure of Invention
In view of the foregoing, an objective of the embodiments of the present invention is to provide a direct current (DC-to-DC) converter with output voltage offset cancellation, and particularly a digital fixed on-time controller suitable for a DC converter, which can effectively cancel the output voltage offset.
According to an embodiment of the present invention, a digital fixed on-time controller for a dc converter includes a current sensing circuit, a half-amplitude detector, a dc voltage detector, an arithmetic device, and a pwm generator. The current sensing circuit senses the stored energy of the DC converter to generate a sensing voltage. The half-amplitude detector detects a peak-to-peak half of the sensing voltage, thereby generating a half-amplitude voltage. The dc voltage detector detects a dc voltage across the effective series resistor in the energy storage circuit providing stored energy, thereby generating a dc voltage. The arithmetic device adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and a preset reference signal. The PWM generator generates a switching control signal according to the result of the arithmetic device.
Preferably, the half-amplitude detector comprises: a rising edge triggered latch circuit, triggered at the rising edge of the switching control signal or digital switching voltage to latch the sensing voltage, thereby generating a minimum value; a falling edge trigger latch circuit which is triggered to latch the sensing voltage at the falling edge of the switching control signal or the digital switching voltage, thereby generating a maximum value; an adder for subtracting the minimum value from the maximum value, thereby generating a peak-to-peak value; and a divide-by-two device for dividing the peak-to-peak value by 2, thereby generating the half-amplitude voltage.
Preferably, the dc voltage detector comprises: a delay element for delaying the switching control signal or the digital switching voltage by half a turn-on period to obtain a delayed switching control signal or a digital switching voltage; a rising edge triggered latch circuit triggered at a rising edge of the delayed switching control signal or digital switching voltage to latch the sensing voltage, thereby generating an intermediate value; and an adder for subtracting the digital output voltage of the DC converter from the intermediate value, thereby generating the DC voltage.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; and a first arithmetic device for adding the sensing voltage and the half-amplitude voltage and subtracting the DC voltage, thereby generating a first signal which is fed to a first input node of the comparator; the predetermined reference signal is used as a second signal, which is fed to the second input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; and a second arithmetic means for adding the predetermined reference signal and the DC voltage and subtracting the half-amplitude voltage, thereby generating a second signal which is fed to a second input node of the comparator; wherein the sensing voltage is provided as a first signal which is fed to a first input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; a first arithmetic means for adding the sensing voltage and the half-amplitude voltage, thereby generating a first signal which is fed to a first input node of the comparator; and a second arithmetic device for adding the predetermined reference signal and the DC voltage, thereby generating a second signal which is fed to a second input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
Preferably, the arithmetic device comprises: a comparator having a first input node and a second input node, the comparison result of the comparator being fed to the PWM generator; a first arithmetic device for subtracting the dc voltage from the sensed voltage, thereby generating a first signal, which is fed to a first input node of the comparator; and a second arithmetic device for subtracting the half-amplitude voltage from the predetermined reference signal, thereby generating a second signal, which is fed to a second input node of the comparator.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
According to an embodiment of the present invention, a digital fixed on-time controller for a dc converter includes: a current sensing circuit for sensing the stored energy of the DC converter to generate a sensing voltage; a valley detector for detecting a valley value of the sensing voltage, thereby generating a valley voltage; a comparator having a first input node and a second input node; a first arithmetic device for adding the sensing voltage and the digital output voltage of the dc converter, thereby generating a first signal which is fed to a first input node of the comparator; a second arithmetic device for adding the valley voltage and a predetermined reference signal, thereby generating a second signal, which is fed to a second input node of the comparator; and a PWM generator for generating a switching control signal according to the comparison result of the comparator.
Preferably, the valley detector comprises: the rising edge triggers the latch circuit, which is triggered to latch the sensing voltage at the rising edge of the switching control signal or digital switching voltage, thereby generating the valley voltage.
Preferably, the first input node is a positive input node, and the second input node is a negative input node.
By the technical scheme, the invention at least has the following advantages: the digital fixed conduction time controller applicable to the direct current converter can effectively offset the output voltage offset.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
Fig. 1A shows a circuit diagram of a dc converter with output voltage offset cancellation.
Fig. 1B shows a circuit diagram of a dc converter with output voltage offset cancellation.
Fig. 2A shows a block diagram of a digital fixed on time (COT) controller according to a first embodiment of the present invention.
Fig. 2B shows a detailed block diagram of the valley detector of fig. 2A.
Fig. 2C shows a block diagram of a digital fixed on-time (COT) controller according to a first alternative embodiment of the present invention.
Fig. 3A shows a block diagram of a digital fixed on time (COT) controller according to a second embodiment of the present invention.
Fig. 3B shows a detailed block diagram of the half-amplitude detector of fig. 3A.
Fig. 3C shows a detailed block diagram of the dc voltage detector of fig. 3A.
Fig. 3D shows a block diagram of a digital fixed on time (COT) controller according to a second alternative embodiment of the present invention.
Fig. 4A shows a block diagram of a digital fixed on-time (COT) controller according to a third embodiment of the present invention.
Fig. 4B shows a block diagram of a digital fixed on-time (COT) controller according to a third alternative embodiment of the present invention.
Fig. 5A shows a block diagram of a digital fixed on time (COT) controller according to a fourth embodiment of the invention.
Fig. 5B shows a block diagram of a digital fixed on-time (COT) controller according to a fourth alternative embodiment of the present invention.
Fig. 6A shows a block diagram of a digital fixed on time (COT) controller according to a fifth embodiment of the invention.
Fig. 6B shows a block diagram of a digital fixed on-time (COT) controller according to a fifth alternative embodiment of the present invention.
[ description of main element symbols ]
100: the dc converter 200: DC converter
11: the switching circuit 111: power supply
12: energy storage circuit 13: analog-to-digital converter
13A: the first analog-to-digital converter 13B: a second analog-to-digital converter
14: the driver 15: digital fixed on-time controller
151: current sensing circuit 1511: high-pass filter
1512: low-pass filter 1513: first adder
1521: valley detector 15211: rising edge triggered latch circuit
1524: the first arithmetic device 1525: second arithmetic device
1526: half-amplitude detector 15261: rising edge triggered latch circuit
15262: falling edge triggered latch circuit 15263: adder
15264: a divide-by-two device 1527: DC voltage detector
15271: the rising edge triggered latch circuit 15272: delay element
15273: the adder 153: comparator with a comparator circuit
154: pulse width modulation generator Mp: first switching device
Mn: second switching device L: inductor
RL: effective series resistor C: capacitor with a capacitor element
RC: effective series resistor Vx: switching voltage/switching node
Vx [ n ]: digital switching voltage Vo: output voltage/output node
Vin: input voltage IL: inductive current
Vo [ n ]: digital output voltage S: switching control signal
Vref: reference signal Vvalley[n]: trough voltage
Vs [ n ]: sense voltage Vpp/2[ n ]: half amplitude voltage
Vdc [ n ]: direct voltage
Detailed Description
Fig. 1A shows a circuit diagram of a direct current (DC-TO-DC) CONVERTER 100 with output voltage offset cancellation, disclosed in U.S. application No. 16/153,467, currently U.S. patent No. 10,291,121, entitled "DC CONVERTER and digital fixed ON-TIME CONTROLLER (DC-TO-DC CONVERTER AND A DIGITAL ON-TIME CONTROLLER thermal), filed ON 5.10.2018 by the present applicant. The dc converter 100 may include a switching circuit 11 for generating a switching voltage Vx. The switching circuit 11 may include a first switching device Mp and a second switching device Mn connected in series between the power source 111 and the ground. The power supply 111 provides an input voltage Vin. The switching voltage Vx is located at a switching node Vx between the first switching device Mp and the second switching device Mn.
The dc converter 100 may include an energy storage circuit 12 that receives a switching voltage Vx to generate a regulated output voltage Vo for provision to a load. Wherein the energy storage circuit 12 may include an inductor L and an effective series resistor RL connected in series between the switching node Vx and the output node Vo; and a capacitor C and an effective series resistor RC connected in series between the output node Vo and ground.
The DC converter 100 may include an analog-to-digital converter (ADC)13 for generating an equivalent digital output voltage Vo [ n ] of the (analog) output voltage Vo. The dc converter 100 may include a driver 14 (e.g., an amplifier) that generates a driving signal to drive the switching circuit 11. The driver 14 generates a driving signal to drive the first switching device Mp, and generates an inverted driving signal to drive the second switching device Mn.
The dc converter 100 may include a digital constant on-time (DCOT) controller 15 that receives the digital output voltage Vo [ n ] to generate a switching control signal S, which is fed to the driver 14. The digital fixed on-time controller 15 generates a fixed on-time (COT) switching control signal according to the stored energy of the energy storage circuit 12 (e.g., the inductor current IL flowing through the inductor L).
Fig. 1B shows a circuit diagram of a direct current (DC-to-DC) converter 200 with output voltage offset cancellation, which is disclosed in the aforementioned U.S. patent application of the present applicant. The dc converter 200 of fig. 1B is similar to the dc converter 100 of fig. 1A, and the differences will be explained below. In FIG. 1B, the first ADC 13A generates an equivalent digital output voltage Vo [ n ] of the (analog) output voltage Vo, and the second ADC 13B generates an equivalent digital switching voltage Vx [ n ] of the (analog) switching voltage Vx. Thus, the digital fixed on-time controller 15 of the second embodiment generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in the first embodiment.
Fig. 2A shows a block diagram of a digital fixed on time (COT) controller 15 according to a first embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may comprise a first arithmetic device 1524 for adding the sensing voltage Vs [ n ] (of the current sensing circuit 151)]And a digital output voltage Vo [ n ]]Thereby generating a first signal which is fed to the first of the comparators 153An input node (e.g., a positive (+) input node). The constant on-time controller 15 of the present embodiment may comprise a valley detector 1521 for detecting the sensing voltage Vs [ n ]]Thus generating a valley voltage Vvalley[n]. Fig. 2B shows a detailed block diagram of the valley detector 1521 of fig. 2A. The valley detector 1521 may include a latch circuit 15211 triggered by a rising edge of the switching control signal S to latch (or sample) the sensing voltage Vs [ n ]]Thus generating a trough voltage Vvalley[n]。
The constant on-time controller 15 of this embodiment may include a second arithmetic device 1525 for adding the valley voltage Vvalley[n]And a preset reference signal Vref, thereby generating a second signal that is fed to a second input node (e.g., a negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153, the first arithmetic device 1524 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ]]+Vo[n])-(Vref+Vvalley[n])
Fig. 2C shows a block diagram of a digital fixed on-time (COT) controller 15 according to a first alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 2A. The Low Pass Filter (LPF)1512 and the valley detector 1521 of the current sensing circuit 151 of FIG. 2C are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 2A.
Fig. 3A shows a block diagram of a digital fixed on time (COT) controller 15 according to a second embodiment of the present invention. The constant on-time controller 15 of the present embodiment may comprise a semi-amplitude detector 1526 for detecting a half of a peak-to-peak value of the sensing voltage Vs [ n ] (of the current sensing circuit 151), thereby generating a semi-amplitude voltage Vpp/2[ n ]. Fig. 3B shows a detailed block diagram of the half-amplitude detector 1526 of fig. 3A. The half-amplitude detector 1526 may comprise a rising edge triggered latch circuit 15261, which is triggered to latch (or sample) the sensing voltage Vs [ n ] at the rising edge of the switching control signal S, thereby generating a minimum value. The half-amplitude detector 1526 may include a falling edge triggered latch circuit 15262 that latches (or samples) the sensing voltage Vs [ n ] upon a falling edge of the switching control signal S, thereby generating a maximum value. The half-amplitude detector 1526 may include an adder 15263 for subtracting the minimum value from the maximum value, thereby generating a peak-to-peak value. The half-amplitude detector 1526 may include a divided-by-two (d-by-2) device 15264 for dividing the peak-to-peak value by 2, thereby generating a half-amplitude voltage Vpp/2[ n ].
The fixed on-time controller 15 of the present embodiment may include a Direct Current (DC) voltage detector 1527 for detecting the effective series resistance R across the energy storage circuit 12 that provides the stored energy of the DC converterLD.c. voltage (i.e., R)LIL(DC)) Thus generating a DC voltage Vdc [ n ]]. Fig. 3C shows a detailed block diagram of the dc voltage detector 1527 of fig. 3A. The dc voltage detector 1527 may comprise a rising edge triggered latch circuit 15271, which is triggered to latch (or sample) the sensing voltage Vs [ n ] at the rising edge of the delayed switching control signal S]Thus producing an intermediate value representing the inductor L and the effective series resistor RLThe dc voltage of the node between. The delayed switching control signal S is obtained by delaying the switching control signal S by half of the on period by the delay element 15272. The DC voltage detector 1527 may include an adder 15273 for subtracting the digital output voltage Vo [ n ] from the intermediate value]Thus generating a DC voltage Vdc [ n ]]。
The fixed on-time controller 15 of the present embodiment may comprise a first arithmetic device 1524 for adding the sensing voltage Vs [ n ] and the half-amplitude voltage Vpp/2[ n ] and subtracting the DC voltage Vdc [ n ], thereby generating a first signal, which is fed to a first input node (e.g., positive (+) input node) of the comparator 153. The reference signal Vref is preset as a second signal, which is fed to a second input node (e.g., a negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153 and the first arithmetic device 1524 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ] + Vpp/2[ n ] -Vdc [ n ]) -Vref [ n ] -
Fig. 3D shows a block diagram of a digital fixed on-time (COT) controller 15 according to a second alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 3A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 3D are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 3A.
Fig. 4A shows a block diagram of a digital fixed on-time (COT) controller 15 according to a third embodiment of the present invention. In the present embodiment, the sensing voltage Vs [ n ] (of the current sensing circuit 151) serves as a first signal, which is fed to a first input node (e.g., a positive (+) input node) of the comparator 153. The constant on-time controller 15 of the present embodiment may comprise a second arithmetic device 1525 for adding the reference signal Vref and the DC voltage Vdc [ n ] (of the DC voltage detector 1527) and subtracting the half-amplitude voltage Vpp/2[ n ] (of the half-amplitude detector 1526) to generate a second signal, which is fed to the second input node (e.g., the negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal Vs [ n ] - (Vref-Vpp/2[ n ] + Vdc [ n ])
Fig. 4B shows a block diagram of a digital fixed on-time (COT) controller 15 according to a third alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 4A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 4B are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 4A.
Fig. 5A shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fourth embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may comprise a first arithmetic device 1524 for adding the sensing voltage Vs [ n ] (of the current sensing circuit 151) and the half-amplitude voltage Vpp/2[ n ] (of the half-amplitude detector 1526) to generate a first signal, which is fed to a first input node (e.g., the positive (+) input node) of the comparator 153. The fixed on-time controller 15 of the present embodiment may comprise a second arithmetic device 1525 for adding the reference signal Vref and the dc voltage Vdc [ n ] (of the dc voltage detector 1527) to generate a second signal, which is fed to a second input node (e.g., a negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153, the first arithmetic device 1524 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ] + Vpp/2[ n ]) - (Vref + Vdc [ n ])
Fig. 5B shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fourth alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 5A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 5B are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 5A.
Fig. 6A shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fifth embodiment of the present invention. In this embodiment, the fixed on-time controller 15 may comprise a first arithmetic device 1524 for subtracting the dc voltage Vdc [ n ] (of the dc voltage detector 1527) from the sensing voltage Vs [ n ], thereby generating a first signal, which is fed to a first input node (e.g., positive (+) input node) of the comparator 153. The fixed on-time controller 15 of the present embodiment may comprise a second arithmetic device 1525 for subtracting the half-amplitude voltage Vpp/2[ n ] (of the half-amplitude detector 1526) from the reference signal Vref, thereby generating a second signal, which is fed to a second input node (e.g., the negative (-) input node) of the comparator 153. The comparison result of the comparator 153 may be fed to a Pulse Width Modulation (PWM) generator 154 for generating the switching control signal S. The comparator 153, the first arithmetic device 1524 and the second arithmetic device 1525 constitute the arithmetic device of the present embodiment. In the present embodiment, the comparison result of the comparator 153 can be expressed as follows:
first signal-second signal ═ (Vs [ n ] -Vdc [ n ]) - (Vref-Vpp/2[ n ])
Fig. 6B shows a block diagram of a digital fixed on-time (COT) controller 15 according to a fifth alternative embodiment of the present invention. In the present embodiment, the digital fixed on-time controller 15 generates the switching control signal S according to the digital output voltage Vo [ n ] and the digital switching voltage Vx [ n ], but only according to the digital output voltage Vo [ n ] in FIG. 6A. The Low Pass Filter (LPF)1512, the half-amplitude detector 1526 and the DC voltage detector 1527 of the current sensing circuit 151 of FIG. 6B are implemented according to the digital switching voltage Vx [ n ], but are implemented according to the switching control signal S in FIG. 5A.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (14)

1.一种适用于直流转换器的数字固定导通时间控制器，其特征在于包含：1. A digital fixed on-time controller applicable to a DC converter is characterized in that comprising: 电流感测电路，其感测该直流转换器的储存能量，以产生感测电压；a current sensing circuit, which senses the stored energy of the DC converter to generate a sensing voltage; 半振幅侦测器，其侦测该感测电压的峰至峰值的一半，因而产生半振幅电压；a half-amplitude detector that detects half of the peak-to-peak value of the sensed voltage, thereby generating a half-amplitude voltage; 直流电压侦测器，在提供该储存能量的能量储存电路当中，侦测跨于有效串联电阻器的直流电压，因而产生直流电压；A DC voltage detector, in an energy storage circuit that provides the stored energy, detects a DC voltage across an effective series resistor, thereby generating a DC voltage; 算术装置，其加入该感测电压与该半振幅电压，并减去该直流电压与预设参考信号；及an arithmetic device that adds the sensing voltage and the half-amplitude voltage, and subtracts the DC voltage and a predetermined reference signal; and 脉宽调变产生器，其根据该算术装置的结果以产生切换控制信号。A pulse width modulation generator for generating a switching control signal according to the result of the arithmetic device. 2.根据权利要求1所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该半振幅侦测器包含：2. The digital fixed on-time controller suitable for a DC converter according to claim 1, wherein the half-amplitude detector comprises: 升缘触发闩锁电路，在该切换控制信号或数字切换电压的升缘触发以闩锁该感测电压，因而产生最小值；a rising edge trigger latch circuit, which is triggered at the rising edge of the switching control signal or the digital switching voltage to latch the sensing voltage, thereby generating a minimum value; 降缘触发闩锁电路，在该切换控制信号或该数字切换电压的降缘触发以闩锁该感测电压，因而产生最大值；a falling edge trigger latch circuit, which is triggered at the falling edge of the switching control signal or the digital switching voltage to latch the sensing voltage, thereby generating a maximum value; 加法器，用以将该最大值减去该最小值，因而产生峰至峰值；及an adder for subtracting the minimum value from the maximum value, thereby producing a peak-to-peak value; and 除二装置，用以将该峰至峰值除以2，因而产生该半振幅电压。A divide-by-two device is used to divide the peak-to-peak value by 2, thereby generating the half-amplitude voltage. 3.根据权利要求1所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该直流电压侦测器包含：3. The digital fixed on-time controller suitable for a DC converter according to claim 1, wherein the DC voltage detector comprises: 延迟元件，用以将该切换控制信号或数字切换电压延迟半个导通周期以得到延迟的切换控制信号或数字切换电压；a delay element for delaying the switching control signal or the digital switching voltage by half a conduction period to obtain the delayed switching control signal or the digital switching voltage; 升缘触发闩锁电路，在该延迟的切换控制信号或数字切换电压的升缘触发以闩锁该感测电压，因而产生中间值；及a rising edge trigger latch circuit that triggers on the rising edge of the delayed switching control signal or digital switching voltage to latch the sensing voltage, thereby generating an intermediate value; and 加法器，用以将该中间值减去该直流转换器的数字输出电压，因而产生该直流电压。an adder for subtracting the digital output voltage of the DC converter from the intermediate value, thereby generating the DC voltage. 4.根据权利要求1所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该算术装置包含：4. The digital fixed on-time controller suitable for a DC converter according to claim 1, wherein the arithmetic device comprises: 比较器，具有第一输入节点与第二输入节点，该比较器的比较结果馈至该脉宽调变产生器；及a comparator having a first input node and a second input node, and a comparison result of the comparator is fed to the PWM generator; and 第一算术装置，用以加入该感测电压与该半振幅电压，并减去该直流电压，因而产生第一信号，其馈至该比较器的第一输入节点；a first arithmetic device for adding the sensing voltage and the half-amplitude voltage, and subtracting the DC voltage, thereby generating a first signal, which is fed to the first input node of the comparator; 其中该预设参考信号作为第二信号，其馈至该比较器的第二输入节点。The preset reference signal is used as the second signal, which is fed to the second input node of the comparator. 5.根据权利要求4所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该第一输入节点为正输入节点，且该第二输入节点为负输入节点。5 . The digital fixed on-time controller of claim 4 , wherein the first input node is a positive input node, and the second input node is a negative input node. 6 . 6.根据权利要求1所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该算术装置包含：6. The digital fixed on-time controller suitable for a DC converter according to claim 1, wherein the arithmetic device comprises: 比较器，具有第一输入节点与第二输入节点，该比较器的比较结果馈至该脉宽调变产生器；及a comparator having a first input node and a second input node, and a comparison result of the comparator is fed to the PWM generator; and 第二算术装置，用以加入该预设参考信号与该直流电压，并减去该半振幅电压，因而产生第二信号，其馈至该比较器的第二输入节点；second arithmetic means for adding the preset reference signal and the DC voltage, and subtracting the half-amplitude voltage, thereby generating a second signal, which is fed to the second input node of the comparator; 其中该感测电压作为第一信号，其馈至该比较器的第一输入节点。The sensing voltage is used as the first signal, which is fed to the first input node of the comparator. 7.根据权利要求6所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该第一输入节点为正输入节点，且该第二输入节点为负输入节点。7 . The digital fixed on-time controller of claim 6 , wherein the first input node is a positive input node, and the second input node is a negative input node. 8 . 8.根据权利要求1所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该算术装置包含：8. The digital fixed on-time controller suitable for a DC converter according to claim 1, wherein the arithmetic device comprises: 比较器，具有第一输入节点与第二输入节点，该比较器的比较结果馈至该脉宽调变产生器；a comparator with a first input node and a second input node, and the comparison result of the comparator is fed to the PWM generator; 第一算术装置，用以加入该感测电压与该半振幅电压，因而产生第一信号，其馈至该比较器的第一输入节点；及a first arithmetic device for adding the sensing voltage and the half-amplitude voltage, thereby generating a first signal, which is fed to a first input node of the comparator; and 第二算术装置，用以加入该预设参考信号与该直流电压，因而产生第二信号，其馈至该比较器的第二输入节点。The second arithmetic device is used for adding the predetermined reference signal and the DC voltage, thereby generating a second signal, which is fed to the second input node of the comparator. 9.根据权利要求8所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该第一输入节点为正输入节点，且该第二输入节点为负输入节点。9 . The digital fixed on-time controller of claim 8 , wherein the first input node is a positive input node, and the second input node is a negative input node. 10 . 10.根据权利要求1所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该算术装置包含：10. The digital fixed on-time controller suitable for a DC converter according to claim 1, wherein the arithmetic device comprises: 比较器，具有第一输入节点与第二输入节点，该比较器的比较结果馈至该脉宽调变产生器；a comparator with a first input node and a second input node, and the comparison result of the comparator is fed to the PWM generator; 第一算术装置，用以将该感测电压减去该直流电压，因而产生第一信号，其馈至该比较器的第一输入节点；及a first arithmetic device for subtracting the DC voltage from the sensing voltage, thereby generating a first signal, which is fed to a first input node of the comparator; and 第二算术装置，用以将该预设参考信号减去该半振幅电压，因而产生第二信号，其馈至该比较器的第二输入节点。second arithmetic means for subtracting the half-amplitude voltage from the predetermined reference signal, thereby generating a second signal, which is fed to the second input node of the comparator. 11.根据权利要求10所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该第一输入节点为正输入节点，且该第二输入节点为负输入节点。11 . The digital fixed on-time controller of claim 10 , wherein the first input node is a positive input node, and the second input node is a negative input node. 12 . 12.一种适用于直流转换器的数字固定导通时间控制器，其特征在于包含：12. A digital fixed on-time controller suitable for a DC converter, characterized by comprising: 电流感测电路，其感测该直流转换器的储存能量，以产生感测电压；a current sensing circuit, which senses the stored energy of the DC converter to generate a sensing voltage; 波谷侦测器，用以侦测该感测电压的波谷值，因而产生波谷电压；a valley detector for detecting the valley value of the sensing voltage, thereby generating a valley voltage; 比较器，具有第一输入节点与第二输入节点；a comparator, having a first input node and a second input node; 第一算术装置，用以加入该感测电压与该直流转换器的数字输出电压，因而产生第一信号，其馈至该比较器的第一输入节点；a first arithmetic device for adding the sensing voltage and the digital output voltage of the DC converter, thereby generating a first signal, which is fed to the first input node of the comparator; 第二算术装置，用以加入该波谷电压与预设参考信号，因而产生第二信号，其馈至该比较器的第二输入节点；及second arithmetic means for adding the valley voltage and a predetermined reference signal, thereby generating a second signal, which is fed to the second input node of the comparator; and 脉宽调变产生器，其根据该比较器的比较结果以产生切换控制信号。A pulse width modulation generator, which generates a switching control signal according to the comparison result of the comparator. 13.根据权利要求12所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该波谷侦测器包含：13. The digital fixed on-time controller suitable for a DC converter according to claim 12, wherein the valley detector comprises: 升缘触发闩锁电路，在该切换控制信号或数字切换电压的升缘触发以闩锁该感测电压，因而产生该波谷电压。The rising edge trigger latch circuit is triggered at the rising edge of the switching control signal or the digital switching voltage to latch the sensing voltage, thereby generating the valley voltage. 14.根据权利要求12所述适用于直流转换器的数字固定导通时间控制器，其特征在于，其中该第一输入节点为正输入节点，且该第二输入节点为负输入节点。14 . The digital fixed on-time controller of claim 12 , wherein the first input node is a positive input node, and the second input node is a negative input node. 15 .
CN201910722287.1A 2019-08-06 2019-08-06 Digital Fixed On-Time Controller for DC Converters Active CN112350574B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910722287.1A CN112350574B (en) 2019-08-06 2019-08-06 Digital Fixed On-Time Controller for DC Converters

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910722287.1A CN112350574B (en) 2019-08-06 2019-08-06 Digital Fixed On-Time Controller for DC Converters

Publications (2)

Publication Number Publication Date
CN112350574A true CN112350574A (en) 2021-02-09
CN112350574B CN112350574B (en) 2022-03-15

Family

ID=74367148

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910722287.1A Active CN112350574B (en) 2019-08-06 2019-08-06 Digital Fixed On-Time Controller for DC Converters

Country Status (1)

Country Link
CN (1) CN112350574B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160172974A1 (en) * 2014-12-15 2016-06-16 Kabushiki Kaisha Toshiba Power supply circuit and control method thereof
CN109429541A (en) * 2016-09-29 2019-03-05 富士电机株式会社 Control method, control device and the inverter of inverter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160172974A1 (en) * 2014-12-15 2016-06-16 Kabushiki Kaisha Toshiba Power supply circuit and control method thereof
CN109429541A (en) * 2016-09-29 2019-03-05 富士电机株式会社 Control method, control device and the inverter of inverter

Also Published As

Publication number Publication date
CN112350574B (en) 2022-03-15

Similar Documents

Publication Publication Date Title
JP4899547B2 (en) Switching power supply
US5764039A (en) Power factor correction circuit having indirect input voltage sensing
JP5163283B2 (en) Power factor correction circuit
JP5382216B2 (en) Switching power supply circuit and power factor correction circuit
US9479047B2 (en) System and method for controlling a power supply with a feed forward controller
US9136760B2 (en) Digital switched mode voltage regulator
US20150303790A1 (en) Power factor correction circuit with digital control scheme and associated control method
US20130223119A1 (en) Boost pfc controller
JP5343816B2 (en) Power factor improved switching power supply
JP2005110434A (en) Power factor improvement circuit
KR20120020080A (en) Method and apparatus for bridgeless power factor correction
JP6272691B2 (en) Amplitude normalization circuit, power supply device and electronic device
TWI543516B (en) Relative efficiency measurement in a pulse width modulation system
EP3160033B1 (en) Current sensing system for full-bridge pulse-width modulated inverter system
JP2012217247A (en) Power-supply circuit
JP2019068675A (en) AC-DC converter
TW201025813A (en) Voltage converters and voltage generating methods
JP2011152017A (en) Switching power supply device
EP3503392A1 (en) Ripple generation device for a constant on-time voltage regulator
JP2022100592A (en) Switching control circuit and power circuit
US20100246227A1 (en) Switching power supply
JP4466089B2 (en) Power factor correction circuit
JP6911677B2 (en) AC-DC converter
TWM454670U (en) DC-DC converter
CN110247547B (en) Switching power converter and its controller circuit and control method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant