CN112350146A - VCSEL array electrode structure and preparation method - Google Patents

VCSEL array electrode structure and preparation method Download PDF

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CN112350146A
CN112350146A CN202011164068.5A CN202011164068A CN112350146A CN 112350146 A CN112350146 A CN 112350146A CN 202011164068 A CN202011164068 A CN 202011164068A CN 112350146 A CN112350146 A CN 112350146A
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vcsel
array
dbr structure
metal electrode
subarray
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CN112350146B (en
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王智勇
李冲
兰天
李颖
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Beijing University of Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
    • H01S5/42—Arrays of surface emitting lasers
    • H01S5/423—Arrays of surface emitting lasers having a vertical cavity

Abstract

The invention discloses a VCSEL array electrode structure and a preparation method thereof, wherein the preparation method comprises the following steps: the VCSEL light emitting array is provided with MxN VCSEL light emitting units, the VCSEL light emitting array is divided into a plurality of VCSEL sub-arrays according to every M x N VCSEL light emitting units, and an isolation channel etched to an insulating substrate is arranged between every two adjacent VCSEL sub-arrays; one end of each VCSEL subarray is reserved with an upper DBR structure, and the other end of each VCSEL subarray is etched to the lower DBR structure and distributed in a staggered mode; each VCSEL subarray is provided with an upper metal electrode connected with the upper DBR structure and a lower metal electrode connected with the lower DBR structure, and the upper metal electrode and the lower metal electrode of any VCSEL subarray are respectively connected with the lower metal electrode and the upper metal electrode of the adjacent VCSEL subarray to form series conduction. The invention greatly reduces the driving current required by the high-power VCSEL array chip and reduces the requirement on the complexity of a driving circuit by adjusting the parallel driving mode of all the light-emitting units in the original VCSEL array into the mode of combining series connection and parallel connection.

Description

VCSEL array electrode structure and preparation method
Technical Field
The invention relates to the technical field of VCSEL lasers, in particular to a VCSEL array electrode structure and a preparation method thereof.
Background
The VCSEL laser has the advantages of small volume, light emitting direction perpendicular to a substrate, easiness in two-dimensional integration, small threshold current, circular symmetric light spots, single longitudinal mode working, high modulation rate and the like, has excellent structural characteristics and physical characteristics, is widely applied to the fields of large-scale data centers, face recognition systems, optical interconnection, optical storage, optical detection and the like, has wide market prospect, and is expected to reach $ 10 billion in the worldwide VCSEL market in 2022 years.
With the continuous advancing development of the technology, each field gradually has higher application requirements on the high-power VCSEL device, and higher requirements on the output power and the beam quality of the high-power VCSEL device are provided, so that the array VCSEL laser is produced.
The circuits adopted by the traditional VCSEL array laser are connected in parallel, namely: all VCSEL sub-light sources adopt a common cathode or common anode design and are conducted in a parallel connection mode, so that a required driving power supply has the characteristics of low voltage and large current. With the increase of the power of the VCSEL array, the requirement for large current becomes stronger, which puts more severe requirements on the driving power supply.
Disclosure of Invention
In view of the above problems in the prior art, the present invention provides a VCSEL array electrode structure and a fabrication method thereof.
The invention discloses a VCSEL array electrode structure, comprising: the VCSEL light emitting array comprises M multiplied by N VCSEL light emitting units, and comprises an insulating substrate, a lower DBR structure, an active layer, an oxidation layer and an upper DBR structure from bottom to top;
the VCSEL light emitting array is divided into a plurality of VCSEL sub-arrays according to every m multiplied by n VCSEL light emitting units, an isolation channel etched to the insulating substrate is arranged between every two adjacent VCSEL sub-arrays, an insulating material is filled in the isolation channel to form an insulating layer, one end of each VCSEL sub-array is reserved with an upper DBR structure, and the other end of each VCSEL sub-array is etched to a lower DBR structure and is distributed in a staggered mode;
each VCSEL subarray is provided with an upper metal electrode connected with the upper DBR structure and a lower metal electrode connected with the lower DBR structure, and the upper metal electrode and the lower metal electrode of any VCSEL subarray are respectively connected with the lower metal electrode and the upper metal electrode of the adjacent VCSEL subarray to form series conduction.
As a further improvement of the invention, all the VCSEL light emitting units are distributed at equal intervals.
As a further improvement of the invention, M is more than or equal to 2, N is more than or equal to 2, and M is less than or equal to M, N and less than or equal to N.
As a further improvement of the invention, in the VCSEL subarray, all the VCSEL light emitting units are connected through the same lower DBR structure to form a coplanar electrode; and the number of the Bragg reflector pairs of the lower DBR structure is greater than that of the Bragg reflectors of the upper DBR structure.
As a further improvement of the present invention, the insulating substrate includes one of a GaAs substrate, a SiC substrate and an SOI substrate, and the insulating material includes SiO2、SiNxOne of the materials, the upper metal electrode material or the lower metal electrode material comprises one or more of Al, Ti, Pt, Pb, Au, Cu, Ni and Ge to form an alloy material.
As a further improvement of the invention, the arrangement mode of the upper metal electrodes and the lower metal electrodes of two adjacent VCSEL sub-arrays is alternately distributed; the upper metal electrode of one VCSEL subarray is adjacent to the lower metal electrode of the other VCSEL subarray, and the lower metal electrode of one VCSEL subarray is adjacent to the upper metal electrode of the other VCSEL subarray.
As a further improvement of the invention, the upper and lower metal electrodes of the VCSEL subarray are respectively connected with the lower and upper metal electrodes of the adjacent VCSEL subarray in a gold plating or sputtering metal electrode mode, and finally Au is deposited on the metal electrodes to form a flat surface.
As a further improvement of the invention, after the VCSEL subarrays are connected in series, the unconnected upper metal electrode at one end is connected to the positive electrode of an external driving power supply, and the unconnected lower metal electrode at one end is connected to the negative electrode of the external driving power supply.
The invention also discloses a preparation method of the VCSEL array electrode structure, which comprises the following steps:
taking every m multiplied by n VCSEL light emitting units in the VCSEL light emitting array as a VCSEL sub-array, and etching the insulating substrate between the adjacent VCSEL sub-arrays to form an isolation channel;
depositing an insulating layer on the surface of the table top of the VCSEL light emitting array, wherein the thickness of the finally formed insulating layer is higher than that of the upper DBR structure;
removing the insulating layer on the surface of the upper DBR structure of the VCSEL light-emitting unit, exposing the upper DBR structure and the upper DBR structure at one end of the first VCSEL subarray, and reserving the insulating layer on the surface of the VCSEL light-emitting hole and the insulating layers at the upper edge and the lower edge of the VCSEL light-emitting array; sputtering a metal electrode on the surface of the exposed upper DBR structure;
etching to remove the insulating layers positioned at the upper edge and the lower edge of the VCSEL luminous array, and alternately exposing the upper DBR structure and the lower DBR structure of the VCSEL subarray; reserving an insulating layer deposited in an insulating channel between adjacent VCSEL subarrays; sputtering a lower metal electrode on the exposed lower DBR structure and the exposed upper DBR structure;
sputtering a metal conducting layer on the surfaces of the adjacent upper metal electrode and the lower metal electrode to realize connection and conduction; and finally, removing the insulating layer covered on the surface of the VCSEL light outlet hole to expose the upper DBR structure.
The invention also discloses a preparation method of the VCSEL array electrode structure, which comprises the following steps:
taking every m multiplied by n VCSEL light emitting units in the VCSEL light emitting array as a VCSEL sub-array, and etching the insulating substrate between the adjacent VCSEL sub-arrays to form an isolation channel;
depositing an insulating layer on the surface of the table top of the VCSEL light emitting array, wherein the thickness of the finally formed insulating layer is higher than that of the upper DBR structure;
removing the insulating layer on the surface of the upper DBR structure of the VCSEL light-emitting unit, exposing the upper DBR structure and the upper DBR structure at one end of the first VCSEL subarray, and reserving the insulating layers at the upper edge and the lower edge of the VCSEL light-emitting array; sputtering a metal electrode on the surface of the exposed upper DBR structure;
etching to remove the insulating layers positioned at the upper edge and the lower edge of the VCSEL luminous array, and alternately exposing the upper DBR structure and the lower DBR structure of the VCSEL subarray; reserving an insulating layer deposited in an insulating channel between adjacent VCSEL subarrays; sputtering a lower metal electrode on the exposed lower DBR structure and the exposed upper DBR structure;
and sputtering a metal conducting layer on the surfaces of the adjacent upper metal electrode and the lower metal electrode to realize connection and conduction.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, the original VCSEL light emitting array is provided with the insulation channel and is divided into a plurality of VCSEL sub-arrays; the VCSEL light emitting units in the VCSEL sub-arrays are arranged in a parallel connection mode, and the VCSEL sub-arrays are arranged in a series connection mode; therefore, the driving current required by the whole VCSEL array is reduced, and the harsh requirement on an external driving circuit can be effectively reduced especially under the condition of high-power output.
Drawings
Fig. 1 is a schematic cross-sectional view of a VCSEL light-emitting unit according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a VCSEL subarray formed after multiple etching on the basis of FIG. 1; wherein, a is a front view, and b is a top view;
FIG. 3 is a schematic structural diagram of a VCSEL array with an insulating medium deposited on the upper surface of the VCSEL array in the structure of FIG. 2;
FIG. 4 is a schematic structural diagram of a VCSEL array with a p-type ohmic contact electrode sputtered on the surface of the VCSEL array based on FIG. 3; wherein, a is a front view, and b is a top view;
FIG. 5 is a schematic structural diagram of a VCSEL array with an n-type ohmic contact electrode sputtered on the surface of the VCSEL array based on FIG. 4; wherein, a is a front view, and b is a top view;
fig. 6 is a schematic diagram of the VCSEL array electrode structure formed by sputtering a metal conducting layer on the surface of the VCSEL array electrode structure in fig. 5.
In the figure:
101. an insulating substrate; 102. a lower DBR structure; 103. an active layer; 104. an oxide layer; 105. an upper DBR structure; 201. an insulating layer; 301. a p-type ohmic contact electrode; 302. an n-type ohmic contact electrode; 303. a metal conducting layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The invention is described in further detail below with reference to the attached drawing figures:
as shown in fig. 1 to 6, the present invention provides a VCSEL array electrode structure, which includes: the VCSEL light emitting array is provided with MXN VCSEL light emitting units, M is more than or equal to 2, N is more than or equal to 2, and all the VCSEL light emitting units are distributed at equal intervals; the VCSEL light emitting array structurally comprises an insulating substrate 101, a lower DBR structure 102, an active layer 103, an oxidation layer 104 and an upper DBR structure 105 from bottom to top, and all VCSEL light emitting units are connected through the same lower DBR structure to form a coplanar electrode; and has M × N upper DBR structures 105; also, the number of bragg mirror pairs of the lower DBR structure 102 is greater than the number of bragg mirror pairs of the upper DBR structure 105.
Based on the VCSEL light emitting array, the VCSEL light emitting array can be divided into a plurality of VCSEL sub-arrays according to m multiplied by N VCSEL light emitting units, wherein m is less than or equal to M, N and is less than or equal to N; for example, if M is 9 and N is 6, the VCSEL light emitting array may be divided into three VCSEL sub-arrays from left to right according to M is 9 and N is 2. According to the invention, an isolation channel etched to the insulating substrate 101 is arranged between the adjacent VCSEL sub-arrays, and the isolation channel can be filled with insulating materials to form an insulating layer 201 so as to block the two adjacent VCSEL sub-arrays. The invention reserves an upper DBR structure 105 at one end of a plurality of VCSEL sub-arrays, the other end is etched to a lower DBR structure 102 and is distributed in a staggered way, each VCSEL sub-array is provided with an upper metal electrode (p-type ohmic contact electrode 301) connected with the upper DBR structure and a lower metal electrode (n-type ohmic contact electrode 302) connected with the lower DBR structure, and the upper metal electrode and the lower metal electrode of any VCSEL sub-array are respectively connected with the lower metal electrode and the upper metal electrode of the adjacent VCSEL sub-array to form series conduction.
Wherein the content of the first and second substances,
the invention is Mxn hairThe VCSEL subarray formed by the optical units needs a driving current of
Figure BDA0002745176340000051
The insulating substrate 101 of the present invention includes one of a GaAs substrate, a SiC substrate and an SOI substrate, and the insulating material includes SiO2、SiNxOne of the materials, the upper metal electrode material or the lower metal electrode material comprises one or more of Al, Ti, Pt, Pb, Au, Cu, Ni and Ge to form an alloy material, and the same metal material or different metal materials can be selected.
The arrangement mode of the upper metal electrodes and the lower metal electrodes of two adjacent VCSEL subarrays is alternatively distributed; that is, the upper metal electrode of one VCSEL sub-array is adjacent to the lower metal electrode of another VCSEL sub-array, and the lower metal electrode of one VCSEL sub-array is adjacent to the upper metal electrode of another VCSEL sub-array.
The upper and lower metal electrodes of the VCSEL subarray are respectively connected with the lower and upper metal electrodes of the adjacent VCSEL subarray in a gold plating or sputtering metal electrode mode, and finally Au is deposited on the metal electrodes to form a flat surface.
After the VCSEL subarrays are connected in series, an upper metal electrode at one unconnected end is connected to the positive electrode of an external driving power supply, and a lower metal electrode at one unconnected end is connected to the negative electrode of the external driving power supply; the two electrodes are etched to the insulating substrate, and then the insulating medium and the corresponding upper metal electrode and lower metal electrode types are deposited in sequence, so that the required electrodes are formed.
Example 1
As shown in fig. 1, an embodiment of the present invention provides an epitaxial wafer with a complete positive-emitting VCSEL array light-emitting structure, which includes: an insulating substrate 101, a lower DBR structure 102, an active layer 103, an oxide layer 104, and an upper DBR structure 105. All VCSEL light emitting cells are connected by the lower DBR structure 102 forming a coplanar electrode.
Wherein the number of bragg mirror pairs of the lower DBR structure 102 is greater than the number of bragg mirror pairs of the upper DBR structure 105.
The following describes a method for manufacturing a VCSEL array electrode structure according to the present invention, which includes the following steps:
s1, as shown in fig. 2, first, every M × n VCSEL light emitting units are used as a VCSEL sub-array, and adjacent VCSEL sub-arrays are etched to the insulating substrate 101 by a mask etching technique to form an insulating channel, where the channel width is 5 um. And the right side of the last VCSEL subarray is not etched back, and the original lower DBR structure is reserved. In this embodiment, M is 9, N is 6, and N is 2.
Preferably, the etching technique is an ICP dry etching technique.
S2, as shown in fig. 3, the insulating layer 201 is deposited on the surface of the VCSEL array mesa by a deposition process, and the insulating layer 201 is finally formed to have a thickness higher than that of the upper DBR structure 105.
Preferably, the insulating medium material is SiO2Or SiNx。
S3, as shown in fig. 4, the insulating layer 201 on the surface of the upper DBR structure 105 of the VCSEL light-emitting unit is removed by a mask etching process to expose the upper DBR structure 105 and the upper DBR structure 105 on the left side of the first VCSEL sub-array. Wherein, an insulating layer 201 on the surface of the VCSEL light exit aperture and an insulating layer 201 at the upper and lower edges of the VCSEL array are remained. Subsequently, a metal electrode is sputtered on the exposed surface of the upper DBR structure 105 as the p-type ohmic contact electrode 301.
Preferably, the p-type ohmic electrode 301 material is 10nmTi +50nmAu +30nmGe alloy material.
S4, as shown in fig. 5, the insulating layer 201 on the upper and lower edges of the VCSEL array is etched away by two mask etching processes to expose the upper DBR structure 105 and the lower DBR structure 102 of the VCSEL sub-array alternately. Leaving an insulating layer 201 deposited in the insulating channel between adjacent VCSEL subarrays. Subsequently, a metal electrode is sputtered on both the exposed lower DBR structure 102 and the upper DBR structure 105 as an n-type ohmic contact electrode 302. The surface of the n-type ohmic contact electrode 302 and the surface of the p-type ohmic contact electrode 301 are on the same horizontal plane, and a flat surface is maintained.
Preferably, the n-type ohmic contact electrode 302 material is 30nmAu +20nmGe +50 nmNi.
S5, as shown in fig. 6, a metal conductive layer 303 with a thickness of 20nm is sputtered on the surfaces of the p-type ohmic contact electrode 301 and the n-type ohmic contact electrode 302, and the p-type ohmic contact electrode 301 and the n-type ohmic contact electrode 302 are connected at their junctions to form conduction. Finally, the insulating layer 201 covering the surface of the VCSEL light-emitting hole is removed, and the upper DBR structure 105 is exposed.
Preferably, the material of the metal conducting layer is Au.
Example 2
As shown in fig. 1, an embodiment of the present invention provides an epitaxial wafer with a complete back-emitting VCSEL array light-emitting structure, which includes: an insulating substrate 101, a lower DBR structure 102, an active layer 103, an oxide layer 104, and an upper DBR structure 105. All VCSEL light emitting cells are connected by the lower DBR structure 102 forming a coplanar electrode.
Wherein the number of bragg mirror pairs of the lower DBR structure 102 is less than the number of bragg mirror pairs of the upper DBR structure 105.
The following describes a method for manufacturing a VCSEL array electrode structure according to the present invention, which includes the following steps:
s1, as shown in fig. 2, first, every M × n VCSEL light emitting units are used as a VCSEL sub-array, and adjacent VCSEL sub-arrays are etched to the insulating substrate 101 by a mask etching technique to form an insulating channel, where the channel width is 5 um. And the right side of the last VCSEL subarray is not etched back, and the original lower DBR structure is reserved. In this embodiment, M is 9, N is 6, and N is 2.
Preferably, the etching technique is an ICP dry etching technique.
S2, as shown in fig. 3, the insulating layer 201 is deposited on the surface of the VCSEL array mesa by a deposition process, and the insulating layer 201 is finally formed to have a thickness higher than that of the upper DBR structure 105.
Preferably, the insulating medium material is SiO2Or SiNx。
S3, removing the insulating layer 201 on the surface of the upper DBR structure 105 of the VCSEL light-emitting unit by using a mask etching process to expose the upper DBR structure 105 and the upper DBR structure 105 on the left side of the first VCSEL sub-array. Wherein an insulating layer 201 at the upper and lower edges of the VCSEL array remains. Subsequently, a metal electrode is sputtered on the exposed surface of the upper DBR structure 105 as the p-type ohmic contact electrode 301.
Preferably, the p-type ohmic contact electrode 301 is made of 10nmTi +50nmAu +30nmGe alloy material.
S4, as shown in fig. 5, the insulating layer 201 on the upper and lower edges of the VCSEL array is etched away by two mask etching processes to expose the upper DBR structure 105 and the lower DBR structure 102 of the VCSEL sub-array alternately. Leaving an insulating layer 201 deposited in the insulating channel between adjacent VCSEL subarrays. Subsequently, a metal electrode is sputtered on both the exposed lower DBR structure 102 and the upper DBR structure 105 as an n-type ohmic contact electrode 302. The surface of the n-type ohmic contact electrode 302 and the surface of the p-type ohmic contact electrode 301 are on the same horizontal plane, and a flat surface is maintained.
Preferably, the n-type ohmic contact electrode 302 material is 30nmAu +20nmGe +50 nmNi.
S5, as shown in fig. 6, a metal conductive layer 303 with a thickness of 20nm is sputtered on the surfaces of the p-type ohmic contact electrode 301 and the n-type ohmic contact electrode 302, and the p-type ohmic contact electrode 301 and the n-type ohmic contact electrode 302 are connected at their junctions to form conduction.
Preferably, the material of the metal conducting layer 303 is Au.
The invention has the advantages that:
according to the invention, an insulation channel is arranged on an original VCSEL light emitting array through a special etching process technology, and the original VCSEL light emitting array is divided into a plurality of VCSEL sub-arrays; the VCSEL light emitting units in the VCSEL sub-arrays are arranged in a parallel connection mode, and the VCSEL sub-arrays are arranged in a series connection mode; based on this, the invention effectively overcomes the difficulty of the small voltage and large current driving circuit required by the traditional high-power VCSEL array by adjusting the parallel driving mode of all the light-emitting units in the original VCSEL array to the mode of combining series connection and parallel connection, greatly reduces the driving current required by the high-power VCSEL array chip, reduces the requirement on the complexity of the driving circuit, and has important application value.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A VCSEL array electrode structure, comprising: the VCSEL light emitting array comprises M multiplied by N VCSEL light emitting units, and comprises an insulating substrate, a lower DBR structure, an active layer, an oxidation layer and an upper DBR structure from bottom to top;
the VCSEL light emitting array is divided into a plurality of VCSEL sub-arrays according to every m multiplied by n VCSEL light emitting units, an isolation channel etched to the insulating substrate is arranged between every two adjacent VCSEL sub-arrays, an insulating material is filled in the isolation channel to form an insulating layer, one end of each VCSEL sub-array is reserved with an upper DBR structure, and the other end of each VCSEL sub-array is etched to a lower DBR structure and is distributed in a staggered mode;
each VCSEL subarray is provided with an upper metal electrode connected with the upper DBR structure and a lower metal electrode connected with the lower DBR structure, and the upper metal electrode and the lower metal electrode of any VCSEL subarray are respectively connected with the lower metal electrode and the upper metal electrode of the adjacent VCSEL subarray to form series conduction.
2. The VCSEL array electrode structure of claim 1, wherein all of the VCSEL light emitting units are equally spaced.
3. The VCSEL array electrode structure of claim 1, wherein M is greater than or equal to 2, N is greater than or equal to 2, and M is less than or equal to M, N.
4. The VCSEL array electrode structure of claim 1, wherein in the VCSEL subarray, all of the VCSEL light emitting units are connected by a same lower DBR structure to form a coplanar electrode; and the number of the Bragg reflector pairs of the lower DBR structure is greater than that of the Bragg reflectors of the upper DBR structure.
5. The VCSEL array electrode structure of claim 1, wherein the insulating substrate comprises one of a GaAs substrate, a SiC substrate, and a SOI substrate, the insulating material comprising SiO2、SiNxOne of the materials, the upper metal electrode material or the lower metal electrode material comprises one or more of Al, Ti, Pt, Pb, Au, Cu, Ni and Ge to form an alloy material.
6. The VCSEL array electrode structure of claim 1, wherein the upper metal electrodes and the lower metal electrodes of two adjacent VCSEL subarrays are arranged in an alternating manner; the upper metal electrode of one VCSEL subarray is adjacent to the lower metal electrode of the other VCSEL subarray, and the lower metal electrode of one VCSEL subarray is adjacent to the upper metal electrode of the other VCSEL subarray.
7. The VCSEL array electrode structure of claim 1, wherein the upper and lower metal electrodes of the VCSEL subarray are connected to the lower and upper metal electrodes of the adjacent VCSEL subarray by gold plating or sputtering, and Au is deposited thereon to form a flat surface.
8. The VCSEL array electrode structure of claim 1, wherein after the VCSEL subarrays are connected in series, the unconnected top metal electrode is connected to a positive terminal of an external driving power source, and the unconnected bottom metal electrode is connected to a negative terminal of the external driving power source.
9. A method for fabricating the VCSEL array electrode structure of any of claims 1 to 8, comprising:
taking every m multiplied by n VCSEL light emitting units in the VCSEL light emitting array as a VCSEL sub-array, and etching the insulating substrate between the adjacent VCSEL sub-arrays to form an isolation channel;
depositing an insulating layer on the surface of the table top of the VCSEL light emitting array, wherein the thickness of the finally formed insulating layer is higher than that of the upper DBR structure;
removing the insulating layer on the surface of the upper DBR structure of the VCSEL light-emitting unit, exposing the upper DBR structure and the upper DBR structure at one end of the first VCSEL subarray, and reserving the insulating layer on the surface of the VCSEL light-emitting hole and the insulating layers at the upper edge and the lower edge of the VCSEL light-emitting array; sputtering a metal electrode on the surface of the exposed upper DBR structure;
etching to remove the insulating layers positioned at the upper edge and the lower edge of the VCSEL luminous array, and alternately exposing the upper DBR structure and the lower DBR structure of the VCSEL subarray; reserving an insulating layer deposited in an insulating channel between adjacent VCSEL subarrays; sputtering a lower metal electrode on the exposed lower DBR structure and the exposed upper DBR structure;
sputtering a metal conducting layer on the surfaces of the adjacent upper metal electrode and the lower metal electrode to realize connection and conduction; and finally, removing the insulating layer covered on the surface of the VCSEL light outlet hole to expose the upper DBR structure.
10. A method for fabricating the VCSEL array electrode structure of any of claims 1 to 8, comprising:
taking every m multiplied by n VCSEL light emitting units in the VCSEL light emitting array as a VCSEL sub-array, and etching the insulating substrate between the adjacent VCSEL sub-arrays to form an isolation channel;
depositing an insulating layer on the surface of the table top of the VCSEL light emitting array, wherein the thickness of the finally formed insulating layer is higher than that of the upper DBR structure;
removing the insulating layer on the surface of the upper DBR structure of the VCSEL light-emitting unit, exposing the upper DBR structure and the upper DBR structure at one end of the first VCSEL subarray, and reserving the insulating layers at the upper edge and the lower edge of the VCSEL light-emitting array; sputtering a metal electrode on the surface of the exposed upper DBR structure;
etching to remove the insulating layers positioned at the upper edge and the lower edge of the VCSEL luminous array, and alternately exposing the upper DBR structure and the lower DBR structure of the VCSEL subarray; reserving an insulating layer deposited in an insulating channel between adjacent VCSEL subarrays; sputtering a lower metal electrode on the exposed lower DBR structure and the exposed upper DBR structure;
and sputtering a metal conducting layer on the surfaces of the adjacent upper metal electrode and the lower metal electrode to realize connection and conduction.
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CN113659443A (en) * 2021-08-17 2021-11-16 苏州长光华芯光电技术股份有限公司 VCSEL array chip and preparation method thereof

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