CN112332848B - Low-power consumption comparator circuit with dynamically adjusted comparison time - Google Patents

Abstract

A low-power consumption comparator circuit with dynamically adjusted comparison time, wherein a positive input processing module inputs VIP and generates a first node signal which is connected to the input ends of a first inverter and a second inverter; the negative input processing module inputs VIN and generates a second node signal which is connected to the input ends of the third inverter and the fourth inverter, and inverters with different inversion threshold voltages are arranged, so that when VIP is larger than VIN, the voltage of the first node drops faster than the voltage of the second node, when the voltage of the first node is smaller than the inversion threshold voltage of the second inverter, and when the voltage of the second node is larger than the inversion threshold voltage of the third inverter, the positive output end of the comparator outputs high level; when VIP is smaller than VIN, the voltage of the first node is slower than the voltage of the second node, and when the voltage of the first node is larger than the turnover threshold voltage of the first inverter and the voltage of the second node is smaller than the turnover threshold voltage of the fourth inverter, the negative output end of the comparator outputs high level; and after the comparison result is obtained, the comparator circuit is turned off, so that the dynamic adjustment of comparison time is realized, and the power consumption is reduced.

Description

A low-power comparator circuit with dynamic adjustment of comparison time

technical field

The invention belongs to the technical field of analog integrated circuits, and relates to a low-power comparator circuit structure with dynamically adjusted comparison time, which can be applied to a successive approximation analog-to-digital converter (SAR ADC).

Background technique

Analog-to-digital converter (ADC) is an eternal topic in the design of analog integrated circuits, and comparators are widely used in analog-to-digital converters. In many application scenarios of human-computer interaction, the speed requirement of the ADC chip is not high, but the power consumption of the ADC chip is required to be low. Therefore, it is necessary for the design of low-power ADC, and the power consumption in the ADC comes from the comparator to a large extent. The power consumption of the Strong-Arm comparator mainly depends on the accuracy of the comparison. In order to compare the input difference is very small The signal requires a large input tube current, but when the input signal is very different, the input tube current is still very large. Therefore, the overall power consumption of the existing Strong-Arm comparator design is too large.

As shown in Figure 1, the traditional Strong-Arm comparator structure, when the clock signal CLK is low, the comparator is in the reset phase, MP1, MP2, MP3, MP4, MP5, MP6 conduction, nodes X, Y, OUTN , OUTP is reset to the power supply voltage VDD. When the clock signal CLK is at a high level, the comparator is in the comparison stage. If the input signal VIP>VIN, the voltage of node X drops faster than node Y, and then the voltage of node OUTN is also pulled down rapidly, and the voltage of node OUTN decrease, suppressing the conduction of MN4 and gradually turning on MP2, so that the voltage of node OUTP increases, and the increase of node OUTP voltage increases the conduction current of MN3, and inhibits the conduction of MP1, and finally the node OUTN outputs is low level, node OUTP output is high level. When the input voltage difference is small, this structure needs a large current to compare the correct results, but the power consumption when the input voltage difference is large is not much different from that when the input voltage difference is small. In the simulation, when the input voltage difference is 50mV, the power consumption is 15% lower than when the input difference is 50uV.

Contents of the invention

Aiming at the problem that the power consumption of the traditional comparator is not much different when the input voltage difference is large and the input voltage difference is small, the present invention proposes a comparator circuit whose comparison time can be dynamically adjusted with the input signal voltage difference. When the input signal difference is large, the comparison speed is fast, and the comparison end flag signal generated when the comparison is completed can be used to turn off the comparator, which can save a lot of power consumption compared with the traditional Strong-Arm comparator; it is suitable for speed requirements Not high systems, such as low-to-medium rate ADCs.

Technical scheme of the present invention is:

A low-power comparator circuit with dynamic adjustment of comparison time, including a positive input processing module, a negative input processing module and a comparison result extraction module,

The forward input processing module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first inverter and the second inverter,

The gate of the second NMOS transistor is used as the positive input terminal of the low-power comparator circuit, its source is connected to the drain of the first NMOS transistor, and its drain is connected to the drain of the first PMOS transistor as the first junction Connect the input terminals of the first inverter and the second inverter;

The gate of the first PMOS transistor is connected to the bias voltage, and its source is connected to the drain of the second PMOS transistor;

The gate of the third NMOS transistor is connected to the output terminal of the second inverter, its drain is connected to the drains of the fourth NMOS transistor and the third PMOS transistor, and the gates of the first NMOS transistor and the second PMOS transistor, and its source The pole is connected to the sources of the first NMOS transistor and the fourth NMOS transistor and grounded;

The gate of the third PMOS transistor is connected to the output terminal of the first inverter, and the source thereof is connected to the drain of the fourth PMOS transistor;

The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and connected to the clock signal, and its source is connected to the source of the second PMOS transistor and connected to the power supply voltage;

The negative input processing module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third inverter and the fourth inverter,

The gate of the sixth NMOS transistor is used as the negative input terminal of the low-power comparator circuit, its source is connected to the drain of the fifth NMOS transistor, and its drain is connected to the drain of the fifth PMOS transistor as the second junction The point is connected to the input terminals of the third inverter and the fourth inverter;

The gate of the fifth PMOS transistor is connected to the bias voltage, and its source is connected to the drain of the sixth PMOS transistor;

The gate of the seventh NMOS transistor is connected to the output terminal of the fourth inverter, and its drain is connected to the drains of the eighth NMOS transistor and the seventh PMOS transistor, and the gates of the fifth NMOS transistor and the sixth PMOS transistor, and its source The pole is connected to the sources of the fifth NMOS transistor and the eighth NMOS transistor and grounded;

The gate of the seventh PMOS transistor is connected to the output terminal of the third inverter, and the source thereof is connected to the drain of the eighth PMOS transistor;

The gate of the eighth PMOS transistor is connected to the gate of the eighth NMOS transistor and connected to the clock signal, and its source is connected to the source of the sixth PMOS transistor and connected to the power supply voltage;

The inversion threshold voltages of the first inverter and the third inverter are equal, and the inversion threshold voltages of the second inverter and the fourth inverter are equal and lower than the inversion threshold voltages of the first inverter and the third inverter ;

The module for taking out the comparison result includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor ,

The gates of the twelfth NMOS transistor and the tenth PMOS transistor are interconnected and connected to the output end of the first inverter, and the gates of the ninth NMOS transistor and the ninth PMOS transistor are interconnected and connected to the output end of the third inverter , the gate of the eleventh NMOS transistor is connected to the output end of the second inverter, and the gate of the fourteenth NMOS transistor is connected to the output end of the fourth inverter;

The gate of the tenth NMOS transistor is connected to the clock signal, and its drain is connected to the drain of the ninth NMOS transistor and the source of the eleventh NMOS transistor and used as the positive output terminal of the low-power comparator circuit;

The gate of the thirteenth NMOS transistor is connected to the clock signal, and its drain is connected to the drain of the twelfth NMOS transistor and the source of the fourteenth NMOS transistor and used as a negative output terminal of the low-power comparator circuit ;

The sources of the ninth NMOS transistor, the tenth NMOS transistor, the twelfth NMOS transistor and the thirteenth NMOS transistor are grounded;

The drain of the ninth PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the source thereof is connected to the power supply voltage;

The drain of the tenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source thereof is connected to the power supply voltage;

The signal at the positive input terminal of the low-power comparator circuit is different from the signal at the negative input terminal of the low-power comparator circuit, resulting in different speeds of voltage drop between the first node and the second node ;

If the positive input terminal signal of the low power consumption comparator circuit is greater than the negative input terminal signal of the low power consumption comparator circuit, the speed at which the voltage at the first node drops is lower than the voltage at the second node Fast speed, when the voltage of the first node is lower than the flipping threshold voltage of the second inverter and the voltage of the second node is larger than the flipping threshold voltage of the third inverter, the low power comparator The positive output terminal of the circuit outputs a high level, the negative output terminal of the low-power comparator circuit outputs a low level, and the low-power comparator circuit generates a comparison end flag signal;

If the positive input terminal signal of the low power consumption comparator circuit is smaller than the negative input terminal signal of the low power consumption comparator circuit, the speed at which the voltage at the second node drops is lower than that at which the voltage at the first node drops Fast speed, when the voltage of the first node is greater than the inversion threshold voltage of the first inverter and the voltage of the second node is less than the inversion threshold voltage of the fourth inverter, the low power comparator The positive output terminal of the circuit outputs a low level, the negative output terminal of the low-power comparator circuit outputs a high level, and the low-power comparator circuit generates a comparison end flag signal;

The comparison end flag signal is used to control the low power comparator circuit to stop working.

Specifically, the inversion threshold voltages of the first inverter and the third inverter are 0.9V, and the inversion threshold voltages of the second inverter and the fourth inverter are 0.2V.

The beneficial effects of the present invention are: the present invention causes the voltage drop speeds of the first node VO1 and the second node VO2 to be different according to the voltage difference between the positive input signal VIP and the negative input signal VIN, so that when the clock signal CLK is low During the flat period, the voltage difference between the first node VO1 and the second node VO2 continues to increase, and then the first node VO1 and the second node VO2 are connected to inverters with different flipping threshold voltages to obtain the comparison results, and after obtaining After the comparison result is generated, the comparison end flag signal is used to control the comparator to stop working, and realize the dynamic adjustment of the comparison time; the comparator proposed by the present invention has a fast comparison speed when the input signal difference is large, and the comparator is turned off immediately after the comparison is completed. , so compared with the traditional Strong-Arm comparator structure, it can save a lot of power consumption.

Description of drawings

Figure 1 is a circuit schematic diagram of a traditional Strong-Arm comparator.

FIG. 2 is a schematic diagram of the circuit structure of a positive input processing module and a negative input processing module in a low-power comparator circuit with dynamic adjustment of comparison time proposed by the present invention.

FIG. 3 is a schematic diagram of the circuit structure of a module for extracting comparison results in a low-power comparator circuit with dynamic adjustment of comparison time proposed by the present invention.

Fig. 4 is a schematic diagram of the simulation results of a low-power comparator circuit with dynamic adjustment of comparison time proposed by the present invention under the condition that the input voltage difference is 50mV, and the comparator compares the results in the third comparison cycle.

Fig. 5 is a schematic diagram of the simulation results of a low-power comparator circuit with dynamic adjustment of comparison time proposed by the present invention when the input voltage difference is 2mV, and the comparator compares the results in the 37th comparison cycle.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in detail below in conjunction with the accompanying drawings. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that in the present invention, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations Any such actual relationship or order exists between.

A low-power comparator circuit with dynamic adjustment of comparison time proposed by the present invention includes a positive input processing module, a negative input processing module, and a module for taking out comparison results. As shown in Figure 2, the positive input processing module includes a first NMOS Tube M1, second NMOS tube M2, third NMOS tube M5, fourth NMOS tube M6, first PMOS tube M3, second PMOS tube M4, third PMOS tube M7, fourth PMOS tube M8, first inverter INV1 and the second inverter INV2, the gate of the second NMOS transistor M2 is used as the positive input terminal of the low-power comparator circuit, its source is connected to the drain of the first NMOS transistor M1, and its drain is connected to the first PMOS The drain of the transistor M3 is connected to the input terminals of the first inverter INV1 and the second inverter INV2 as the first node VO1; the gate of the first PMOS transistor M3 is connected to the bias voltage VCM, and its source is connected to the second The drain of the PMOS transistor M4; the gate of the third NMOS transistor M5 is connected to the output terminal of the second inverter INV2, and its drain is connected to the drains of the fourth NMOS transistor M6 and the third PMOS transistor M7, and the first NMOS transistor The gates of M1 and the second PMOS transistor M4, the sources of which are connected to the sources of the first NMOS transistor M1 and the fourth NMOS transistor M6 and grounded; the gate of the third PMOS transistor M7 is connected to the output terminal of the first inverter INV1 , its source is connected to the drain of the fourth PMOS transistor M8; the gate of the fourth PMOS transistor M8 is connected to the gate of the fourth NMOS transistor M6 and connected to the clock signal CLK, its source is connected to the source of the second PMOS transistor M4 and Connect the mains voltage.

The present invention has a symmetrical structure, and the structure and working principle of the negative input processing module and the positive input processing module are similar. As shown in Figure 2, the negative input processing module includes a fifth NMOS transistor M9, a sixth NMOS transistor M10, a seventh NMOS transistor Tube M13, eighth NMOS tube M14, fifth PMOS tube M11, sixth PMOS tube M12, seventh PMOS tube M15, eighth PMOS tube M16, third inverter INV3 and fourth inverter INV4, sixth NMOS The gate of the tube M10 is used as the negative input terminal of the low-power comparator circuit, its source is connected to the drain of the fifth NMOS tube M9, and its drain is connected to the drain of the fifth PMOS tube M11 as the second node VO2 Connect the input terminals of the third inverter INV3 and the fourth inverter INV4; the gate of the fifth PMOS transistor M11 is connected to the bias voltage VCM, and its source is connected to the drain of the sixth PMOS transistor M12; the seventh NMOS transistor M13 Its gate is connected to the output terminal of the fourth inverter INV4, its drain is connected to the drains of the eighth NMOS transistor M14 and the seventh PMOS transistor M15, and the gates of the fifth NMOS transistor M9 and the sixth PMOS transistor M12, which The source is connected to the source of the fifth NMOS transistor M9 and the eighth NMOS transistor M14 and grounded; the gate of the seventh PMOS transistor M15 is connected to the output terminal of the third inverter INV3, and its source is connected to the drain of the eighth PMOS transistor M16 The gate of the eighth PMOS transistor M16 is connected to the gate of the eighth NMOS transistor M14 and connected to the clock signal CLK, and the source thereof is connected to the source of the sixth PMOS transistor M12 and connected to the power supply voltage.

The structure and working principle of the negative input processing module and the positive input processing module are similar, only the input and output signs are different, and the comparison result module is used to process the flag signals generated by the negative input processing module and the positive input processing module to obtain the comparator The final comparison result, as shown in Figure 3, the module for taking out the comparison result includes the ninth NMOS transistor M17, the tenth NMOS transistor M18, the eleventh NMOS transistor M19, the twelfth NMOS transistor M21, the thirteenth NMOS transistor M22, the tenth NMOS transistor The four NMOS transistors M23, the ninth PMOS transistor M20 and the tenth PMOS transistor M24, the gates of the twelfth NMOS transistor M21 and the tenth PMOS transistor M24 are interconnected and connected to the output end of the first inverter INV1, the ninth NMOS transistor The gates of M17 and the ninth PMOS transistor M20 are interconnected and connected to the output terminal of the third inverter INV3, the gate of the eleventh NMOS transistor M19 is connected to the output terminal of the second inverter INV2, and the gate of the fourteenth NMOS transistor M23 The gate of the tenth NMOS transistor M18 is connected to the output terminal of the fourth inverter INV4; the gate of the tenth NMOS transistor M18 is connected to the clock signal CLK, and its drain is connected to the drain of the ninth NMOS transistor M17 and the source of the eleventh NMOS transistor M19. As the positive output terminal of the low-power comparator circuit; the gate of the thirteenth NMOS transistor M22 is connected to the clock signal CLK, and its drain is connected to the drain of the twelfth NMOS transistor M21 and the source of the fourteenth NMOS transistor M23 And as the negative output terminal of the low-power comparator circuit; the sources of the ninth NMOS transistor M17, the tenth NMOS transistor M18, the twelfth NMOS transistor M21 and the thirteenth NMOS transistor M22 are grounded; the ninth PMOS transistor M20 The drain is connected to the drain of the eleventh NMOS transistor M19, and its source is connected to the power supply voltage; the drain of the tenth PMOS transistor M24 is connected to the drain of the fourteenth NMOS transistor M23, and its source is connected to the power supply voltage.

The working process and working principle of the present invention will be described in detail below.

The present invention uses comparators with different inversion threshold voltages, setting the inversion threshold voltages of the first inverter INV1 and the third inverter INV3 to be equal, and setting the inversion threshold voltages of the second inverter INV2 and the fourth inverter INV4 to be equal And less than the inversion threshold voltage of the first inverter INV1 and the third inverter INV3; in this embodiment, the power supply voltage is 1.1V, then the inversion threshold voltage of the first inverter INV1 and the third inverter INV3 is set to For a higher voltage of 0.9V, the inversion threshold voltage of the second inverter INV2 and the fourth inverter INV4 is set to a lower voltage of 0.2V as an example. Of course, other suitable values can also be used to set the inverters threshold voltage. Since the left and right parts of the comparator circuit of the present invention shown in Figures 2 and 3 are completely symmetrical, only the input and output signs are different, the following uses the positive input processing module on the left part and the corresponding output comparison result module as an example to illustrate the principle.

When the clock signal CLK is at a high level, the fourth PMOS transistor M8 is turned off, the fourth NMOS transistor M6 is turned on, and the voltage of the node CTRL1 (that is, the drain terminal of the fourth NMOS transistor M6) is pulled to 0, and the second PMOS transistor M6 is pulled to 0. Tube M4 conducts. The bias voltage VCM is used to make the first PMOS transistor M3 and the fifth PMOS transistor M11 constant conduction, which can be generated by the reference voltage source circuit. The bias voltage VCM can take different values, as long as the first PMOS transistor M3 and the fifth PMOS transistor M3 are guaranteed to be The PMOS transistor M11 needs to be turned on. In this embodiment, the bias voltage VCM is set to a lower level such as 550mV, the first PMOS transistor M3 is turned on, the voltage of the first node VO1 is pulled up to the power supply voltage VDD, and the node X1 (that is, the first inverter The output terminal of INV1), the voltage of node Y1 (that is, the output terminal of the second inverter INV2) is low.

When the clock signal CLK changes to a low level, the node CTRL1 is pulled high, then the second PMOS transistor M4 is turned off, the first NMOS transistor M1 is turned on, and the voltage of the first node VO1 begins to drop until the first node VO1 is less than the second The inversion threshold voltage (0.2V in this embodiment) of the two inverters INV2, at this time, the nodes X1 and Y1 are both 1, the node CTRL1 becomes 0, the second PMOS transistor M4 is turned on again, and the first NMOS transistor M4 is turned on again. M1 is turned off, and the voltage of the first node VO1 rises until the voltage of the first node VO1 is greater than the inversion threshold voltage (0.9V in this embodiment) of the first inverter INV1, the nodes X1 and Y1 are both 0, and the junction Point CTRL1 becomes 1, so the cycle repeats. The clock signal CLK is equivalent to a reset signal, and the comparator resets each time the clock signal CLK goes high, and then performs a comparison when the clock signal CLK is at a low level to obtain a comparison result.

因此，比较器正向输出信号DOP＝1，比较器负向输出信号DON＝0。The comparison process in the negative input processing module on the right is similar to the positive input processing module on the left, the difference lies in the positive input signal VIP input to the positive input processing module and the negative input signal VIN input to the negative input processing module The voltages of the first node VO1 and the second node VO2 drop at different speeds, so that in each cycle during which the clock signal CLK is low, the voltages of the first node VO1 and the second node VO2 The voltage difference keeps increasing. If VIP>VIN, the voltage of the first node VO1 drops faster than the voltage of the second node VO2, when the voltage of the first node VO1 is lower than 0.2V and the voltage of the second node VO2 is greater than 0.9V , the voltages of the output node X1 of the first inverter INV1 and the output node Y1 of the second inverter INV2 are high level 1, the output node X2 of the third inverter INV3, the voltage of the output node Y1 of the fourth inverter The output terminal node Y2 voltage of the phase device INV4 is all low level 0, which is used as the basis for the comparison completion, and the comparison result module shown in Figure 3 is used to generate the comparison result.

Therefore, the comparator outputs signal DOP=1 in positive direction, and the comparator outputs signal DON=0 in negative direction.

Conversely, if VIP<VIN, the voltage drop rate of the first node VO1 is slower than that of the second node voltage VO2. When it is greater than 0.9V, the comparator output signal DOP=0 in positive direction, and the comparator output signal DON=1 in negative direction.

After the comparison result is obtained, the comparator circuit generates a comparison end flag signal, which is used to turn off the transistor in the comparator circuit, thereby controlling the low-power comparator circuit to stop working, so as to save power consumption. Illustrate in conjunction with emulation, as Fig. 4 and Fig. 5 are the emulation result figures of the present invention, wherein Fig. 4 is the situation that the input voltage difference of comparator is 50mV, it can be seen that comparator compares result in the 3rd comparison cycle; Figure 5 shows the situation where the input voltage difference of the comparator is 2mV, it can be seen that the comparator compares the result in the 37th comparison cycle. After the comparison result is obtained, the comparator does not need to recirculate the comparison within a cycle of the clock signal CLK. The present invention proposes to generate a flag signal that the comparison of the comparator is completed when DOP or DON is flipped to 1, and the flag signal can be compared by a logic circuit. The transistor in the comparator is turned off, thereby dynamically adjusting the power consumption of the comparator. Therefore, the comparator structure proposed by the present invention can realize very low power consumption when the input voltage difference is relatively large. Here, it is only about 1/10 of that when the input differential voltage is small, and in the traditional comparator design, its power consumption has little relationship with the input differential signal (the difference is only 16% in the simulation), and the purpose of saving power consumption cannot be achieved.

The power consumption of a traditional Strong-Arm comparator mainly depends on the comparison accuracy. In order to compare signals with small input differences, a large input tube current is required. However, when the input signals differ greatly, the input tube current is still very large. Therefore, the overall power consumption of the traditional comparator design is too large. However, the present invention proposes a comparator circuit structure that dynamically adjusts the comparison time to reduce power consumption. The output result of the present invention is a digital signal, so the digital signal can be used to disconnect the transistor in the comparator after comparing the result, so that the comparator The device stops working, so that the comparison time can be adjusted dynamically. The invention can quickly compare the results and stop the comparator when the input signal difference is large, and greatly reduces the power consumption of the comparator.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (2)

1. A low-power comparator circuit with dynamically adjusted comparison time, characterized in that it includes a positive input processing module, a negative input processing module and a comparison result module, The forward input processing module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first inverter and the second inverter, The gate of the second NMOS transistor is used as the positive input terminal of the low-power comparator circuit, its source is connected to the drain of the first NMOS transistor, and its drain is connected to the drain of the first PMOS transistor as the first junction Connect the input terminals of the first inverter and the second inverter; The gate of the first PMOS transistor is connected to the bias voltage, and its source is connected to the drain of the second PMOS transistor; The gate of the third NMOS transistor is connected to the output terminal of the second inverter, its drain is connected to the drains of the fourth NMOS transistor and the third PMOS transistor, and the gates of the first NMOS transistor and the second PMOS transistor, and its source The pole is connected to the sources of the first NMOS transistor and the fourth NMOS transistor and grounded; The gate of the third PMOS transistor is connected to the output terminal of the first inverter, and the source thereof is connected to the drain of the fourth PMOS transistor; The gate of the fourth PMOS transistor is connected to the gate of the fourth NMOS transistor and connected to the clock signal, and its source is connected to the source of the second PMOS transistor and connected to the power supply voltage; The negative input processing module includes a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third inverter and the fourth inverter, The gate of the sixth NMOS transistor is used as the negative input terminal of the low-power comparator circuit, its source is connected to the drain of the fifth NMOS transistor, and its drain is connected to the drain of the fifth PMOS transistor as the second junction The point is connected to the input terminals of the third inverter and the fourth inverter; The gate of the fifth PMOS transistor is connected to the bias voltage, and its source is connected to the drain of the sixth PMOS transistor; The gate of the seventh NMOS transistor is connected to the output terminal of the fourth inverter, and its drain is connected to the drains of the eighth NMOS transistor and the seventh PMOS transistor, and the gates of the fifth NMOS transistor and the sixth PMOS transistor, and its source The pole is connected to the sources of the fifth NMOS transistor and the eighth NMOS transistor and grounded; The gate of the seventh PMOS transistor is connected to the output terminal of the third inverter, and the source thereof is connected to the drain of the eighth PMOS transistor; The gate of the eighth PMOS transistor is connected to the gate of the eighth NMOS transistor and connected to the clock signal, and its source is connected to the source of the sixth PMOS transistor and connected to the power supply voltage; The inversion threshold voltages of the first inverter and the third inverter are equal, and the inversion threshold voltages of the second inverter and the fourth inverter are equal and lower than the inversion threshold voltages of the first inverter and the third inverter ; The module for taking out the comparison result includes a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a ninth PMOS transistor, and a tenth PMOS transistor , The gates of the twelfth NMOS transistor and the tenth PMOS transistor are interconnected and connected to the output end of the first inverter, and the gates of the ninth NMOS transistor and the ninth PMOS transistor are interconnected and connected to the output end of the third inverter , the gate of the eleventh NMOS transistor is connected to the output end of the second inverter, and the gate of the fourteenth NMOS transistor is connected to the output end of the fourth inverter; The gate of the tenth NMOS transistor is connected to the clock signal, and its drain is connected to the drain of the ninth NMOS transistor and the source of the eleventh NMOS transistor and used as the positive output terminal of the low-power comparator circuit; The gate of the thirteenth NMOS transistor is connected to the clock signal, and its drain is connected to the drain of the twelfth NMOS transistor and the source of the fourteenth NMOS transistor and used as a negative output terminal of the low-power comparator circuit ; The sources of the ninth NMOS transistor, the tenth NMOS transistor, the twelfth NMOS transistor and the thirteenth NMOS transistor are grounded; The drain of the ninth PMOS transistor is connected to the drain of the eleventh NMOS transistor, and the source thereof is connected to the power supply voltage; The drain of the tenth PMOS transistor is connected to the drain of the fourteenth NMOS transistor, and the source thereof is connected to the power supply voltage; The signal at the positive input terminal of the low-power comparator circuit is different from the signal at the negative input terminal of the low-power comparator circuit, resulting in different speeds of voltage drop between the first node and the second node ; If the positive input terminal signal of the low power consumption comparator circuit is greater than the negative input terminal signal of the low power consumption comparator circuit, the speed at which the voltage at the first node drops is lower than the voltage at the second node Fast speed, when the voltage of the first node is lower than the flipping threshold voltage of the second inverter and the voltage of the second node is larger than the flipping threshold voltage of the third inverter, the low power comparator The positive output terminal of the circuit outputs a high level, the negative output terminal of the low-power comparator circuit outputs a low level, and the low-power comparator circuit generates a comparison end flag signal; If the positive input terminal signal of the low power consumption comparator circuit is smaller than the negative input terminal signal of the low power consumption comparator circuit, the speed at which the voltage at the second node drops is lower than that at which the voltage at the first node drops Fast speed, when the voltage of the first node is greater than the inversion threshold voltage of the first inverter and the voltage of the second node is less than the inversion threshold voltage of the fourth inverter, the low power comparator The positive output terminal of the circuit outputs a low level, the negative output terminal of the low-power comparator circuit outputs a high level, and the low-power comparator circuit generates a comparison end flag signal; The comparison end flag signal is used to control the low power comparator circuit to stop working. 2. The low-power comparator circuit with dynamic adjustment of comparison time according to claim 1, wherein the flipping threshold voltage of the first inverter and the third inverter is 0.9V, and the second inverter and the third inverter The flipping threshold voltage of the fourth inverter is 0.2V.

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