CN112332848B - Low-power consumption comparator circuit with dynamically adjusted comparison time - Google Patents

Abstract

A low-power consumption comparator circuit with dynamically adjusted comparison time, wherein a positive input processing module inputs VIP and generates a first node signal which is connected to the input ends of a first inverter and a second inverter; the negative input processing module inputs VIN and generates a second node signal which is connected to the input ends of the third inverter and the fourth inverter, and inverters with different inversion threshold voltages are arranged, so that when VIP is larger than VIN, the voltage of the first node drops faster than the voltage of the second node, when the voltage of the first node is smaller than the inversion threshold voltage of the second inverter, and when the voltage of the second node is larger than the inversion threshold voltage of the third inverter, the positive output end of the comparator outputs high level; when VIP is smaller than VIN, the voltage of the first node is slower than the voltage of the second node, and when the voltage of the first node is larger than the turnover threshold voltage of the first inverter and the voltage of the second node is smaller than the turnover threshold voltage of the fourth inverter, the negative output end of the comparator outputs high level; and after the comparison result is obtained, the comparator circuit is turned off, so that the dynamic adjustment of comparison time is realized, and the power consumption is reduced.

Description

Low-power consumption comparator circuit with dynamically adjusted comparison time

Technical Field

The invention belongs to the technical field of analog integrated circuits, and relates to a low-power consumption comparator circuit structure with a comparison time dynamically adjusted, which can be applied to a successive approximation analog-to-digital converter (SAR ADC).

Background

Analog-to-digital converters (ADCs) are a constant topic in analog integrated circuit design, and comparators are widely used in analog-to-digital converters. In many application scenarios of man-machine interaction, the speed requirement on the ADC chip is not high, but the power consumption of the ADC chip is required to be low. Therefore, for low power ADC designs it is necessary that the power consumption in the ADC is largely from the comparator, and the power consumption of the Strong-Arm comparator is mainly dependent on the comparison accuracy, in order to compare signals with small input differences, a large input tube current is required, however when the input signals differ significantly, the input tube current is still large. Therefore, existing Strong-Arm comparator designs have a large overall power consumption.

As shown in fig. 1, which shows a conventional Strong-Arm comparator structure, when the clock signal CLK is at a low level, the comparator is in a reset phase, MP1, MP2, MP3, MP4, MP5, MP6 are turned on, and the node X, Y, OUTN, OUTP is reset to the power supply voltage VDD. When the clock signal CLK is at a high level, the comparator is in a comparison stage, if the input signal VIP > VIN, the voltage of the node X is faster than the voltage of the node Y, then the voltage of the node OUTN is also rapidly pulled down, the voltage of the node OUTN is reduced, the conduction of MN4 is inhibited and MP2 is gradually turned on, so that the voltage of the node OUTP is increased, the conduction current of MN3 is increased, the conduction of MP1 is inhibited, the output of the node OUTN is at a low level, and the output of the node OUTP is at a high level. This configuration requires a large current to compare the correct results when the input voltage difference is small, but the power consumption is not much different from when the input voltage difference is large. In the simulation, the power consumption was 15% lower when the input voltage difference was 50mV than when the input difference was 50 uV.

Disclosure of Invention

Aiming at the problem that the power consumption of the traditional comparator is not great when the input voltage difference is large and the input voltage difference is small, the invention provides a comparator circuit, the comparison time of which can be dynamically adjusted along with the voltage difference of the input signals, when the input signal difference of the comparator is large, the comparison speed is high, a comparison ending mark signal generated when the comparison is finished can be used for turning off the comparator, and compared with the traditional Strong-Arm comparator, a great amount of power consumption can be saved; is suitable for systems with low requirements on speed, such as an ADC with medium and low speed.

The technical scheme of the invention is as follows:

a low-power consumption comparator circuit with dynamically adjusted comparison time comprises a positive input processing module, a negative input processing module and a comparison result taking-out module,

the positive input processing module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first inverter and a second inverter,

the grid electrode of the second NMOS tube is used as the positive input end of the low-power consumption comparator circuit, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube and used as a first node to be connected with the input ends of the first inverter and the second inverter;

the grid electrode of the first PMOS tube is connected with bias voltage, and the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube;

the grid electrode of the third NMOS tube is connected with the output end of the second inverter, the drain electrodes of the third NMOS tube and the third PMOS tube are connected with the drain electrodes of the first NMOS tube and the second PMOS tube, and the source electrodes of the third NMOS tube and the second PMOS tube are connected with the source electrodes of the first NMOS tube and the fourth NMOS tube and are grounded;

the grid electrode of the third PMOS tube is connected with the output end of the first inverter, and the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube;

the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected with a clock signal, and the source electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a power supply voltage;

the negative input processing module comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third inverter and a fourth inverter,

the grid electrode of the sixth NMOS tube is used as the negative input end of the low-power consumption comparator circuit, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube and used as a second node to be connected with the input ends of the third inverter and the fourth inverter;

the grid electrode of the fifth PMOS tube is connected with bias voltage, and the source electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube;

the grid electrode of the seventh NMOS tube is connected with the output end of the fourth inverter, the drain electrodes of the seventh NMOS tube and the seventh PMOS tube are connected with the drain electrodes of the fifth NMOS tube and the sixth PMOS tube, and the source electrodes of the seventh NMOS tube and the eighth NMOS tube are connected with the source electrodes of the fifth NMOS tube and the eighth NMOS tube and are grounded;

the grid electrode of the seventh PMOS tube is connected with the output end of the third inverter, and the source electrode of the seventh PMOS tube is connected with the drain electrode of the eighth PMOS tube;

the grid electrode of the eighth PMOS tube is connected with the grid electrode of the eighth NMOS tube and is connected with a clock signal, and the source electrode of the eighth PMOS tube is connected with the source electrode of the sixth PMOS tube and is connected with a power supply voltage;

the inversion threshold voltages of the first inverter and the third inverter are equal, and the inversion threshold voltages of the second inverter and the fourth inverter are equal and smaller than the inversion threshold voltages of the first inverter and the third inverter;

the module for taking out the comparison result comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube and a tenth PMOS tube,

the grid electrode of the twelfth NMOS tube and the grid electrode of the tenth PMOS tube are connected with each other and are connected with the output end of the first inverter, the grid electrode of the ninth NMOS tube and the grid electrode of the ninth PMOS tube are connected with the output end of the third inverter, the grid electrode of the eleventh NMOS tube is connected with the output end of the second inverter, and the grid electrode of the fourteenth NMOS tube is connected with the output end of the fourth inverter;

the grid electrode of the tenth NMOS tube is connected with the clock signal, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the ninth NMOS tube and the source electrode of the eleventh NMOS tube and is used as the positive output end of the low-power consumption comparator circuit;

the grid electrode of the thirteenth NMOS tube is connected with the clock signal, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube and the source electrode of the fourteenth NMOS tube and is used as the negative output end of the low-power consumption comparator circuit;

the sources of the ninth NMOS tube, the tenth NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube are grounded;

the drain electrode of the ninth PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the source electrode of the ninth PMOS tube is connected with the power supply voltage;

the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube, and the source electrode of the tenth PMOS tube is connected with the power supply voltage;

the positive input end signal of the low-power consumption comparator circuit is different from the negative input end signal of the low-power consumption comparator circuit, so that the voltage falling speeds of the first node and the second node are different;

if the positive input end signal of the low-power consumption comparator circuit is larger than the negative input end signal of the low-power consumption comparator circuit, the voltage of the first node drops faster than the voltage of the second node, when the voltage of the first node is smaller than the turnover threshold voltage of the second inverter and the voltage of the second node is larger than the turnover threshold voltage of the third inverter, the positive output end of the low-power consumption comparator circuit outputs high level, the negative output end of the low-power consumption comparator circuit outputs low level, and the low-power consumption comparator circuit generates a comparison end mark signal;

if the positive input end signal of the low-power consumption comparator circuit is smaller than the negative input end signal of the low-power consumption comparator circuit, the voltage of the second node drops faster than the voltage of the first node, when the voltage of the first node is larger than the turnover threshold voltage of the first inverter and the voltage of the second node is smaller than the turnover threshold voltage of the fourth inverter, the positive output end of the low-power consumption comparator circuit outputs a low level, the negative output end of the low-power consumption comparator circuit outputs a high level, and the low-power consumption comparator circuit generates a comparison end mark signal;

and the comparison ending mark signal is used for controlling the low-power consumption comparator circuit to stop working.

Specifically, the inversion threshold voltages of the first inverter and the third inverter are 0.9V, and the inversion threshold voltages of the second inverter and the fourth inverter are 0.2V.

The beneficial effects of the invention are as follows: according to the invention, according to the difference of voltages of a positive input signal VIP and a negative input signal VIN, the voltage falling speeds of a first node VO1 and a second node VO2 are different, so that the voltage difference between the first node VO1 and the second node VO2 is continuously increased during the period that a clock signal CLK is in a low level, then the first node VO1 and the second node VO2 are connected with inverters with different turnover threshold voltages to obtain a comparison result, and after the comparison result is obtained, a comparison end mark signal is generated, the comparison result is used for controlling a comparator to stop working, so that the dynamic adjustment of comparison time is realized; the comparator provided by the invention has high comparison speed when the input signal difference value is large, and the comparator is turned off immediately after comparison is finished, so that a great amount of power consumption can be saved compared with the traditional Strong-Arm comparator structure.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional Strong-Arm comparator.

Fig. 2 is a schematic circuit diagram of a positive input processing module and a negative input processing module in a low-power comparator circuit with dynamically adjusted comparison time according to the present invention.

Fig. 3 is a schematic circuit diagram of a comparison result module taken out from a low-power comparator circuit with dynamically adjusted comparison time according to the present invention.

FIG. 4 is a schematic diagram showing simulation results of a low power comparator circuit with dynamically adjusted comparison time under the condition that the input voltage difference is 50mV, wherein the comparator compares the results in the 3 rd comparison cycle.

FIG. 5 is a schematic diagram showing simulation results of a low power comparator circuit with dynamically adjusted comparison time under the condition that the input voltage difference is 2mV, and the comparator compares the results in the 37 th comparison cycle.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that in the present invention, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The invention provides a low-power consumption comparator circuit with dynamically adjusted comparison time, which comprises a positive input processing module, a negative input processing module and a comparison result taking module, wherein the positive input processing module comprises a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M5, a fourth NMOS tube M6, a first PMOS tube M3, a second PMOS tube M4, a third PMOS tube M7, a fourth PMOS tube M8, a first inverter INV1 and a second inverter INV2, as shown in figure 2, the grid electrode of the second NMOS tube M2 is used as the positive input end of the low-power consumption comparator circuit, the source electrode of the second NMOS tube M2 is connected with the drain electrode of the first NMOS tube M1, the drain electrode of the second NMOS tube M5 is connected with the drain electrode of the first PMOS tube M3 and used as a first node VO1 to be connected with the input ends of the first inverter INV1 and the second inverter INV 2; the grid electrode of the first PMOS tube M3 is connected with the bias voltage VCM, and the source electrode of the first PMOS tube M3 is connected with the drain electrode of the second PMOS tube M4; the grid electrode of the third NMOS tube M5 is connected with the output end of the second inverter INV2, the drain electrodes of the third NMOS tube M6 and the third PMOS tube M7 are connected with the drain electrodes of the first NMOS tube M1 and the second PMOS tube M4, and the source electrodes of the third NMOS tube M5 are connected with the source electrodes of the first NMOS tube M1 and the fourth NMOS tube M6 and are grounded; the grid electrode of the third PMOS tube M7 is connected with the output end of the first inverter INV1, and the source electrode of the third PMOS tube M7 is connected with the drain electrode of the fourth PMOS tube M8; the gate of the fourth PMOS transistor M8 is connected to the gate of the fourth NMOS transistor M6 and to the clock signal CLK, and the source thereof is connected to the source of the second PMOS transistor M4 and to the power supply voltage.

The invention is a symmetrical structure, the structure and working principle of the negative input processing module and the positive input processing module are similar, as shown in figure 2, the negative input processing module comprises a fifth NMOS tube M9, a sixth NMOS tube M10, a seventh NMOS tube M13, an eighth NMOS tube M14, a fifth PMOS tube M11, a sixth PMOS tube M12, a seventh PMOS tube M15, an eighth PMOS tube M16, a third inverter INV3 and a fourth inverter INV4, the grid electrode of the sixth NMOS tube M10 is used as the negative input end of the low-power consumption comparator circuit, the source electrode of the sixth NMOS tube M10 is connected with the drain electrode of the fifth NMOS tube M9, the drain electrode of the sixth NMOS tube M11 is connected with the drain electrode of the fifth PMOS tube M11 and used as a second node VO2 to be connected with the input ends of the third inverter INV3 and the fourth inverter INV 4; the grid electrode of the fifth PMOS tube M11 is connected with the bias voltage VCM, and the source electrode of the fifth PMOS tube M11 is connected with the drain electrode of the sixth PMOS tube M12; the grid electrode of the seventh NMOS tube M13 is connected with the output end of the fourth inverter INV4, the drain electrodes of the seventh NMOS tube M14 and the seventh PMOS tube M15 are connected with the drain electrodes of the fifth NMOS tube M9 and the sixth PMOS tube M12, and the source electrodes of the seventh NMOS tube M13 and the eighth NMOS tube M14 are connected with the source electrodes of the fifth NMOS tube M9 and the eighth NMOS tube M14 and are grounded; the grid electrode of the seventh PMOS tube M15 is connected with the output end of the third inverter INV3, and the source electrode of the seventh PMOS tube M16 is connected with the drain electrode of the eighth PMOS tube M16; the gate of the eighth PMOS transistor M16 is connected to the gate of the eighth NMOS transistor M14 and to the clock signal CLK, and the source thereof is connected to the source of the sixth PMOS transistor M12 and to the power supply voltage.

The negative input processing module and the positive input processing module have similar structures and working principles, only have different input and output marks, the extraction comparison result module is used for processing mark signals generated by the negative input processing module and the positive input processing module to obtain a final comparison result of the comparator, as shown in fig. 3, the extraction comparison result module comprises a ninth NMOS tube M17, a tenth NMOS tube M18, an eleventh NMOS tube M19, a twelfth NMOS tube M21, a thirteenth NMOS tube M22, a fourteenth NMOS tube M23, a ninth PMOS tube M20 and a tenth PMOS tube M24, the grids of the twelfth NMOS tube M21 and the tenth PMOS tube M24 are connected with each other and are connected with the output end of the first inverter INV1, the grids of the ninth NMOS tube M17 and the ninth PMOS tube M20 are connected with the output end of the third inverter INV3, the grids of the eleventh NMOS tube M19 are connected with the output end of the second inverter INV2, and the grids of the fourteenth NMOS tube M23 are connected with the output end of the fourth inverter INV 4; the grid electrode of the tenth NMOS tube M18 is connected with a clock signal CLK, and the drain electrode of the tenth NMOS tube M17 and the source electrode of the eleventh NMOS tube M19 are connected and used as the positive output end of the low-power consumption comparator circuit; the grid electrode of the thirteenth NMOS tube M22 is connected with a clock signal CLK, and the drain electrode of the thirteenth NMOS tube M21 and the source electrode of the fourteenth NMOS tube M23 are connected and used as negative output ends of the low-power consumption comparator circuit; the sources of the ninth NMOS tube M17, the tenth NMOS tube M18, the twelfth NMOS tube M21 and the thirteenth NMOS tube M22 are grounded; the drain electrode of the ninth PMOS tube M20 is connected with the drain electrode of the eleventh NMOS tube M19, and the source electrode of the ninth PMOS tube M20 is connected with the power supply voltage; the drain electrode of the tenth PMOS tube M24 is connected with the drain electrode of the fourteenth NMOS tube M23, and the source electrode thereof is connected with the power supply voltage.

The working process and working principle of the present invention are described in detail below.

The invention uses comparators with different inversion threshold voltages, sets the inversion threshold voltages of the first inverter INV1 and the third inverter INV3 to be equal, and sets the inversion threshold voltages of the second inverter INV2 and the fourth inverter INV4 to be equal and smaller than the inversion threshold voltages of the first inverter INV1 and the third inverter INV 3; in this embodiment, taking the power supply voltage of 1.1V, the inversion threshold voltages of the first inverter INV1 and the third inverter INV3 are set to be 0.9V, and the inversion threshold voltages of the second inverter INV2 and the fourth inverter INV4 are set to be 0.2V, which is an example, however, other suitable values may be used to set the inverter threshold voltages. Since the left and right parts of the comparator circuit of the present invention shown in fig. 2 and 3 are completely symmetrical, only the input/output marks are different, and the principle is described below by taking the forward input processing module and the corresponding comparison result taking module on the left part as an example.

When the clock signal CLK is at a high level, the fourth PMOS transistor M8 is turned off, the fourth NMOS transistor M6 is turned on, the voltage of the node CTRL1 (i.e., the drain terminal of the fourth NMOS transistor M6) is pulled to 0, and the second PMOS transistor M4 is turned on. The bias voltage VCM is used for enabling the first PMOS transistor M3 and the fifth PMOS transistor M11 to be constantly conducted, and can be generated by the reference voltage source circuit, and the bias voltage VCM can take different values as long as the first PMOS transistor M3 and the fifth PMOS transistor M11 are guaranteed to be conducted. In this embodiment, the bias voltage VCM is set to a lower level, such as 550mV, the first PMOS transistor M3 is turned on, the voltage of the first node VO1 is pulled up to the power voltage VDD, and the voltages of the node X1 (i.e., the output terminal of the first inverter INV 1) and the node Y1 (i.e., the output terminal of the second inverter INV 2) are set to be low.

When the clock signal CLK changes to a low level, the node CTRL1 is pulled high, then the second PMOS transistor M4 is turned off, the first NMOS transistor M1 is turned on, the voltage of the first node VO1 starts to decrease until the voltage of the first node VO1 is less than the inversion threshold voltage (0.2V in this embodiment) of the second inverter INV2, at this time, the nodes X1 and Y1 are both 1, the node CTRL1 becomes 0, the second PMOS transistor M4 is turned on again, the first NMOS transistor M1 is turned off, the voltage of the first node VO1 increases until the voltage of the first node VO1 is greater than the inversion threshold voltage (0.9V in this embodiment) of the first inverter INV1, the voltages of the nodes X1 and Y1 are both 0, the node CTRL1 becomes 1, and the cycle repeats. The clock signal CLK corresponds to a reset signal, and the comparator is reset each time the clock signal CLK is turned high, and then the comparison is performed during the period when the clock signal CLK is at a low level to obtain a comparison result.

The comparison process in the negative input processing module of the right part is similar to that of the positive input processing module of the left part, and the difference is that the positive input signal VIP input by the positive input processing module is different from the negative input signal VIN input by the negative input processing module, so that the first node VOThe voltage of 1 is different from the voltage of the second node VO2, so that the voltage difference between the first node VO1 and the second node VO2 is increased every cycle during which the clock signal CLK is low. If VIP>VIN, the voltage of the first node VO1 drops faster than the voltage of the second node VO2, when the voltage of the first node VO1 is less than 0.2V and the voltage of the second node VO2 is greater than 0.9V, the voltages of the output node X1 of the first inverter INV1 and the output node Y1 of the second inverter INV2 are both at high level 1, the voltages of the output node X2 of the third inverter INV3 and the output node Y2 of the fourth inverter INV4 are both at low level 0, which is used as a basis for comparison completion, and the comparison result is generated by using the extraction comparison result module shown in fig. 3,

thus, the comparator outputs the signal dop=1 in the positive direction and the signal don=0 in the negative direction.

Conversely, if VIP < VIN, the voltage at the first node VO1 drops slower than the voltage at the second node VO2, and when the voltage at the second node VO2 drops below 0.2V and the voltage at the first node VO1 exceeds 0.9V, the comparator outputs a positive output signal dop=0 and the comparator outputs a negative output signal don=1.

After the comparison result is obtained, the comparator circuit generates a comparison ending mark signal for turning off a transistor in the comparator circuit, so that the low-power consumption comparator circuit is controlled to stop working, and the purpose of saving power consumption is achieved. Referring to fig. 4 and 5, wherein fig. 4 is a diagram showing simulation results of the present invention, and fig. 4 is a diagram showing a case that an input voltage difference of the comparator is 50mV, it can be seen that the comparator compares the results in the 3 rd comparison cycle; fig. 5 shows the input voltage difference of the comparator 2mV, and it can be seen that the comparator compares the result in the 37 th comparison cycle. After the comparison result is obtained, the comparator does not need to carry out recirculation comparison in the period of one clock signal CLK, and the invention proposes that a sign signal which is compared by the comparator is generated when DOP or DON is turned to 1, and the sign signal can turn off a transistor in the comparator through a logic circuit so as to dynamically adjust the power consumption of the comparator, so that the comparator structure provided by the invention can realize very low power consumption when the input voltage difference value is larger. Only about 1/10 of the input differential voltage is smaller, but in the traditional comparator design, the power consumption is not greatly related to the magnitude of the input differential signal (only 16% of the difference in simulation), and the purpose of saving the power consumption cannot be achieved.

The power consumption of the conventional Strong-Arm comparator mainly depends on the comparison precision, and in order to compare signals with small input differences, a large input tube current is required, however, when the input signals have large differences, the input tube current is still large. The overall power consumption of conventional comparator designs is therefore large. The invention provides a comparator circuit structure for dynamically adjusting the comparison time to reduce the power consumption, and the output result of the invention is a digital signal, so that after the comparison result is obtained, a transistor in the comparator can be disconnected by the digital signal, the comparator stops working, and the comparison time can be dynamically adjusted. The invention can quickly compare the result and stop the comparator when the input signal difference is larger, thereby greatly reducing the power consumption of the comparator.

Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.

Claims (2)

1. A low-power consumption comparator circuit with dynamically adjusted comparison time is characterized by comprising a positive input processing module, a negative input processing module and a comparison result taking-out module,

the positive input processing module comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first inverter and a second inverter,

the grid electrode of the second NMOS tube is used as the positive input end of the low-power consumption comparator circuit, the source electrode of the second NMOS tube is connected with the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the first PMOS tube and used as a first node to be connected with the input ends of the first inverter and the second inverter;

the grid electrode of the first PMOS tube is connected with bias voltage, and the source electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube;

the grid electrode of the third NMOS tube is connected with the output end of the second inverter, the drain electrodes of the third NMOS tube and the third PMOS tube are connected with the drain electrodes of the first NMOS tube and the second PMOS tube, and the source electrodes of the third NMOS tube and the second PMOS tube are connected with the source electrodes of the first NMOS tube and the fourth NMOS tube and are grounded;

the grid electrode of the third PMOS tube is connected with the output end of the first inverter, and the source electrode of the third PMOS tube is connected with the drain electrode of the fourth PMOS tube;

the grid electrode of the fourth PMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected with a clock signal, and the source electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a power supply voltage;

the negative input processing module comprises a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third inverter and a fourth inverter,

the grid electrode of the sixth NMOS tube is used as the negative input end of the low-power consumption comparator circuit, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the fifth PMOS tube and used as a second node to be connected with the input ends of the third inverter and the fourth inverter;

the grid electrode of the fifth PMOS tube is connected with bias voltage, and the source electrode of the fifth PMOS tube is connected with the drain electrode of the sixth PMOS tube;

the grid electrode of the seventh NMOS tube is connected with the output end of the fourth inverter, the drain electrodes of the seventh NMOS tube and the seventh PMOS tube are connected with the drain electrodes of the fifth NMOS tube and the sixth PMOS tube, and the source electrodes of the seventh NMOS tube and the eighth NMOS tube are connected with the source electrodes of the fifth NMOS tube and the eighth NMOS tube and are grounded;

the grid electrode of the seventh PMOS tube is connected with the output end of the third inverter, and the source electrode of the seventh PMOS tube is connected with the drain electrode of the eighth PMOS tube;

the grid electrode of the eighth PMOS tube is connected with the grid electrode of the eighth NMOS tube and is connected with a clock signal, and the source electrode of the eighth PMOS tube is connected with the source electrode of the sixth PMOS tube and is connected with a power supply voltage;

the inversion threshold voltages of the first inverter and the third inverter are equal, and the inversion threshold voltages of the second inverter and the fourth inverter are equal and smaller than the inversion threshold voltages of the first inverter and the third inverter;

the module for taking out the comparison result comprises a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a ninth PMOS tube and a tenth PMOS tube,

the grid electrode of the twelfth NMOS tube and the grid electrode of the tenth PMOS tube are connected with each other and are connected with the output end of the first inverter, the grid electrode of the ninth NMOS tube and the grid electrode of the ninth PMOS tube are connected with the output end of the third inverter, the grid electrode of the eleventh NMOS tube is connected with the output end of the second inverter, and the grid electrode of the fourteenth NMOS tube is connected with the output end of the fourth inverter;

the grid electrode of the tenth NMOS tube is connected with the clock signal, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the ninth NMOS tube and the source electrode of the eleventh NMOS tube and is used as the positive output end of the low-power consumption comparator circuit;

the grid electrode of the thirteenth NMOS tube is connected with the clock signal, and the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube and the source electrode of the fourteenth NMOS tube and is used as the negative output end of the low-power consumption comparator circuit;

the sources of the ninth NMOS tube, the tenth NMOS tube, the twelfth NMOS tube and the thirteenth NMOS tube are grounded;

the drain electrode of the ninth PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the source electrode of the ninth PMOS tube is connected with the power supply voltage;

the drain electrode of the tenth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube, and the source electrode of the tenth PMOS tube is connected with the power supply voltage;

the positive input end signal of the low-power consumption comparator circuit is different from the negative input end signal of the low-power consumption comparator circuit, so that the voltage falling speeds of the first node and the second node are different;

if the positive input end signal of the low-power consumption comparator circuit is larger than the negative input end signal of the low-power consumption comparator circuit, the voltage of the first node drops faster than the voltage of the second node, when the voltage of the first node is smaller than the turnover threshold voltage of the second inverter and the voltage of the second node is larger than the turnover threshold voltage of the third inverter, the positive output end of the low-power consumption comparator circuit outputs high level, the negative output end of the low-power consumption comparator circuit outputs low level, and the low-power consumption comparator circuit generates a comparison end mark signal;

if the positive input end signal of the low-power consumption comparator circuit is smaller than the negative input end signal of the low-power consumption comparator circuit, the voltage of the second node drops faster than the voltage of the first node, when the voltage of the first node is larger than the turnover threshold voltage of the first inverter and the voltage of the second node is smaller than the turnover threshold voltage of the fourth inverter, the positive output end of the low-power consumption comparator circuit outputs a low level, the negative output end of the low-power consumption comparator circuit outputs a high level, and the low-power consumption comparator circuit generates a comparison end mark signal;

and the comparison ending mark signal is used for controlling the low-power consumption comparator circuit to stop working.

2. The low power comparator circuit according to claim 1, wherein the inversion threshold voltages of the first inverter and the third inverter are 0.9V, and the inversion threshold voltages of the second inverter and the fourth inverter are 0.2V.

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