CN112332836B - Inverter reference signal phase-locked circuit - Google Patents
Inverter reference signal phase-locked circuit Download PDFInfo
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- CN112332836B CN112332836B CN202011290245.4A CN202011290245A CN112332836B CN 112332836 B CN112332836 B CN 112332836B CN 202011290245 A CN202011290245 A CN 202011290245A CN 112332836 B CN112332836 B CN 112332836B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
Abstract
The invention discloses an inverter reference signal phase-locked circuit, comprising: the phase adjusting and hysteresis comparing circuit comprises a phase adjusting and hysteresis comparing circuit, a zero-crossing comparing circuit, a phase locking circuit, a frequency dividing circuit, a D trigger and an 18-step sine signal generating circuit, wherein an externally input reference sine signal and an inversion output sine signal inside equipment are converted into standard square wave signals with 50% duty ratio, then the two square wave signals are sent into a phase locking chip, a voltage is output according to the phase difference of the two input signals, a voltage-controlled oscillator inside the phase locking chip adjusts the frequency of the output signal according to the phase difference voltage, and the signal is sent into a sine reference signal generator to control the frequency of the reference sine signal so as to realize the phase synchronization between the output phase of the inverter and the reference sine signal. The phase difference between the slave machine and the reference sinusoidal signal is fixed, the phase difference is not easily influenced by external interference, including electromagnetic conduction interference and ambient temperature, and reliability and interference resistance are improved.
Description
Technical Field
The invention belongs to the technical field of inverters, and relates to an inverter reference signal phase-locked circuit, in particular to a reference signal phase-locked circuit for an inverter.
Background
The inverter needs a plurality of products to work in combination in some special application occasions, and three single-phase inverters are combined to form a three-phase inverter output for supplying power to a three-phase electric load and simultaneously improving the total output power. But the phase difference between the three products needs to be kept at 120 degrees, and for the reasons, the inverter reference signal phase-locking circuit is designed, and the circuit can realize the fixed phase difference between the output of the inverter and the input reference signal.
Disclosure of Invention
Objects of the invention
The purpose of the invention is: a phase-locked circuit for an inverter reference signal is provided to realize a fixed phase difference between an output of the inverter and an input reference signal.
(II) technical scheme
In order to solve the above technical problem, the present invention provides an inverter reference signal phase-locked circuit, which is totally divided into six parts: the phase adjusting and hysteresis comparing circuit, the zero-crossing comparing circuit, the phase locking circuit, the frequency dividing circuit and the D trigger.
A first part: after an external reference signal enters the circuit, phase compensation adjustment is firstly carried out to reduce phase errors in the transmission process of the reference signal, the compensated signal enters the hysteresis comparison circuit to eliminate the jitter of a sinusoidal signal near a zero crossing point, and a 400Hz positive and negative level rectangular wave signal is output after passing through the hysteresis comparison circuit;
a second part: the zero-crossing comparison circuit converts the positive and negative level rectangular wave signals into 400Hz square wave signals by using a zero-crossing comparator;
and a third part: the phase locking circuit compares the 400Hz square wave signal generated by the zero-crossing comparison circuit with the 400Hz square wave signal output by the phase locking loop and generated by frequency division, and adjusts the frequency of the output signal of the phase locking circuit according to the phase difference of the two input square wave signals;
the fourth part: the frequency dividing circuit is used for dividing the frequency of the square wave signal output by the third part of phase locking circuit and outputting a pulse signal with the frequency of 1/8 duty ratio about 800Hz after frequency division;
the fifth part is that: the D trigger is used for carrying out 1/2 frequency division on the pulse signal output by the fourth part according to the characteristics of the D trigger, the output level is turned over once after a rising edge is received, and the D trigger finally outputs a 400Hz square wave model;
a sixth part: and the 18-step sinusoidal signal generating circuit is used for simultaneously sending signals generated by the third part phase-locked circuit and the fifth part D trigger into the 18-step sinusoidal signal generating circuit, wherein the signal of the third part phase-locked circuit is used for generating a sinusoidal signal, and the signal of the fifth part D trigger is used for periodically resetting the generated sinusoidal signal, so that the occurrence of accumulated phase errors is avoided.
(III) advantageous effects
According to the inverter reference signal phase-locked circuit provided by the technical scheme, the phase-locked circuit can realize the phase locking of the slave to the host in a high precision in a long-time operation process, the fixed phase difference between the slave and the reference sinusoidal signal is met, the phase-locked circuit is not easily influenced by external interference, including electromagnetic conduction interference and ambient temperature, and the reliability and the interference resistance are improved.
Drawings
Fig. 1 is a schematic block diagram of an inverter reference signal phase locking circuit according to the present invention.
Fig. 2 is a specific circuit diagram of an inverter reference signal phase-locking circuit according to the present invention.
Detailed Description
In order to make the objects, contents, and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
When three inverters are used in phase locking mode, the phase locking error exists between the phase B and C products as the slave machines and the phase A as the host machine, and the phase difference between any two phases is relatively serious. In order to solve the problem of phase-locked combination of three inverters, the invention designs an inverter reference signal phase-locked circuit to meet the phase difference of 120 degrees +/-1 degree between three phases and ensure that a three-phase power supply output by the combination of three products meets the input alternating current power supply index of electric equipment.
Fig. 1 is a schematic block diagram of the present invention, which is divided into six parts: the phase adjusting and hysteresis comparing circuit comprises a phase adjusting and hysteresis comparing circuit, a zero-crossing comparing circuit, a phase locking circuit, a frequency dividing circuit and a D trigger.
A first part: after an external reference signal enters the circuit, phase compensation adjustment is firstly carried out to reduce phase errors in the transmission process of the reference signal, the compensated signal enters the hysteresis comparison circuit to eliminate the jitter of a sinusoidal signal near a zero crossing point, and a 400Hz positive and negative level rectangular wave signal is output after passing through the hysteresis comparison circuit;
a second part: the zero-crossing comparison circuit converts the positive and negative level rectangular wave signals into 400Hz square wave signals by using a zero-crossing comparator;
and a third part: the phase locking circuit compares the 400Hz square wave signal generated by the zero-crossing comparison circuit with the 400Hz square wave signal output by the phase locking loop and generated by frequency division, and adjusts the frequency of the output signal of the phase locking circuit according to the phase difference of the two input square wave signals;
the fourth part: the frequency dividing circuit is used for dividing the frequency of the square wave signal output by the third part of phase locking circuit and outputting a pulse signal with the frequency of 1/8 duty ratio about 800Hz after frequency division;
the fifth part is that: the D trigger is used for carrying out 1/2 frequency division on the pulse signal output by the fourth part according to the characteristics of the D trigger, the output level is turned over once after a rising edge is received, and the D trigger finally outputs a 400Hz square wave model;
a sixth part: and the 18-step sinusoidal signal generating circuit is used for simultaneously sending signals generated by the third part phase-locked circuit and the fifth part D trigger into the 18-step sinusoidal signal generating circuit, wherein the signal of the third part phase-locked circuit is used for generating a sinusoidal signal, and the signal of the fifth part D trigger is used for periodically resetting the generated sinusoidal signal, so that the occurrence of accumulated phase errors is avoided.
The circuit connection is made as shown in fig. 2.
(1) The resistors R1 and R2 are used for dividing the voltage of an input reference signal, and the capacitors C1 and C2 are used for adjusting the phase of the input reference sine alternating current signal, so that the adjusted signal is consistent with the phase of the input host signal, and the phase error in the transmission process is reduced. The operational amplifier U1A is used as a hysteresis comparator, outputs a 400Hz rectangular wave with symmetric positive and negative, is used for eliminating the defect that the output level generates oscillation jump caused by the fact that an input host sine signal is easily interfered when passing through the vicinity of a zero level, and ensures that the output generates only one jump when the input signal passes through the zero level
(2) The zero-crossing comparator U2 shapes the input 400Hz rectangular wave to shorten the rising edge time of the rectangular wave, and converts the positive and negative symmetrical 400Hz rectangular wave into a standard 400Hz square wave signal.
(3) The output of the zero crossing comparator U2 is sent to a reference signal input pin (14 pin) of a phase-locked loop chip U3, a feedback signal is sent to a comparison signal input pin (3 pin) of the U3, the output (13 pin) of the phase comparator 2 is connected to a control input pin (9 pin) of the voltage-controlled oscillator after being subjected to RC filtering, and the output (4 pin) of the voltage-controlled oscillator is used as the feedback signal of the phase-locked loop after being subjected to frequency division. Meanwhile, the 6 pin and the 7 pin of the phase-locked loop chip U3 are required to be externally connected with an oscillation capacitor, and the 11 pin is required to be externally connected with an oscillation resistor.
(4) The output signal of the voltage-controlled oscillator in the phase-locked loop chip U3 is divided into two paths, one path is sent to the subtraction counter U4, and the other path is sent to the sine reference signal generator to be used as the clock signal of the sine reference signal generator. The preset number of the subtraction counter U4 is set to be 8,2 pins and 9 pins connected with high level, 3 pins connected with low level, 14 pins and 15 pins connected with short circuit, the chip is reset once every 8 pulses, and 14 pins output a pulse signal with the duty ratio of 0.125 and the frequency of 800 Hz.
(5) The output signal of a 14-pin of a subtraction counter U4 is sent to a CLK input pin (3-pin) of a D trigger U5, pins 4 and 6 of the D trigger U5 are grounded through a pull-down resistor, pins 2 and 5 are in short circuit, a 400Hz square wave signal is output at pin 2 of the D trigger, the square wave signal is divided into two paths, one path of the square wave signal is used as a feedback signal of a phase-locked loop and sent to pin 3 of the U3, the other path of the square wave signal is sent to a sine reference signal generator and used as a reset signal of the sine reference signal generator, and the sine reference signal is reset cycle by cycle.
According to the technical scheme, the phase-locking circuit can realize the phase locking of the slave to the host in a high precision in the long-time running process, meets the phase difference of 120 degrees between the slave and a given sinusoidal signal, is not easily influenced by external interference, including electromagnetic conduction interference and environment temperature, and greatly improves the reliability and the anti-interference performance compared with the prior art.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, it is possible to make various improvements and modifications without departing from the technical principle of the present invention, and those improvements and modifications should be considered as the protection scope of the present invention.
Claims (9)
1. An inverter reference signal phase-locked circuit, comprising: the device comprises a phase adjustment and hysteresis comparison circuit, a zero-crossing comparison circuit, a phase locking circuit, a frequency division circuit, a D trigger and an 18-step sinusoidal signal generation circuit; the external input sinusoidal reference signal is connected with the input end of the phase adjusting and hysteresis comparing circuit, the output end of the phase adjusting and hysteresis comparing circuit is connected with the input end of the zero-crossing comparing circuit, the output end of the zero-crossing comparing circuit is connected with the input end of the phase locking circuit, the output end of the phase locking circuit is connected with the input end of the frequency dividing circuit and the input end of the 18-step sinusoidal signal generating circuit, the output end of the frequency dividing circuit is connected with the input end of the D trigger, and the output end of the D trigger is connected with the input end of the phase locking circuit and the input end of the 18-step sinusoidal signal generating circuit; the sine reference signal is input into the phase adjustment and hysteresis comparison circuit from the outside, the positive and negative level rectangular wave signals adjusted to 400Hz are input into the zero-crossing comparison circuit, the zero-crossing comparison circuit outputs 400Hz square wave signals to the phase locking circuit, the phase locking circuit simultaneously receives 400Hz square wave signals transmitted by the D trigger, frequency output signals are adjusted to the frequency division circuit and the 18-step sine signal generation circuit according to the phase difference of the two input square wave signals, the frequency division circuit divides the frequency of the square wave signals output by the phase locking circuit and outputs pulse signals to the D trigger, and the D trigger divides the frequency of the pulse signals by 1/2 and respectively transmits the pulse signals to the phase locking circuit and the 18-step sine signal generation circuit for generating sine signals;
the 18-step sinusoidal signal generating circuit sends signals generated by the phase-locked circuit and the D trigger to the 18-step sinusoidal signal generating circuit simultaneously, the signal of the phase-locked circuit is used for generating a sinusoidal signal, and the signal of the D trigger is used for periodically resetting the generated sinusoidal signal.
2. The inverter reference signal phase-locked circuit of claim 1, wherein the phase adjusting and hysteresis comparing circuit comprises a phase adjusting circuit and a hysteresis comparing circuit.
3. The inverter reference signal phase-locked loop circuit according to claim 2, wherein the externally input sinusoidal reference signal is subjected to phase compensation adjustment by the phase adjustment circuit after entering the phase adjustment and hysteresis comparison circuit, so as to reduce a phase error during transmission of the reference signal, the compensated signal enters the hysteresis comparison circuit, so as to eliminate jitter of the sinusoidal signal around a zero crossing point, and a 400Hz positive and negative level rectangular wave signal is output after passing through the hysteresis comparison circuit.
4. The inverter reference signal phase-locked circuit of claim 3, wherein the zero-cross comparison circuit comprises a zero-cross comparator, and wherein the zero-cross comparator is used to convert positive and negative level rectangular wave signals into 400Hz square wave signals.
5. The inverter reference signal phase-locked circuit of claim 4, wherein the phase-locked circuit phase-compares the 400Hz square wave signal generated by the zero-cross comparison circuit with the 400Hz square wave signal generated by the phase-locked loop and frequency-divided, and adjusts the frequency of the output signal of the phase-locked circuit according to the phase difference between the two input square wave signals.
6. The inverter reference signal phase-locked circuit according to claim 5, wherein the frequency dividing circuit divides the frequency of the square wave signal outputted from the phase-locked circuit, and outputs the divided frequency as a pulse signal having a 1/8 duty ratio at a frequency of 800 Hz.
7. The inverter reference signal phase-locked circuit of claim 6, wherein the D flip-flop divides the pulse signal output from the frequency divider circuit by 1/2, and the output level is inverted once every time a rising edge is received, and the D flip-flop finally outputs a 400Hz square wave type.
8. The inverter reference signal phase-locked circuit according to claim 7, wherein the phase adjusting circuit comprises a resistor R1, a resistor R2, a capacitor C1, and a capacitor C2, the hysteresis comparator circuit comprises a hysteresis comparator, and the hysteresis comparator is an operational amplifier U1A; an externally input sinusoidal reference signal is connected with one end of a resistor R1 and one end of a capacitor C1, the other end of the resistor R1 is connected with one end of a resistor R2, the other end of the capacitor C1 is connected with one end of a capacitor C2, the other end of the resistor R2 and the other end of the capacitor C2 are grounded, a lead between the resistor R1 and the resistor R2 is connected between the capacitor C1 and the capacitor C2, and the negative input end of an operational amplifier U1A is further connected; the resistor R1 and the resistor R2 are used for dividing the voltage of an input reference signal, the capacitors C1 and C2 are used for adjusting the phase of the input reference sine alternating current signal, the adjusted signal is consistent with the phase of the input host signal, the operational amplifier U1A is used as a hysteresis comparator, and a 400Hz rectangular wave with symmetrical positive and negative is output.
9. The inverter reference signal phase-locking circuit according to any one of claims 1 to 8, wherein the phase-locking circuit is applied in the field of inverter technology.
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| CN202011290245.4A CN112332836B (en) | 2020-11-17 | 2020-11-17 | Inverter reference signal phase-locked circuit |
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| CN202011290245.4A CN112332836B (en) | 2020-11-17 | 2020-11-17 | Inverter reference signal phase-locked circuit |
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| CN202931283U (en) * | 2012-11-02 | 2013-05-08 | 李军 | Precise phase locking device |
| US9093894B2 (en) * | 2012-12-17 | 2015-07-28 | Greenmark Technology Inc. | Multiple-level power control system |
| CN108566105B (en) * | 2018-06-20 | 2023-12-26 | 南京麦格安倍电气科技有限公司 | Module reference sinusoidal signal generating circuit for combined three-phase inverter |
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