CN112331676A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN112331676A CN112331676A CN202011205211.0A CN202011205211A CN112331676A CN 112331676 A CN112331676 A CN 112331676A CN 202011205211 A CN202011205211 A CN 202011205211A CN 112331676 A CN112331676 A CN 112331676A
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- 239000000758 substrate Substances 0.000 title claims abstract description 114
- 239000002184 metal Substances 0.000 claims abstract description 62
- 239000011521 glass Substances 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 17
- 238000004080 punching Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 11
- 238000005192 partition Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
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- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 230000003111 delayed effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
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Abstract
The invention provides an array substrate, a display panel and a display device, wherein the array substrate comprises pixel units which are arranged in an array mode, the pixel units in the same row comprise a first gate line and a second gate line, the first gate line and the second gate line are respectively connected with partial pixel units in the same row, the first gate line is provided with a first subsection and a second subsection, the second gate line is provided with a third subsection and a fourth subsection, the first subsection and the second subsection are located on different metal layers and are connected through punching holes, and the third subsection and the fourth subsection are located on different metal layers and are connected through punching holes. The invention can solve the problem that the load of a single gate line is overlarge, and can ensure the aperture opening ratio of the display panel, thereby ensuring the brightness of the display panel.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
With the continuous development and improvement of the vehicle-mounted system, the attention of people to vehicle-mounted display is continuously increased, so that the change of a series of vehicle-mounted display technologies is accompanied. In order to bring more science and technology feelings and modern feelings to the interior of an automobile, various automobile companies pay attention to a vehicle-mounted display system, so that not only are various requirements on the appearance of the display, but also various requirements on the internal performance of the display, such as optical performance, power consumption and reliability performance, are required.
In recent years, a large-screen central control mode is a vehicle-mounted display mode which is simulated by various automobile companies and is continuously subjected to technical pursuit, and the fashion sense brought by the large-screen central control mode to automobile interior and the flexibility of screen operation are obvious. With the development of subsequent unmanned technology, the vehicle-mounted large screen also brings immersive visual experience to the passengers, but the large screen display still has more problems, such as too large load, insufficient pixel charging and the like, so that the medium-control large screen display technology is urgently needed to be improved, and better visual experience is expected to be brought to the users.
Disclosure of Invention
In view of the foregoing, embodiments of the present invention provide an array substrate, a display panel and a display device.
The array substrate provided by the embodiment of the invention comprises a display area, wherein the display area comprises pixel units which are arranged in an array manner, the pixel units extend along a first direction and are arranged along a second direction, and the first direction is intersected with the second direction;
the pixel unit comprises a thin film transistor, at least one thin film transistor in the same row of pixel units is electrically connected with the first gate line, and at least one thin film transistor in the same row of pixel units is electrically connected with the second gate line;
the pixel units in the same row comprise a first area and a second area, and the first area is adjacent to the second area;
the grid electrode of the thin film transistor in the first area is connected with the first grid line, and the grid electrode of the thin film transistor in the second area is connected with the second grid line;
the first gate line has a first part and a second part, the vertical projection of the first part on the array substrate is located in the first area, the vertical projection of the second part on the array substrate is located in the second area, the second gate line has a third part and a fourth part, the vertical projection of the third part on the array substrate is located in the second area, and the vertical projection of the fourth part on the array substrate is located in the first area;
the first subsection is located on a first metal layer, the second subsection is located on a second metal layer, the third subsection is located on a third metal layer, the fourth subsection is located on a fourth metal layer, and an insulating layer is arranged between different metal layers;
the first subsection and the second subsection are electrically connected through a first through hole, and the third subsection and the fourth subsection are electrically connected through a second through hole.
The display panel and the display device provided by the embodiment of the invention comprise the array substrate.
Compared with the prior art, the array substrate, the display panel and the display device provided by the embodiment of the invention have the advantages that the pixel brightness of different positions of the array substrate is driven by two gate lines together, one gate line drives one part of pixel units in the same row, and the other gate line drives the other part of pixel units in the same row, so that the problem of overlarge load caused by the fact that the whole row of pixel units is driven by a single gate line is avoided, and the phenomenon of uneven pixel brightness caused by the fact that the driving start end and the driving tail end are charged differently is also avoided; in addition, according to the array substrate, the display panel and the display device provided by the embodiment of the invention, each grid line is divided into two parts, the two parts are arranged in a layered mode, and the two parts are connected through the holes, so that the problem that the shading area needs to be increased when two grid lines are designed on the same metal layer is avoided, and the aperture opening ratio of the display panel is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that are required in the description of the embodiments will be briefly introduced, the drawings described herein are provided to provide further understanding of the present invention and constitute a part of the present invention, and the exemplary embodiments and descriptions thereof of the present invention are provided for explaining the present invention and do not constitute a limitation of the present invention.
Fig. 1 is a schematic top view of an array substrate in the prior art;
FIG. 2 is a partial structural diagram of the array substrate S1 of FIG. 1;
fig. 3 is a schematic top view of an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic view of a portion of the structure of the region S of the array substrate of FIG. 3;
FIG. 5 is a schematic cross-sectional view of FIG. 4 taken along axis AA';
FIG. 6 is a schematic diagram of a structure of the region T in FIG. 5;
FIG. 7 is a circuit diagram of a vertical shift register in the area of FIG. 3R;
FIG. 8 is a diagram of a shift register with gate metal lines in FIG. 5;
FIG. 9 is a schematic cross-sectional view of another array substrate according to an embodiment of the present invention;
FIG. 10 is a partial cross-sectional view of another array substrate according to an embodiment of the present invention;
FIG. 11 is a schematic view of another gate line structure according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a gate line via arrangement according to an embodiment of the invention.
Detailed Description
The embodiments of the present invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The existing vehicle-mounted central control is increasingly moving to a large-size screen, the size of the screen is usually more than 10 inches, even more than 30 inches, and the screen size is large, so that the number of transverse pixels of the screen exceeds 9000, and the length of the screen is more than 800 mm.
Generally, a display panel includes a display area and a non-display area surrounding the display area, at least one side of the non-display area has a vertical shift register, the vertical shift register includes a plurality of shift register circuits, one end of each shift register circuit is connected to a gate driving signal, and the other end of each shift register circuit is connected to a gate line. The display area gate drive signal has three drive modes, namely single-side drive, double-side drive and cross drive, wherein the single-side drive means that a vertical shift register is arranged on one side of the display panel, the gate drive signal is connected with each row of gates through each stage of shift register circuit, that is, the gate driving signal is input only at a single end of the display panel, the dual-side driving means that vertical shift registers are provided at two symmetrical sides of the display panel, the gate driving signal is connected to the gate of each row through each stage of shift register at the two sides, the grid driving signals are input at two ends of the display panel, the cross driving means that vertical shift registers are arranged at two symmetrical sides of the display panel, one side of the shift register circuit is connected with the grid lines of the corresponding odd rows, the other side of the shift register circuit is connected with the grid lines of the corresponding even rows, and the grid driving signals of the odd rows and the even rows are input at two different ends.
As shown in fig. 1 and 2, fig. 1 is a schematic top view of an array substrate in the prior art, fig. 2 is a partial structure of an area S1 of the array substrate of fig. 1, the array substrate 11 includes a display area 111 and a non-display area 112, wherein the display area 111 includes a gate line 12, a data line 13, a drain electrode 14, an active device 15, and the like, the gate line 12 extends along a first direction, the data line 13 extends along a second direction, the first direction is arranged, the gate line 12 and the data line 13 cross each other to define a plurality of pixel units 16, and the same row of pixels 16 is driven by a single gate line 12. When the number of pixels driven by a single gate line is too large, the load of the gate line is easily too large, and the brightness of the pixels at the starting end and the tail end is inconsistent due to the charging difference between the starting end and the tail end of the gate line driving, so that the brightness of the display panel is uneven.
Aiming at the conditions that a single grid line has large load and the charging voltages of the starting end and the tail end of an input driving signal are inconsistent, the embodiment of the invention provides a scheme that pixels in the same row are driven by two grid lines;
the technical solution of the embodiment of the present invention provides an array substrate design, referring to fig. 3 and 4, fig. 3 is a schematic top view of an array substrate according to an embodiment of the present invention, and fig. 4 is a schematic structural view of a portion of an S region of the array substrate of fig. 3; the array substrate 31 provided by the embodiment of the invention includes a display area 311, the display area 31 includes pixel units 36 arranged in an array, the pixel units extend along a first direction and are arranged along a second direction, and the first direction intersects with the second direction; the array substrate 31 further includes a first gate line 321, a second gate line 322, and the extending directions of the first gate line 321 and the second gate line 322 are parallel to the first direction, the pixel unit 36 includes a thin film transistor 37, at least one thin film transistor 37 in the same row of pixel units is electrically connected to the first gate line 321, and at least one thin film transistor 37 in the same row of pixel units is electrically connected to the second gate line 322, that is, the thin film transistors of a part of the pixel units in the same row of pixels are electrically connected to the first gate line, and the thin film transistors of another part of the pixel units are electrically connected to the second gate line. The same row of pixel units comprises a first region D1 and a second region D2, the first region D1 and the second region D2 are adjacent to each other; the gate of the thin film transistor of the first region D1 is connected to the first gate line 321, and the gate of the thin film transistor of the second region D2 is connected to the second gate line 322.
And one part of the pixel units in the same row are driven by one gate line, and the other part of the pixel units are driven by the other gate line, so that the problem of overlarge load caused by the fact that a single gate line drives the whole row of pixel units is avoided, and the phenomenon of uneven pixel brightness caused by inconsistent charging of the driving start end and the driving tail end is also avoided. On the premise of the above design scheme, the embodiments of the present invention further provide the following designs. As shown in fig. 4 and 5, fig. 5 is a schematic cross-sectional structure taken along an axis AA' in fig. 4, in which the array substrate 31 includes a metallic light-shielding layer 39, an insulating layer 38, and an active layer 35, the first gate line 321 has a first segment 3211 and a second segment 3212, a vertical projection of the first segment 3211 on the array substrate is located in the first area D1, a vertical projection of the second segment 3212 on the array substrate is located in the second area D2, the second gate line 322 has a third segment 3221 and a fourth segment 3222, a vertical projection of the third segment 3221 on the array substrate is located in the second area D2, and a vertical projection of the fourth segment 3222 on the array substrate is located in the first area D1. The first segment 3211 is located in a first metal layer, the second segment 3212 is located in a second metal layer, the third segment 3221 is located in a third metal layer, and the fourth segment 3222 is located in a fourth metal layer, and an insulating layer 38 is disposed between different metal layers.
As shown in fig. 5 and 6, fig. 6 is a schematic structural diagram of the region of fig. 5T, the first subsection 3211 is electrically connected to the second subsection 3212 through a first via H1, and the third subsection 3221 is electrically connected to the fourth subsection 3222 through a second via H2.
Two grid lines of the same row of pixel units are divided into two parts, the two parts adopt layered design, the situation that the grid lines and the active devices are placed on two sides of a row of pixels along the second direction is avoided, the size of a black matrix along the second direction needs to be increased in order to shield the two grid lines and the active devices, and therefore the aperture opening ratio of the pixels is guaranteed.
In the structural design of the array substrate according to the embodiment of the invention, the first gate line 321 and the second gate line 322 are respectively connected to a part of the pixel units in the same row, and the first gate line 321 and the second gate line 322 are respectively divided into two parts, and the two parts are located on different metal layers and connected together through a perforation. When driving signals are input to two ends of the first gate line 321 and the second gate line 322, the first gate line 321 and the second gate line 322 respectively charge part of pixels in the same row, so that the phenomenon that the load on the gate lines is too large is avoided, the input end of the gate line driving signal is generally positioned at the edge of the display area, the tail end of the gate line driving signal is generally positioned at the position, close to the middle part, of the display area, when the driving signals are input, the difference between the charging voltage of the pixels positioned at the edge of the display area and the charging voltage of the pixels close to the middle part is small, the difference between the brightness of the pixels in the display area is small, and.
The first gate line 321 and the second gate line 322 respectively have two parts, and the two parts are designed in a layered manner, so that the gap between the first gate line 321 and the second gate line 322 arranged along the second direction is reduced, that is, the size of the non-light-transmitting part of the pixel unit along the second direction is reduced, the aperture opening ratio of the pixel unit is ensured, the brightness of the display panel is basically consistent with the brightness of the array substrate designed by adopting a single gate line, and the brightness of the display panel is ensured at the same time.
Due to the limitation of the preparation process, the side wall of the via hole can not be ensured to be completely vertical to the plane of the array substrate, that is, the side wall of the via hole usually is in an inclined state, the aperture of the via hole close to one side of the glass substrate is usually small, the aperture of the via hole far from one side of the glass substrate is usually large, and the via hole nesting of each film layer can have fluctuation of alignment precision, so that the distance between the geometric centers of the vertical projection of any two via holes on the array substrate on the display panel is at least 5 μm, because the minimum aperture distance of the vertical projection of the via hole on the array substrate is at least 3 μm, and the deviation of the alignment precision between different film layers is +/-1 μm, so that the geometric center distance of the vertical projection of any two via holes on the array substrate is ensured to be at least 5 μm, in order to ensure that the two via holes can be completely separated, and simultaneously avoid the problem that the two via holes can, thereby preventing the first gate line 321 and the second gate line 322 from being connected.
Alternatively, the thickness of the insulating layer 38 between different metal layers is 1 μm or more in a direction perpendicular to the array substrate. Generally, in a direction perpendicular to the array substrate, the gate metal layer has a certain thickness h, and the thickness h is within a numerical range of 0 ≤ h ≤ 1 μm, if the thickness of the insulating layer prepared on the gate metal layer is too thin, the insulating layer in an upper region of the gate metal layer away from the glass substrate will bulge, that is, the surface of the insulating layer at the side away from the glass substrate is not flat, and has a certain step difference, which will affect the subsequent film forming and photolithography processes, so that the gate line prepared subsequently has problems such as wire breakage due to the step difference, and the line width of the gate line may be non-uniform, so the insulating layer prepared on the gate metal layer must have a certain thickness, thereby ensuring that each layer of gate metal layer can be prepared on the flat insulating layer.
Optionally, as shown in fig. 3, the array substrate 31 provided in the embodiment of the present invention includes a non-display area 312, and the non-display area surrounds the display area, as shown in fig. 7, fig. 7 is a schematic diagram of a circuit structure of a vertical shift register in the area of fig. 3R; the non-display area includes vertical shift register circuits V arranged along the second direction, and the vertical shift register circuits in the same column include a plurality of shift register circuits V11, V12, and the like, as shown in fig. 8, fig. 8 is a schematic diagram of a gate metal line connected to the shift register in fig. 5; the first and fourth segments 3211 and 3222 are connected to the same set of shift register circuits V11, the second and third segments 3212 and 3221 are connected to the same set of shift register circuits V12, and the shift register circuits V11 and V12 input signals at the same time.
The first sub-portion 3211 and the fourth sub-portion 3222 are connected to the same shift register circuit V11, and the second sub-portion 3212 and the third sub-portion 3221 are connected to the same shift register circuit V12, so that the number of shift register circuits does not need to be increased in a non-display area of the array substrate, and the width of the non-display area is ensured to be consistent with that of the existing design, and the shift register circuits V11 and V12 input signals at the same time, thereby ensuring that pixels in the same row are simultaneously lighted, and avoiding a delayed lighting phenomenon of some pixels.
Optionally, as shown in fig. 9, fig. 9 is a schematic cross-sectional structure diagram of another array substrate portion according to an embodiment of the present invention, where the array substrate 311 according to an embodiment of the present invention includes a glass substrate 30, an insulating layer 38, an active layer 35, and the like, where the active layer 35 in a first area D1 is located on a side of the first metal layer where the first sub-portion 3211 is located and a side of the fourth metal layer where the fourth sub-portion 3222 is located, which faces away from the glass substrate 30, the fourth metal layer is located between the first metal layer and the glass substrate 30, the active layer 35 in a second area D2 is located on a side of the second metal layer where the second sub-portion 3212 is located and a side of the third metal layer where the third sub-portion 3221 is located, which faces away from the glass substrate 30, and the second metal layer is located between the third.
As shown in fig. 5, the array substrate 31 is sequentially provided with a metal light shielding layer 39, an insulating layer 38, an active layer 35, metal layers where the first gate line 321 and the second gate line 322 are located, and insulating layers between the metal layers, that is, the active layer 35 is disposed between each metal layer and the glass substrate 30, and fig. 9 differs from fig. 5 in that each metal layer is disposed between the active layer 35 and the glass substrate 30, so that the active layer 35 can be shielded by the gate metal layer, the manufacturing process of the metal light shielding layer 39 is reduced, the production process of the array substrate can be accelerated, and the production cost is reduced.
Alternatively, as shown in fig. 10, fig. 10 is a schematic cross-sectional structure diagram of a portion of another array substrate according to an embodiment of the present invention, where the array substrate 312 according to an embodiment of the present invention includes a glass substrate 30, an insulating layer 38, an active layer 35, and the like, where a vertical projection of the first partition 3211 and the fourth partition 3222 on the array substrate 312 overlaps, a vertical projection of the second partition 3212 and the third partition 3221 on the array substrate 312 overlaps, a first region D1 is located between metal layers at which the first partition 3211 and the fourth partition 3222 are located, and a second region D2 is located between metal layers at which the second partition 3212 and the third partition 3221 are located.
The array substrate 312 provided by the embodiment of the invention can also shield the active layer 35 by using the gate metal layer, thereby reducing the manufacturing process of the metal shielding layer 39, accelerating the production process of the array substrate and reducing the production cost.
Alternatively, as shown in fig. 3, the first region D1 and the second region D2 of the array substrate may be two regions with the same area, and the design may make the number of the pixel units driven by the first gate line 321 consistent with the number of the pixel units driven by the second gate line 322, so as to ensure that the pixel unit rates driven by the first region D1 and the second region D2 are consistent, the transmission rates of the driving signal input ends and the tail ends of the two gate lines are substantially consistent, and the charging voltages of the pixel units of the first region D1 and the second region D2 are substantially the same, thereby further ensuring the brightness uniformity of the display panel.
Optionally, as shown in fig. 5, the first sub-portion 3211 and the third sub-portion 3221 may be prepared in the same layer, and the second sub-portion 3212 and the fourth sub-portion 3222 may be prepared in the same layer, that is, the first sub-portion 3211 and the third sub-portion 3221 are located in the same metal layer, and the second sub-portion 3212 and the fourth sub-portion 3222 are located in the same metal layer, and the two sub-portions in the same metal layer may be prepared by using the same photolithography mask and photolithography process.
Alternatively, as shown in fig. 4, the first segment 3211 has a first geometric center C1 in a vertical projection of the array substrate, the third segment 3221 has a second geometric center C2 in a vertical projection of the array substrate, and the first geometric center C1 and the second geometric center C2 are collinear, and an extending direction of the line is parallel to the first direction; by arranging the geometric centers of the first and third segments 3211 and 3221 on a straight line, that is, by keeping the distances between the first gate line 321 in the first region D1 and the second gate line 322 in the second region D2 and the pixel opening area consistent, in this state, the line width of the light shielding layer facing away from the glass substrate and covering the gate lines in the second direction is consistent with that of a single gate line, and the line width is not increased due to the misalignment of the two gate lines in the second direction, thereby greatly ensuring the aperture ratio of the pixel area.
Optionally, as shown in fig. 5, the vertical projections of the fourth segment 3222 and the first segment 3211 in the first region D1 on the array substrate at least partially overlap, and the vertical projections of the second segment 3212 and the third segment 3221 in the second region D2 on the array substrate at least partially overlap, which is also designed to ensure that the line width of the light shielding layer in the second direction is reduced as much as possible, so as to ensure the opening of the pixel region of the display panel and ensure the display brightness of the display panel.
Alternatively, as shown in fig. 11, fig. 11 is a schematic view of another gate line structure provided in the embodiment of the invention, in which a vertical projection of the first via H1 on the array substrate has a third geometric center C3, a vertical projection of the second via H2 on the array substrate has a fourth geometric center C4, a first geometric center C1 of a vertical projection of the first segment 3211 of the first gate line 321 on the array substrate, and a second geometric center C2 of a vertical projection of the third segment 3221 of the second gate line 322 on the array substrate may define a straight line, the third geometric center C3 is located on the straight line and located between the vertical projections of the two segments on the array substrate, and the fourth geometric center C4 is not located on the straight line. Alternatively, the fourth geometric center C4 can be located on the straight line, and the third geometric center C3 is not located on the straight line.
The geometric centers of the first via hole H1 or the second via hole H2 and the geometric centers of the first subsection 3211 of the first gate line 321 and the third subsection 3221 of the second gate line 322 are arranged on the same straight line, so that the line width of the light shielding layer at the via hole along the second direction is not increased due to the staggered design of the two via holes and the subsections of the gate lines, the uniformity of the line width of the light shielding layer in the same row is ensured, and the aperture opening ratios of the pixels in the same row are kept consistent.
Alternatively, the third geometric center C3 of the first via H1 and the fourth geometric center C4 of the second via H2 in the same row may define a straight line, and the extending direction of the straight line intersects with the second direction, that is, the third geometric center C3 and the fourth geometric center C4 in the same row are staggered along the second direction, so as to avoid the line width of the light shielding layer at the via along the second direction from increasing due to the need of covering two vias, and at the same time, because the line width of the light shielding layer at the via is not consistent with the line width of the gate line, if the third geometric center C3 and the fourth geometric center C4 in the same row are not staggered along the second direction, the aperture ratio of the pixels at two ends of the via will not be consistent with the aperture ratio of the other pixels in the same row, and thus the phenomenon of uneven display brightness will occur, the design provided by the embodiment of the invention can reduce or eliminate the phenomenon of uneven display brightness of the display panel.
Alternatively, as shown in fig. 12, fig. 12 is a schematic diagram of a gate line via arrangement according to an embodiment of the present invention, in which an extending direction of a connection line of the third geometric centers C3 of two adjacent rows intersects with the second direction, and an extending direction of a connection line of the fourth geometric centers C4 of two adjacent rows intersects with the second direction. It should be noted that, it is not limited herein that the extending direction of the connecting line between the third geometric center C3 and the fourth geometric center C4 of two adjacent rows intersects the second direction, and in design, only the extending direction of the connecting line between the third geometric center C3 of two adjacent rows intersects the second direction, or only the extending direction of the connecting line between the fourth geometric center C4 of two adjacent rows intersects the second direction, or both the extending directions of the connecting line between the third geometric center C3 and the fourth geometric center C4 of two adjacent rows intersect the second direction, according to the arrangement of the pixels on the display surface.
The design can ensure that the third geometric center C3 and/or the fourth geometric center C4 of the same column are staggered along the second direction, so that the phenomenon that the aperture ratio of pixels at two ends of the same column of vias is inconsistent with the aperture ratio of pixels in other columns, and the display brightness is uneven can not occur.
Based on the above embodiments, the embodiment of the present invention further provides a display panel, which may be a liquid crystal display panel, an organic light emitting display panel, or a micron-sized LED display panel, wherein the display panel includes the structural design of the array substrate described in the above embodiments. The advantageous effects produced by the display panel are as described in the above embodiments, and are not described herein again.
The embodiment of the present invention further provides a display device, where the display device includes a vehicle-mounted product, and certainly not limited to vehicle-mounted products, such as a flat panel display device, a notebook display device, and the like, may adopt the design scheme of the present invention, the display device includes the display panel, and beneficial effects produced by the display device are also the beneficial effects described in the above embodiments, and are not described herein again.
The foregoing description shows and describes several preferred embodiments of the present application, but as aforementioned, it is to be understood that the application is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the application, which is to be protected by the claims appended hereto.
Claims (15)
1. An array substrate is characterized by comprising a display area, wherein the display area comprises pixel units arranged in an array manner, the pixel units extend along a first direction and are arranged along a second direction, and the first direction is intersected with the second direction;
the pixel unit comprises a thin film transistor, at least one thin film transistor in the same row of pixel units is electrically connected with the first gate line, and at least one thin film transistor in the same row of pixel units is electrically connected with the second gate line;
the pixel units in the same row comprise a first area and a second area, and the first area is adjacent to the second area;
the grid electrode of the thin film transistor in the first area is connected with the first grid line, and the grid electrode of the thin film transistor in the second area is connected with the second grid line;
the first gate line has a first part and a second part, the vertical projection of the first part on the array substrate is located in the first area, the vertical projection of the second part on the array substrate is located in the second area, the second gate line has a third part and a fourth part, the vertical projection of the third part on the array substrate is located in the second area, and the vertical projection of the fourth part on the array substrate is located in the first area;
the first subsection is located on a first metal layer, the second subsection is located on a second metal layer, the third subsection is located on a third metal layer, the fourth subsection is located on a fourth metal layer, and an insulating layer is arranged between different metal layers;
the first subsection and the second subsection are electrically connected through a first through hole, and the third subsection and the fourth subsection are electrically connected through a second through hole.
2. The array substrate of claim 1, wherein the distance between the geometric centers of the vertical projections of any two vias on the array substrate is at least 5 μm.
3. The array substrate of claim 1, wherein the insulating layer has a thickness of 1 μm or more in a direction perpendicular to the array substrate.
4. The array substrate of claim 1, comprising a non-display area surrounding the display area, wherein the non-display area comprises vertical shift register circuits arranged along the second direction, the vertical shift register circuits comprise a plurality of shift register circuits, the first part and the fourth part are connected to a same shift register circuit, the second part and the third part are connected to a same shift register circuit, and the two shift register circuits input signals simultaneously.
5. The array substrate of claim 1, comprising a glass substrate, an active layer, wherein the first area active layer is located on a side of the first metal layer and a fourth metal layer facing away from the glass substrate, and the fourth metal layer is located between the first metal layer and the glass substrate; the second region active layer is located on one side, away from the glass substrate, of the second metal layer and the third metal layer, and the second metal layer is located between the third metal layer and the glass substrate.
6. The array substrate of claim 1, comprising a glass substrate, an active layer, wherein the first subsection overlaps a vertical projection of the fourth subsection on the array substrate, the second subsection overlaps a vertical projection of the third subsection on the array substrate, the first area active layer is located between the first metal layer and a fourth metal layer, and the second area active layer is located between the second metal layer and a third metal layer.
7. The array substrate of claim 1, wherein the first region and the second region are two regions with the same area.
8. The array substrate of claim 1, wherein the first subsection and the third subsection are located at a same metal layer, and the second subsection and the fourth subsection are located at a same metal layer.
9. The array substrate of claim 8, wherein the first section has a first geometric center in a vertical projection of the array substrate, the third section has a second geometric center in a vertical projection of the array substrate, the first geometric center and the second geometric center are on a same straight line, and the extending direction of the straight line is parallel to the first direction.
10. The array substrate of claim 9, wherein the first subsection and the fourth subsection at least partially overlap in a vertical projection of the array substrate, and the second subsection and the third subsection at least partially overlap in a vertical projection of the array substrate.
11. The array substrate of claim 10, wherein a vertical projection of the first via on the array substrate has a third geometric center, a vertical projection of the second via on the array substrate has a fourth geometric center, one of the third geometric center or the fourth geometric center is located on a same line with the first and second geometric centers and between the vertical projections of the first and third sections on the array substrate, and the other geometric center is not located on a same line with the first geometric center and the second geometric center.
12. The array substrate of claim 1, wherein a vertical projection of the first via on the array substrate has a third geometric center, a vertical projection of the second via on the array substrate has a fourth geometric center, and an extending direction of a line connecting the third geometric center and the fourth geometric center of the same row intersects with the second direction.
13. The array substrate of claim 1, wherein the extension direction of the line connecting the third geometric centers of two adjacent rows intersects with the second direction;
and/or the extending direction of the connecting line of the fourth geometric centers of two adjacent rows is intersected with the second direction.
14. A display panel comprising the array substrate of claims 1-13.
15. A display device characterized by comprising the display panel according to claim 14.
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| WO2022236866A1 (en) * | 2021-05-11 | 2022-11-17 | Tcl华星光电技术有限公司 | Driving circuit, display panel, and panel |
| US11756478B2 (en) | 2021-05-11 | 2023-09-12 | Tcl China Star Optoelectronics Technology Co., Ltd. | Driving circuit, display panel, and panel |
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| CN112331676B (en) | 2022-07-26 |
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