CN112331673A - Semiconductor chip and intelligent power module - Google Patents
Semiconductor chip and intelligent power module Download PDFInfo
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- CN112331673A CN112331673A CN201910718545.9A CN201910718545A CN112331673A CN 112331673 A CN112331673 A CN 112331673A CN 201910718545 A CN201910718545 A CN 201910718545A CN 112331673 A CN112331673 A CN 112331673A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a semiconductor chip, which comprises a first semiconductor layer, a first insulating layer, an isolating layer, a second insulating layer and a second semiconductor layer which are sequentially stacked; wherein a first electronic component is formed on the first semiconductor layer; forming a second electronic component on the second semiconductor layer; along range upon range of direction, the vertical projection of first electronic components with the vertical projection of second electronic components is at least by the isolation layer covers, first preset electric potential is connected to the isolation layer to keep apart first electronic components with electric interference between the second electronic components.
Description
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a semiconductor chip and an intelligent power module.
Background
IPM (Intelligent Power Module) is widely applied to the fields of variable frequency speed regulation of ac motors, chopper speed regulation of dc motors, various high-performance Power supplies, industrial electrical automation, new energy and the like, and has wide market application. The IPM is an advanced power switch device, and is essentially a module integrating a power device and a driving circuit thereof; the IPM plays an important role in the field of energy management, which is difficult to reach by other integrated circuits, and the device performance directly affects the utilization efficiency of an energy system.
The existing IPM generally comprises a plurality of electronic components, and each electronic component may need a plurality of components; therefore, the total number of electronic components in the IPM is large, the size of the packaged module is large, the inductance effect is obvious, and how to improve the integration level becomes one of the technical problems to be solved urgently at the present stage.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor chip and an intelligent power module.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a semiconductor chip, which comprises a first semiconductor layer, a first insulating layer, an isolating layer, a second insulating layer and a second semiconductor layer which are sequentially stacked; wherein the content of the first and second substances,
forming a first electronic component on the first semiconductor layer;
forming a second electronic component on the second semiconductor layer;
along range upon range of direction, the vertical projection of first electronic components with the vertical projection of second electronic components is at least by the isolation layer covers, first preset electric potential is connected to the isolation layer to keep apart first electronic components with electric interference between the second electronic components.
In the above scheme, the first electronic component includes a power device, and the second electronic component includes a driving circuit.
In the above scheme, the isolation layer is a semiconductor layer.
In the above scheme, the semiconductor layer is a silicon layer.
In the above scheme, the isolation layer contains doping ions.
In the above scheme, the thickness range of the isolation layer is 40-200 nm.
In the above scheme, the first preset potential is 0 v.
The embodiment of the invention also provides a semiconductor chip which is provided with a double silicon-on-insulator D-SOI structure, wherein the D-SOI structure comprises a first semiconductor layer, a second semiconductor layer and an insulating layer positioned between the first semiconductor layer and the second semiconductor layer; wherein the content of the first and second substances,
a first electronic component is formed on the first semiconductor layer and comprises a reverse conducting insulated gate bipolar transistor (RC-IGBT);
and a second electronic component is formed on the second semiconductor layer and comprises at least one of a driving circuit, a control circuit, a monitoring circuit and a protection circuit.
An embodiment of the present invention further provides an intelligent power module IPM, including at least one semiconductor chip according to any one of the above schemes.
In the above scheme, the IPM further includes a lead frame, the lead frame is provided with an upper bridge chip mounting location and a lower bridge chip mounting location, and the semiconductor chip is mounted on at least one of the upper bridge chip mounting location and the lower bridge chip mounting location.
Based on the semiconductor chip provided by the embodiment of the invention, the first semiconductor layer and the second semiconductor layer of the semiconductor chip are respectively provided with the electronic components, namely the first electronic component and the second electronic component are integrated on one semiconductor chip, so that the integration level of the semiconductor chip is improved, and the full utilization of a wafer is realized; furthermore, by arranging the isolation layer, the electrical interference between the first electronic component and the second electronic component is avoided to a great extent, and the working stability of each electronic component in the semiconductor chip is ensured; in specific application, the first electronic component comprises an RC-IGBT, the second electronic component comprises at least one of a driving circuit, a control circuit, a monitoring circuit and a protection circuit, and the RC-IGBT and a circuit part are integrated on the same semiconductor chip and are separated on two semiconductor layers through a D-SOI structure. In addition, the intelligent power module provided by the embodiment of the invention comprises at least one semiconductor chip provided by the embodiment of the invention, so that the integration level of the intelligent power module is improved, the size of the module is reduced, and the inductance effect is reduced.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor chip according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of an intelligent power module according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
The embodiment of the invention provides a semiconductor chip. Fig. 1 is a schematic cross-sectional view of a semiconductor chip according to an embodiment of the present invention, and as shown in the figure, the semiconductor chip 100 includes a first semiconductor layer 110, a first insulating layer 120, an isolation layer 130, a second insulating layer 140, and a second semiconductor layer 150, which are sequentially stacked; wherein a first electronic component (not shown) is formed on the first semiconductor layer 110; a second electronic component 151 is formed on the second semiconductor layer 150; along the stacking direction, the vertical projection of the first electronic component and the vertical projection of the second electronic component 151 are at least covered by the isolation layer 130, and the isolation layer 130 is connected with a first preset potential to isolate the electrical interference between the first electronic component and the second electronic component 151.
In the embodiment of the present invention, the first semiconductor layer 110, the first insulating layer 120, the isolation layer 130, the second insulating layer 140, and the second semiconductor layer 150 form a special D-SOI (Double-Silicon On Insulator) structure, that is, the isolation layer is additionally disposed in the insulating layer of the D-SOI structure to isolate the electrical interference between the first electronic component and the second electronic component. In some embodiments, a D-SOI substrate including a first semiconductor layer 110, a first insulating layer 120, an isolation layer 130, a second insulating layer 140, and a second semiconductor layer 150 may be provided, and then a first electronic component is formed on the first semiconductor layer 110 and a second electronic component 151 is formed on the second semiconductor layer 150; in other embodiments, the first electronic component may be formed on the first semiconductor layer 110, the second electronic component 151 may be formed on the second semiconductor layer 150, and then bonded together to form the D-SOI structure.
The first semiconductor layer 110 and the second semiconductor layer 150 may be silicon layers, i.e., two wafers.
The first insulating layer 120 and the second insulating layer 140 may be buried oxide layers, such as SiO2And (3) a layer. The thickness ranges of the first insulating layer 120 and the second insulating layer 140 are 200-400 nm; in some embodiments, the first insulating layer 120 and the second insulating layer 140 have the same thickness; in other embodiments, the thickness of the first insulating layer 120 is greater than that of the second insulating layer 140, so as to improve the voltage endurance of the device.
As shown in fig. 1, the second electronic component 151 only occupies a partial region on the second semiconductor layer 150, and a structure such as a through silicon via or an oxide layer may be further included in a region other than the second electronic component 151 on the second semiconductor layer 150. The first electronic component may occupy only a partial region on the first semiconductor layer 110; the first electronic component may be located directly below the second electronic component 151 on the first semiconductor layer 110, or may be located laterally below the second electronic component 151, but in either case, the isolation layer 130 is completely isolated between the first electronic component and the second electronic component 151; that is, in the stacking direction, the vertical projection of the first electronic component and the vertical projection of the second electronic component 151 are covered by at least the spacer 130.
The first electronic component and the second electronic component 151 can be electrically connected through the through silicon via, so that the problem of poor reliability of wire connection is solved, the structural size is reduced, and the possibility of integrating more complex functions is provided.
The semiconductor chip provided by the embodiment can be applied to an intelligent power module. The first electronic component may include a power device, and the second electronic component may include a driving circuit; therefore, the power device and the driving circuit are integrated on the same semiconductor chip. In this case, the driving circuit may be a driving circuit corresponding to the power device.
In a specific embodiment, the first electronic component may include an IGBT (Insulated Gate Bipolar Transistor) and an FRD (Fast Recovery Diode); further, for example, an RC-IGBT (Reverse Conducting-IGBT) is included, that is, a conventional IGBT cell structure and an FRD cell structure are integrated. The second electronic component includes a driving Circuit, which may be an Integrated Circuit (IC); in some embodiments, the driving circuit is a single channel driving IC. The second electronic component may further include a control circuit (e.g., a Micro-controller Unit (MCU)), a monitoring circuit, a protection circuit, and the like. In addition, the second electronic component may further include elements such as a capacitor and a resistor.
When the first electronic component includes an IGBT/RC-IGBT, the IGBT/RC-IGBT may be in a lateral structure or a vertical structure, that is, the collector and the emitter may be located on the same side or on different sides. The first electronic component may be formed on a side of the first semiconductor layer 110 away from the first insulating layer 120, or may be formed on a side close to the first insulating layer 120; the D-SOI substrate may be provided and then formed on the first semiconductor layer 110 in the D-SOI substrate, or the first electronic component may be formed on the first semiconductor layer 110 and then bonded to the first insulating layer 120.
In an embodiment, the thickness of the first semiconductor layer 110 forming the power device may be greater than the thickness of the second semiconductor layer 150 forming the driving circuit, and in this case, the first semiconductor layer 110 may serve as a substrate and serve as a mechanical support; the quality of the first semiconductor layer 110 is required to meet the quality requirement for manufacturing components.
The isolation layer 130 may be a semiconductor layer. In an embodiment, the isolation layer 130 may be the same as the material of the first semiconductor layer 110 and/or the material of the second semiconductor layer 150. The isolation layer 130 is, for example, a silicon layer.
In some embodiments, the isolation layer 130 contains doped ions, thereby improving conductivity and isolation effect.
The thickness of the isolation layer 130 ranges from 40 to 200 nm.
The isolation layer 130 is connected to a first predetermined potential, thereby forming an electrostatic shield between the first electronic component and the second electronic component 151. The first predetermined potential is 0 v, for example, alternating the isolation layer 130 to ground; in addition, the isolating layer 130 can also be connected to other controllable potentials, which can in principle be adjusted within the withstand voltage range.
Therefore, the first electronic component and the second electronic component are integrated on one semiconductor chip and are separated by the isolating layer, so that the integration level of the semiconductor chip is improved, the electrical interference between the first electronic component and the second electronic component is avoided to a great extent, and the working stability of each electronic component in the semiconductor chip is ensured.
On the basis, the embodiment of the invention also provides a semiconductor chip, wherein the semiconductor chip is provided with a double silicon-on-insulator D-SOI structure, and the D-SOI structure comprises a first semiconductor layer, a second semiconductor layer and an insulating layer positioned between the first semiconductor layer and the second semiconductor layer; a first electronic component is formed on the first semiconductor layer and comprises a reverse conducting insulated gate bipolar transistor (RC-IGBT); and a second electronic component is formed on the second semiconductor layer and comprises at least one of a driving circuit, a control circuit, a monitoring circuit and a protection circuit.
Therefore, in specific application, the RC-IGBT and at least one of the corresponding driving circuit, the control circuit, the monitoring circuit and the protection circuit are integrated on the same semiconductor chip, and all parts can be connected without wires, so that higher integration level is realized; the driving circuit, the control circuit, the monitoring circuit and the protection circuit in the embodiment of the invention can realize high switching speed and low power consumption, eliminate Latch Up effect (Latch-Up effect) and have better temperature tolerance.
It is understood that the insulating layer in the present embodiment may also include the first insulating layer 120 and the second insulating layer 140, that is, the insulating layer may be a plurality of layers; in addition, the present embodiment does not exclude the case where there is an isolation layer 130 between the first semiconductor layer and the second semiconductor layer, or other structures.
Furthermore, an IPM is provided in an embodiment of the present invention, where the IPM includes at least one semiconductor chip described in any one of the above embodiments.
Fig. 2 is a schematic cross-sectional view of an IPM according to an embodiment of the present invention, as shown in the figure, the IPM further includes a lead frame 200, the lead frame 200 has an upper bridge chip mounting location 220 and a lower bridge chip mounting location 210, and at least one of the upper bridge chip mounting location 220 and the lower bridge chip mounting location 210 has the semiconductor chip 100 mounted thereon.
In one embodiment, the IPM is a 6-channel three-phase driving IPM; by integrating 6 semiconductor chips 100 according to any one of the above embodiments of the present invention, it is equivalent to integrating 6 IGBT chips, 6 FRD chips, and corresponding driving circuits.
The upper bridge chip mounting positions 220 and the lower bridge chip mounting positions 210 can be respectively three, namely, six chip mounting positions are provided in total; all or part of the six chip mounting sites are mounted with the semiconductor chip described in any one of the embodiments of the present invention.
The IPM provided by the embodiment of the invention is applied to a variable frequency air conditioner.
Therefore, the intelligent power module provided by the embodiment of the invention comprises at least one semiconductor chip, so that the integration level of the intelligent power module is improved, and the size of the module is reduced; the lead frame and other metal wires are used for providing electrical connection for the semiconductor chip, and the layout is simple and convenient; after encapsulation, the module is small in overall size and high in stability.
The technical features described in the embodiments of the present invention may be arbitrarily combined without conflict with each other.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (10)
1. A semiconductor chip includes a first semiconductor layer, a first insulating layer, an isolation layer, a second insulating layer, and a second semiconductor layer which are stacked in this order; wherein the content of the first and second substances,
forming a first electronic component on the first semiconductor layer;
forming a second electronic component on the second semiconductor layer;
along range upon range of direction, the vertical projection of first electronic components with the vertical projection of second electronic components is at least by the isolation layer covers, first preset electric potential is connected to the isolation layer to keep apart first electronic components with electric interference between the second electronic components.
2. The semiconductor chip of claim 1, wherein the first electronic component comprises a power device and the second electronic component comprises a driver circuit.
3. The semiconductor chip of claim 1, wherein the isolation layer is a semiconductor layer.
4. The semiconductor chip of claim 3, wherein the semiconductor layer is a silicon layer.
5. The semiconductor chip of claim 3 or 4, wherein the isolation layer contains dopant ions.
6. The semiconductor chip of claim 1, wherein the thickness of the isolation layer is in the range of 40-200 nm.
7. The semiconductor chip of claim 1, wherein the first predetermined potential is 0 volts.
8. A semiconductor chip having a dual silicon-on-insulator D-SOI structure comprising a first semiconductor layer, a second semiconductor layer, and an insulating layer between the first semiconductor layer and the second semiconductor layer; wherein the content of the first and second substances,
a first electronic component is formed on the first semiconductor layer and comprises a reverse conducting insulated gate bipolar transistor (RC-IGBT);
and a second electronic component is formed on the second semiconductor layer and comprises at least one of a driving circuit, a control circuit, a monitoring circuit and a protection circuit.
9. An intelligent power module IPM, comprising at least one semiconductor chip according to any one of claims 1 to 8.
10. The IPM of claim 9, wherein the IPM further comprises a lead frame having an upper bridge chip mounting site and a lower bridge chip mounting site thereon, at least one of said upper bridge chip mounting site and said lower bridge chip mounting site having said semiconductor chip mounted thereon.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910718545.9A CN112331673A (en) | 2019-08-05 | 2019-08-05 | Semiconductor chip and intelligent power module |
| PCT/CN2019/125111 WO2021022748A1 (en) | 2019-08-05 | 2019-12-13 | Semiconductor chip and smart power module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910718545.9A CN112331673A (en) | 2019-08-05 | 2019-08-05 | Semiconductor chip and intelligent power module |
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| CN112331673A true CN112331673A (en) | 2021-02-05 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070090400A1 (en) * | 2004-08-26 | 2007-04-26 | Hirokazu Fujimaki | Method of producing the same |
| US20070281438A1 (en) * | 2006-05-31 | 2007-12-06 | Lianjun Liu | Methods and apparatus for RF shielding in vertically-integrated semiconductor devices |
| CN107026216A (en) * | 2015-09-24 | 2017-08-08 | 拉碧斯半导体株式会社 | The manufacture method of semiconductor device and semiconductor device |
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| JP2012094720A (en) * | 2010-10-27 | 2012-05-17 | Sony Corp | Solid state image pick up device, semiconductor device, method for manufacturing solid state image pick up device and semiconductor device, and electronic apparatus |
| US9607942B2 (en) * | 2013-10-18 | 2017-03-28 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor device with patterned ground shielding |
| JP2018190766A (en) * | 2017-04-28 | 2018-11-29 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device, manufacturing method, imaging element, and electronic equipment |
| KR102309462B1 (en) * | 2018-06-28 | 2021-10-06 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | A three-dimensional memory device having a shielding layer and a method for forming a three-dimensional memory device |
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- 2019-12-13 WO PCT/CN2019/125111 patent/WO2021022748A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070090400A1 (en) * | 2004-08-26 | 2007-04-26 | Hirokazu Fujimaki | Method of producing the same |
| US20070281438A1 (en) * | 2006-05-31 | 2007-12-06 | Lianjun Liu | Methods and apparatus for RF shielding in vertically-integrated semiconductor devices |
| CN107026216A (en) * | 2015-09-24 | 2017-08-08 | 拉碧斯半导体株式会社 | The manufacture method of semiconductor device and semiconductor device |
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Application publication date: 20210205 |
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