CN112331657A - Forming method of packaging connection structure of three-dimensional memory and three-dimensional memory - Google Patents
Forming method of packaging connection structure of three-dimensional memory and three-dimensional memory Download PDFInfo
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Abstract
The invention provides a method for forming a packaging connection structure of a three-dimensional memory and the three-dimensional memory, based on the open etching principle of 'two dielectric layers + two times of etching', a first dielectric layer and a second dielectric layer are formed on a pad structure of the three-dimensional memory, and the etching rate of the second dielectric layer is obviously higher than that of the first dielectric layer when the second dielectric layer is etched, so that the first time of etching is stopped on the first dielectric layer, and the first dielectric layer and a part of the pad structure with the same depth are removed by combining with the second time of etching, thereby realizing the accurate control of the two times of etching depths, particularly the accurate control of the first time of etching depth, and neglecting the influence of the difference of the etching rates and the difference of the deposition thicknesses of the dielectric layers on the etching depths; through the accurate control of the etching depth twice, the over-etching phenomenon can be avoided, the damage of charges accumulated by continuous bombardment of over-etching ions and a generated electric field to a logic circuit structure in the three-dimensional memory is reduced, and the reliability of the three-dimensional memory is enhanced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a packaging connection structure of a three-dimensional memory and the three-dimensional memory.
Background
The three-dimensional memory is a technology for stacking data units, can realize the stacking of 32 layers or more of data units at present, overcomes the limitation of the practical expansion limit of a plane memory, further improves the storage capacity, reduces the storage cost of each data bit, and reduces the energy consumption.
In the packaging and connecting process of the conventional three-dimensional memory, after a bonding pad electrically connected with a metal interconnection structure is formed on the top of the three-dimensional memory, a dielectric layer at least covering the bonding pad is directly formed on the top of the three-dimensional memory, and then the dielectric layer on the bonding pad is etched to open and expose a part of the bonding pad, so as to ensure that a plurality of bonding pads on the top of the three-dimensional memory can be opened and exposed, a groove is inevitably etched on the bonding pad by over-etching to a certain degree, but the over-etching depth of the bonding pad cannot be effectively and accurately controlled due to the difference between the thickness of the dielectric layer on the bonding pad in different areas and the etching rate; meanwhile, the bonding pad is continuously bombarded by plasma, and the accumulated charges and the generated electric field can influence and even damage logic circuits inside the three-dimensional memory, so that the reliability of the three-dimensional memory is reduced.
Therefore, how to avoid the damage of the circuit structure in the three-dimensional memory caused by the ion bombardment when the top bonding pad of the three-dimensional memory is subsequently opened is a problem to be solved urgently at present.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for forming a package connection structure of a three-dimensional memory based on opening pads by two etching operations, so as to solve the above-mentioned technical problems.
To achieve the above and other related objects, the present invention provides a method for forming a package connection structure of a three-dimensional memory, including:
providing a three-dimensional memory, wherein a first surface of the three-dimensional memory is provided with an exposed bonding pad structure;
forming a first dielectric layer on a first surface of the three-dimensional memory, the first dielectric layer covering at least the pad structure;
forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least covers the first dielectric layer, and the etching rate of the second dielectric layer is higher than that of the first dielectric layer when the second dielectric layer is etched;
carrying out first etching to remove the second dielectric layer on the region to be etched, wherein the first etching is stopped on the first dielectric layer;
and performing second etching to remove the first dielectric layer on the area to be etched and a part of the pad structure on the area to be etched, wherein the second etching stays in the pad structure, and a groove is formed in the pad structure.
Optionally, the region to be etched refers to a local area of a projection of the pad structure in a vertical direction of the first surface of the three-dimensional memory.
Optionally, the first surface of the three-dimensional memory has a plurality of the pad structures, and the step of forming the first dielectric layer on the first surface of the three-dimensional memory includes:
cleaning at least a first surface of the three-dimensional memory;
depositing the first dielectric layer on the first surface of the three-dimensional memory, wherein the first dielectric layer at least covers a plurality of pad structures.
Optionally, the step of forming the second dielectric layer on the first dielectric layer comprises:
cleaning at least the exposed surface of the first dielectric layer;
depositing the second dielectric layer on the first dielectric layer.
Optionally, after forming the second dielectric layer and before performing the first etching, the method for forming the package connection structure of the three-dimensional memory further includes:
and cleaning at least the exposed surface of the second dielectric layer.
Optionally, the step of performing the first etching includes:
etching by using first plasma along the vertical direction of the first surface of the three-dimensional memory to remove the second dielectric layers on the regions to be etched;
and the plurality of areas to be etched correspond to the plurality of bonding pad structures one to one.
Optionally, after the performing the first etching and before the performing the second etching, the method for forming the package connection structure of the three-dimensional memory further includes:
and cleaning at least the etching area etched for the first time.
Optionally, the step of performing the second etching includes:
and etching by using second plasma along the vertical direction of the first surface of the three-dimensional memory, removing the first dielectric layers on the areas to be etched, removing a part of the pad structures on the areas to be etched, and forming a groove in each pad structure.
Optionally, the pad structure includes a metal blocking layer, a metal pad layer, and a pad blocking layer, the metal blocking layer is electrically connected to the metal interconnection structure in the three-dimensional memory, the metal pad layer is disposed on the metal blocking layer, the pad blocking layer is disposed on the metal pad layer, the first dielectric layer is at least disposed on the pad blocking layer, and the second etching is performed in the metal pad layer.
Optionally, after the second etching, the method for forming the package connection structure of the three-dimensional memory further includes:
cleaning at least the etching area of the second etching;
and forming a metal connecting structure in the groove, and electrically leading out the pad structure through the metal connecting structure.
Optionally, the metal connection structure at least comprises: metal wire structure, metal ball structure.
Further, to achieve the above and other related objects, the present invention provides a three-dimensional memory including:
a substrate;
the storage structure layer is arranged on the substrate and comprises a storage array structure and a logic circuit which are mutually independent, and the storage array structure is electrically connected with the logic circuit;
a metal interconnection layer disposed on the memory structure layer and including a plurality of pad structures electrically connected to the logic circuit;
a first dielectric layer disposed on the metal interconnect layer, at least covering the pad structure;
and the second dielectric layer is arranged on the first dielectric layer and at least covers the first dielectric layer.
Optionally, the storage structure layer includes:
the storage array structure layer is arranged on the substrate and is internally provided with the storage array structure;
and the CMOS circuit structure layer is arranged on the storage array structure layer, and a plurality of mutually independent logic circuits are arranged in the CMOS circuit structure layer.
Optionally, the etching rate of the second dielectric layer is higher than that of the first dielectric layer, and the first dielectric layer is used as an etching stop layer when the second dielectric layer is etched.
Optionally, the first dielectric layer includes silicon nitride and silicon oxynitride, and the second dielectric layer includes silicon oxide.
Optionally, the three-dimensional memory further comprises a metal connection structure, wherein the metal connection structure penetrates through the second dielectric layer and the first dielectric layer and is electrically connected with the pad structure to electrically lead out the pad structure.
Optionally, the metal connection structure at least comprises: metal wire structure, metal ball structure.
As described above, the method for forming the package connection structure of the three-dimensional memory provided by the invention has the following beneficial effects:
forming a first dielectric layer and a second dielectric layer which are sequentially stacked from bottom to top on a pad structure of the three-dimensional memory, wherein the etching rate of the second dielectric layer is higher than that of the first dielectric layer when the second dielectric layer is etched, removing the second dielectric layer on a local area of the pad structure through first etching, and removing the first dielectric layer on a region to be etched and a part of the pad structure on the region to be etched through second etching; because the etching rate of the second dielectric layer is higher than that of the first dielectric layer when the second dielectric layer is etched, the thickness difference of the second dielectric layer on the local areas of the pad structures and the difference of the first etching rate can be ignored, so that the first etching on the local areas of the pad structures stays on the first dielectric layer, and the first dielectric layer and a part of the pad structures with the same depth are removed on the local areas of the pad structures by combining with the second etching, so that the depth of the two times of etching is accurately controllable, especially the depth of the first etching is accurately controllable, and the etching control precision when the top metal pad of the three-dimensional memory is opened is enhanced; meanwhile, based on the open etching principle of 'two dielectric layers + two times of etching', the first etching on the local areas of the pad structures is stopped on the first dielectric layer, and the over-etching which occurs when the thickness of the dielectric layer on the partial pad structures is thinner and the etching rate is higher in the open etching principle of 'one dielectric layer + one time of etching' can be effectively avoided, so that the damage of charges accumulated by long-time ion bombardment and generated electric fields caused by the over-etching to the logic circuit structure in the three-dimensional memory can be reduced, and the reliability of the three-dimensional memory is enhanced.
Drawings
Fig. 1-2 are process flow diagrams illustrating a method for forming a package connection structure of a three-dimensional memory.
FIG. 3 is a schematic diagram showing a method for forming a package connection structure of a three-dimensional memory according to the present invention.
Fig. 4-10 are process flow diagrams illustrating a method for forming a package connection structure of a three-dimensional memory according to the present invention.
FIG. 11 is a schematic diagram of a three-dimensional memory according to the present invention.
Description of the reference numerals
1-three-dimensional memory, 1 a-first surface of three-dimensional memory 1, 10-substrate, 11-dielectric structure, 12-metal interconnection structure, 13-pad structure, 131-metal barrier layer, 132-metal pad layer, 133-pad barrier layer, 14-memory array structure layer, 2-dielectric layer, 20-CMOS circuit structure layer, 21-first dielectric layer, 22-second dielectric layer, 3-metal connection structure, A-region to be etched, and T-groove in pad structure 13.
Detailed Description
The inventor researches and discovers that: as shown in fig. 1, currently, in a package connection process of a three-dimensional memory, after a pad structure 13 electrically connected to a metal interconnection structure 12 is formed on a dielectric structure 11 on the top of the three-dimensional memory 1, a dielectric layer 2 at least covering the pad structure 13 is formed directly on the dielectric structure 11; etching and opening the dielectric layer 2 on the pad structure 13, as shown in fig. 2, exposing a part of the pad structure 13, inevitably performing a certain degree of over-etching to etch the pad structure 13 into a groove in order to ensure that the plurality of pad structures 13 on the top of the three-dimensional memory 1 can be opened and exposed, but due to the difference between the thickness and the etching rate of the dielectric layer 2 on the pad structures 13 in different areas, the final over-etching depth of the pad structures 13 cannot be effectively and accurately controlled; meanwhile, the pad structure 13 is continuously bombarded by plasma, and the accumulated charges and the generated electric field affect or even damage logic circuits (not shown) inside the three-dimensional memory 1, resulting in a decrease in reliability of the three-dimensional memory 1.
Therefore, the invention provides a forming method of a three-dimensional memory packaging connection structure based on two dielectric layers and two etching steps, which comprises the following steps: forming a first dielectric layer and a second dielectric layer which are from bottom to top on the pad structure, wherein the etching rate of the second dielectric layer is obviously higher than that of the first dielectric layer when the second dielectric layer is etched, then etching twice, the thickness difference of the second dielectric layers on the pad structures and the difference of the first etching rate can be ignored, so that the first etching on the pad structures is stopped on the first dielectric layer, and then the second etching is combined to remove the first dielectric layers and a part of the pad structures with the same depth on the pad structures, so as to enhance the control precision of the two etching depths, especially the etching depth of the first etching; meanwhile, through the precise control of the etching depth twice, the over-etching which occurs when the dielectric layer on part of the bonding pad structure is thinner and the etching speed is faster can be avoided, so that the damage of the charges accumulated by the continuous bombardment of over-etching ions and the generated electric field to the logic circuit structure in the three-dimensional memory can be reduced.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 11. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. The structures, proportions, sizes, and other dimensions shown in the drawings and described in the specification are for understanding and reading the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined in the claims, and are not essential to the art, and any structural modifications, changes in proportions, or adjustments in size, which do not affect the efficacy and attainment of the same are intended to fall within the scope of the present disclosure. In addition, the terms "upper", "lower", "middle", "surface" and "first" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the relative relationship may be changed or adjusted without substantial technical change.
As shown in fig. 3, the present invention provides a method for forming a package connection structure of a three-dimensional memory, which comprises the steps of:
s1, providing the three-dimensional memory 1, wherein the first surface 1a of the three-dimensional memory 1 is provided with an exposed bonding pad structure 13;
s2, forming a first dielectric layer 21 on the first surface 1a of the three-dimensional memory 1, the first dielectric layer 21 at least covering the pad structure 13;
s3, forming a second dielectric layer 22 on the first dielectric layer 21, wherein the second dielectric layer 22 at least covers the first dielectric layer 21, and the etching rate of the second dielectric layer 22 is higher than that of the first dielectric layer 21 when the second dielectric layer 22 is etched;
s4, carrying out first etching to remove the second dielectric layer 22 on the area A to be etched, wherein the first etching is stopped on the first dielectric layer 21;
s5, performing second etching to remove the first dielectric layer 21 on the area A to be etched and a part of the pad structure 13 on the area A to be etched, wherein the second etching stays in the pad structure 13, and a groove T is formed in the pad structure 13;
the region to be etched a refers to a projected local region of the pad structure 13 in the vertical direction of the first surface 1a of the three-dimensional memory 1.
In detail, as shown in fig. 4, in step S1, the three-dimensional memory 1 provided includes a dielectric structure 11, a metal interconnection structure 12, a pad structure 13, a CMOS logic circuit structure (located in a middle lower layer, not shown in the figure) and a memory array structure (located in a middle lower layer, not shown in the figure), the CMOS logic circuit structure is electrically connected to the memory array structure, the metal interconnection structure 12 located in a top layer is electrically connected to the CMOS logic circuit structure located in the middle lower layer, the metal interconnection structure 12 is disposed in the dielectric structure 11 located in the top layer, the pad structure 13 is disposed on the dielectric structure 11 and electrically connected to the metal interconnection structure 12, and the pad structure 13 is exposed to the outside on the first surface 1a of the three-dimensional memory 1.
In more detail, as shown in fig. 4, in step S1, the pad structure 13 includes a metal barrier layer 131, a metal pad layer 132, and a pad barrier layer 133, the metal barrier layer 131 is electrically connected to the metal interconnect structure 12 in the three-dimensional memory 1, the metal pad layer 132 is disposed on the metal barrier layer 131, and the pad barrier layer 133 is disposed on the metal pad layer 132.
The metal barrier layer 131 is mainly used as a diffusion permeation prevention barrier layer for the metal interconnection structure 12 and the metal pad layer 132, and simultaneously, the electrical connection between the two is realized; the pad barrier layer 133 mainly serves as a barrier layer against diffusion and permeation of the metal pad layer 132 and a dielectric layer subsequently formed on the metal pad layer 132.
In detail, the first surface 1a of the three-dimensional memory 1 has a plurality of pad structures 13, and the step S2 of forming the first dielectric layer 21 on the first surface 1a of the three-dimensional memory 1 further includes:
s21, cleaning at least the first surface 1a of the three-dimensional memory 1;
s22, depositing a first dielectric layer 21 on the first surface 1a of the three-dimensional memory 1, wherein the first dielectric layer 21 at least covers the plurality of pad structures 13.
In more detail, in step S21, before the first dielectric layer 21 is formed by deposition, the first surface 1a of the three-dimensional memory 1 or all surfaces of the three-dimensional memory 1 are cleaned to remove dust, oil or other impurities such as metal particles remaining on the deposition surface.
In more detail, in step S22, a first dielectric layer 21 is formed on the first surface 1a of the three-dimensional memory 1, and the first dielectric layer 21 at least covers the exposed pad structures 13, that is, the first dielectric layer 21 is at least disposed on the pad blocking layer 133, so as to cover and protect the pad structures 13; alternatively, as shown in fig. 5, the first dielectric layer 21 is formed to cover all regions of the first surface 1a of the three-dimensional memory 1.
In detail, the step S3 of forming the second dielectric layer 22 on the first dielectric layer 21 further includes:
s31, cleaning at least the exposed surface of the first dielectric layer 21;
s32, depositing a second dielectric layer 22 on the first dielectric layer 21.
In more detail, in step S31, before the second dielectric layer 22 is deposited, the exposed surface of the first dielectric layer 21 or all surfaces of the entire device are cleaned to remove at least the impurities remaining on the exposed surface of the first dielectric layer 21.
In more detail, in step S32, a second dielectric layer 22 is formed on the first dielectric layer 21, the second dielectric layer 22 at least covers the first dielectric layer 21, and the etching rate of the second dielectric layer 22 is higher than that of the first dielectric layer 21 when the second dielectric layer 22 is etched, the first dielectric layer 21 is used as an etching stop layer when the second dielectric layer 22 is etched; alternatively, as shown in fig. 6, the second dielectric layer 22 just covers the first dielectric layer 21. The etching rate of the second dielectric layer 22 is significantly higher than that of the first dielectric layer 21 when the second dielectric layer 22 is etched (i.e. the etching selectivity of the second dielectric layer 22 relative to the first dielectric layer 21 is higher when the second dielectric layer 22 is etched), and the thickness of the second dielectric layer 22 is greater than that of the first dielectric layer 21.
Alternatively, the first dielectric layer 21 may comprise silicon nitride, silicon oxynitride, etc., and the second dielectric layer 22 may comprise silicon oxide, etc. The material of the first dielectric layer 21 and the second dielectric layer 22 is not limited as long as the condition that the etching rate of the second dielectric layer 22 is higher than the etching rate of the first dielectric layer 21 when the second dielectric layer 22 is etched is satisfied. Optionally, after forming the second dielectric layer 22 and before performing the first etching, i.e., between step S3 and step S4, the method for forming the package connection structure of the three-dimensional memory further includes the steps of:
at least the exposed surface of the second dielectric layer 22 is cleaned to remove the impurities remaining on the exposed surface of the second dielectric layer 22, so as to prevent the impurities from affecting the subsequent etching precision.
In detail, the step S4 of performing the first etching includes:
as shown in fig. 7, the second dielectric layer 22 on the plurality of regions to be etched a is removed by etching with the first plasma along the vertical direction of the first surface 1a of the three-dimensional memory 1, and the first etching on the plurality of regions to be etched a is stopped on the first dielectric layer 21.
As shown in fig. 7, the region to be etched a refers to a local region of a projection of the pad structure 13 in the vertical direction of the first surface 1a of the three-dimensional memory 1, that is, a position to be etched is a local part of a position occupied by the pad structure 13 on the first surface 1a of the three-dimensional memory 1, and the etching exposes the local region of the pad structure 13; the plurality of areas A to be etched correspond to the plurality of pad structures 13 one by one; it is understood that only one pad structure 13 and one region to be etched a are shown in fig. 6-7.
Optionally, after the performing of the first etching and before the performing of the second etching, that is, between step S4 and step S5, the method for forming the package connection structure of the three-dimensional memory further includes:
and cleaning at least the etching area etched for the first time to remove the residual impurities on the etching area so as to prevent the influence of the impurities on the second etching.
In detail, the step S5 of performing the second etching includes:
as shown in fig. 8, etching is performed by using the second plasma along the vertical direction of the first surface 1a of the three-dimensional memory 1, so as to remove the first dielectric layer 21 on the plurality of regions to be etched a and remove a portion of the pad structures 13 on the plurality of regions to be etched a, a groove T is formed in each pad structure 13, and the second etching on the plurality of regions to be etched a stays in the metal pad layer 132.
Optionally, after the second etching, the method for forming the package connection structure of the three-dimensional memory further includes:
s6, at least cleaning the etching area of the second etching to remove the residual impurities after etching;
s7, as shown in fig. 9-10, forming a metal connection structure 3 in the groove T, the opening formed by etching the first dielectric layer 21, and the opening formed by etching the second dielectric layer 22, and electrically leading out the pad structure 13 through the metal connection structure 3.
Optionally, the metal connection structure 3 includes a metal ball structure as shown in fig. 9, and further includes a metal line structure as shown in fig. 10; and completing the electrical connection between the three-dimensional memory 1 and an external PCB or other wafer chips through the metal connecting structure 3.
Further, based on steps S1-S3, the present invention also obtains a three-dimensional memory as shown in fig. 11, which includes:
a substrate 10;
a memory structure layer disposed on the substrate 10 and including a memory array structure (not shown) and a logic circuit, which are independent of each other, the memory array structure being electrically connected to the logic circuit;
a metal interconnection layer disposed on the memory structure layer and including a plurality of pad structures 13 electrically connected to the logic circuit;
a first dielectric layer 21 disposed on the metal interconnection layer, covering at least the pad structure 13;
the second dielectric layer 22 is disposed on the first dielectric layer 21 and at least covers the first dielectric layer 21.
In detail, as shown in fig. 11, the storage structure layer includes:
a memory array structure layer 14 disposed on the substrate 10, wherein a memory array structure (not shown) is disposed therein;
the CMOS circuit structure layer 20 is disposed on the memory array structure layer 14, and a plurality of independent logic circuits (the rounded rectangular frames shown in fig. 11) are disposed therein, and the logic circuits may be a plurality of independent transistor structures formed in corresponding substrates.
The memory array structure includes a gate layer, a conductive channel structure, and the like, and the detailed process structure can refer to the prior art and is not described herein again.
In detail, as shown in fig. 11, the metal interconnection layer includes a metal interconnection structure 12 and a pad structure 13, a portion of the metal interconnection structure 12 is electrically connected to the memory array structure and the pad structure 13 at the same time, a portion of the metal interconnection structure 12 is electrically connected to the logic circuit and the pad structure 13 at the same time, and the memory array structure and the logic circuit are electrically connected through the metal interconnection layer.
In detail, as shown in fig. 11, a first dielectric layer 21 and a second dielectric layer 22 are formed on the pad structure 13, and an etching rate of the second dielectric layer 22 is (significantly) higher than an etching rate of the first dielectric layer 21 when the second dielectric layer 22 is etched, the first dielectric layer 21 is used as an etching stop layer when the second dielectric layer 22 is etched, that is, a first etching stops on the first dielectric layer 21 when the pad structure 13 is opened by two subsequent etches, and the first dielectric layer 21 and a part of the pad structure 13 with the same depth are removed on the pad structure 13 by combining with the second etching, so that the control accuracy of the two etching depths is enhanced; meanwhile, through the accurate control of the etching depth twice, the over-etching phenomenon can be avoided, and the damage of charges accumulated by continuous bombardment of over-etching ions and a generated electric field to a logic circuit structure in the three-dimensional memory is effectively reduced.
The first dielectric layer 21 includes silicon nitride, silicon oxynitride, and the like, the second dielectric layer 22 includes silicon oxide, and the specific materials of the first dielectric layer 21 and the second dielectric layer 22 are not limited as long as the condition that the etching rate of the second dielectric layer 22 is higher or significantly higher than the etching rate of the first dielectric layer 21 when the second dielectric layer 22 is etched is satisfied.
In detail, as shown in fig. 11, the three-dimensional memory further includes a metal connection structure 3, the metal connection structure 3 passes through the second dielectric layer 22 and the first dielectric layer 21 and is electrically connected to the pad structure 13, and the pad structure 13 is electrically led out.
Alternatively, as shown in fig. 11, the metal connection structure 3 includes at least: metal wire structure, metal ball structure.
In summary, in the package connecting method for the three-dimensional memory and the three-dimensional memory provided by the invention, based on the open etching principle of "two dielectric layers + two etching", a first dielectric layer and a second dielectric layer which are sequentially stacked from bottom to top are formed on the bonding pad structure of the three-dimensional memory, and the etching rate of the second dielectric layer is higher than that of the first dielectric layer when the second dielectric layer is etched, then, two times of etching are carried out, so that the first etching on the local area of the pad structure is stopped on the first dielectric layer, and then the second etching is combined to remove the first dielectric layer and a part of the pad structure with the same depth on the local area of the pad structure, therefore, the accurate control of the etching depth of the two times, particularly the accurate control of the etching depth of the first time is realized, and the influence of the difference of the etching rate and the difference of the deposition thickness of the dielectric layer on the etching depth can be ignored; meanwhile, based on the open etching principle of 'two dielectric layers + two times of etching', the over-etching phenomenon can be avoided through the precise control of the etching depth of the two times, the damage of charges accumulated by continuous bombardment of over-etching ions and a generated electric field to a logic circuit structure in the three-dimensional memory is effectively reduced, and the reliability of the three-dimensional memory is enhanced; in addition, based on the open etching principle of 'two dielectric layers + two times of etching', the corresponding process is mature, and the additional cost increase can be ignored.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (17)
1. A method for forming a packaging connection structure of a three-dimensional memory is characterized by comprising the following steps:
providing a three-dimensional memory, wherein a first surface of the three-dimensional memory is provided with an exposed bonding pad structure;
forming a first dielectric layer on a first surface of the three-dimensional memory, the first dielectric layer covering at least the pad structure;
forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least covers the first dielectric layer, and the etching rate of the second dielectric layer is higher than that of the first dielectric layer when the second dielectric layer is etched;
carrying out first etching to remove the second dielectric layer on the region to be etched, wherein the first etching is stopped on the first dielectric layer;
and performing second etching to remove the first dielectric layer on the area to be etched and a part of the pad structure on the area to be etched, wherein the second etching stays in the pad structure, and a groove is formed in the pad structure.
2. The method as claimed in claim 1, wherein the region to be etched refers to a projected local area of the pad structure in a vertical direction of the first surface of the three-dimensional memory.
3. The method as claimed in claim 2, wherein the first surface of the three-dimensional memory has a plurality of the pad structures, and the step of forming the first dielectric layer on the first surface of the three-dimensional memory comprises:
cleaning at least a first surface of the three-dimensional memory;
depositing the first dielectric layer on the first surface of the three-dimensional memory, wherein the first dielectric layer at least covers a plurality of pad structures.
4. The method as claimed in claim 3, wherein the step of forming the second dielectric layer on the first dielectric layer comprises:
cleaning at least the exposed surface of the first dielectric layer;
depositing the second dielectric layer on the first dielectric layer.
5. The method as claimed in claim 4, wherein after the step of forming the second dielectric layer and before the step of etching for the first time, the step of forming the package connection structure of the three-dimensional memory further comprises:
and cleaning at least the exposed surface of the second dielectric layer.
6. The method as claimed in claim 5, wherein the step of performing the first etching comprises:
etching by using first plasma along the vertical direction of the first surface of the three-dimensional memory to remove the second dielectric layers on the regions to be etched;
and the plurality of areas to be etched correspond to the plurality of bonding pad structures one to one.
7. The method as claimed in claim 6, wherein after the first etching and before the second etching, the method further comprises:
and cleaning at least the etching area etched for the first time.
8. The method as claimed in claim 7, wherein the step of performing the second etching comprises:
and etching by using second plasma along the vertical direction of the first surface of the three-dimensional memory, removing the first dielectric layers on the areas to be etched, removing a part of the pad structures on the areas to be etched, and forming a groove in each pad structure.
9. The method as claimed in any one of claims 1 to 8, wherein the pad structure includes a metal barrier layer, a metal pad layer and a pad barrier layer, the metal barrier layer is electrically connected to the metal interconnect structure in the three-dimensional memory, the metal pad layer is disposed on the metal barrier layer, the pad barrier layer is disposed on the metal pad layer, the first dielectric layer is disposed on at least the pad barrier layer, and the second etching is performed to stay in the metal pad layer.
10. The method for forming the packaging connection structure of the three-dimensional memory according to any one of claims 1 to 8, wherein after the second etching, the method for forming the packaging connection structure of the three-dimensional memory further comprises:
cleaning at least the etching area of the second etching;
and forming a metal connecting structure in the groove, and electrically leading out the pad structure through the metal connecting structure.
11. The method as claimed in claim 10, wherein the metal connection structure at least comprises: metal wire structure, metal ball structure.
12. A three-dimensional memory, comprising:
a substrate;
the storage structure layer is arranged on the substrate and comprises a storage array structure and a logic circuit which are mutually independent, and the storage array structure is electrically connected with the logic circuit;
a metal interconnection layer disposed on the memory structure layer and including a plurality of pad structures electrically connected to the logic circuit;
a first dielectric layer disposed on the metal interconnect layer, at least covering the pad structure;
and the second dielectric layer is arranged on the first dielectric layer and at least covers the first dielectric layer.
13. The three-dimensional memory according to claim 12, wherein the storage structure layer comprises:
the storage array structure layer is arranged on the substrate and is internally provided with the storage array structure;
and the CMOS circuit structure layer is arranged on the storage array structure layer, and a plurality of mutually independent logic circuits are arranged in the CMOS circuit structure layer.
14. The three-dimensional memory according to claim 12, wherein the etching rate of the second dielectric layer is higher than the etching rate of the first dielectric layer, and the first dielectric layer serves as an etching stop layer when the second dielectric layer is etched.
15. The three-dimensional memory according to claim 14, wherein the first dielectric layer comprises silicon nitride, silicon oxynitride, and the second dielectric layer comprises silicon oxide.
16. The three-dimensional memory according to claim 12 or 14, further comprising a metal connection structure passing through the second dielectric layer and the first dielectric layer and electrically connected with the pad structure, electrically leading out the pad structure.
17. The three-dimensional memory according to claim 16, wherein the metal connection structure comprises at least: metal wire structure, metal ball structure.
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