CN112331581A - Display substrate, preparation method thereof, display panel and display device - Google Patents

Display substrate, preparation method thereof, display panel and display device Download PDF

Info

Publication number
CN112331581A
CN112331581A CN202011323625.3A CN202011323625A CN112331581A CN 112331581 A CN112331581 A CN 112331581A CN 202011323625 A CN202011323625 A CN 202011323625A CN 112331581 A CN112331581 A CN 112331581A
Authority
CN
China
Prior art keywords
signal lines
adjacent signal
display
display substrate
adjacent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011323625.3A
Other languages
Chinese (zh)
Other versions
CN112331581B (en
Inventor
芦月
孙超超
赵祖彬
王腾飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Mianyang BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Mianyang BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Mianyang BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202011323625.3A priority Critical patent/CN112331581B/en
Publication of CN112331581A publication Critical patent/CN112331581A/en
Application granted granted Critical
Publication of CN112331581B publication Critical patent/CN112331581B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The application provides a display substrate, a preparation method thereof, a display panel and a display device. The display substrate comprises a display area and a bending area. The preparation method comprises the following steps: forming a plurality of signal wires which are arranged at intervals and test electrodes which are in one-to-one correspondence with the signal wires, wherein the signal wires extend from the display area to the bending area, and the signal wires are electrically connected with the corresponding test electrodes; for any two adjacent signal lines, applying voltage between the test electrodes corresponding to the two adjacent signal lines by using an electrical characteristic detector, and acquiring electrical parameters detected by the electrical characteristic detector; judging whether metal residue exists between the two adjacent signal wires according to the electrical parameters corresponding to the two adjacent signal wires; and if no metal residue exists between any two adjacent signal lines, a light emitting layer is formed in the display area.

Description

Display substrate, preparation method thereof, display panel and display device
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, a display panel, and a display device.
Background
An Organic Light-Emitting Diode (OLED) has the advantages of a wide viewing angle, a fast response, a high contrast ratio, and the like, and has been widely used in display devices.
In the preparation process, metal residue may occur in the bending area of the OLED display device between the display area and the binding area, and the residual metal may short-circuit the adjacent signal lines, thereby causing an abnormal picture displayed by the display panel.
Disclosure of Invention
According to a first aspect of embodiments of the present application, a method of manufacturing a display substrate is provided. The display substrate comprises a display area and a bending area; the preparation method comprises the following steps:
forming a plurality of signal wires which are arranged at intervals and test electrodes which are in one-to-one correspondence with the signal wires, wherein the signal wires extend from the display area to the bending area, and the signal wires are electrically connected with the corresponding test electrodes;
for any two adjacent signal lines, applying voltage between the test electrodes corresponding to the two adjacent signal lines by using an electrical characteristic detector, and acquiring electrical parameters detected by the electrical characteristic detector;
judging whether metal residue exists between the two adjacent signal wires according to the electrical parameters corresponding to the two adjacent signal wires;
and if no metal residue exists between any two adjacent signal lines, a light emitting layer is formed in the display area.
In one embodiment, the determining whether there is metal residue between two adjacent signal lines according to the electrical parameter corresponding to the two adjacent signal lines includes:
if the resistance value corresponding to the two adjacent signal lines is smaller than a first preset threshold value, determining that metal residue exists between the two adjacent signal lines;
if the resistance value corresponding to the two adjacent signal lines is greater than or equal to the first preset threshold value, determining that no metal residue exists between the two adjacent signal lines;
or,
the electrical parameter is a current value, and the method for judging whether metal residue exists between two adjacent signal lines according to the electrical parameter corresponding to the two adjacent signal lines comprises the following steps:
if the current values corresponding to the two adjacent signal lines are larger than a second preset threshold value, determining that metal residues exist between the two adjacent signal lines;
and if the current values corresponding to the two adjacent signal lines are smaller than or equal to the second preset threshold value, determining that no metal residue exists between the two adjacent signal lines.
In one embodiment, the test electrode and the signal line are completed in a one-time patterning process; and/or the presence of a gas in the gas,
the signal line is a data line.
In one embodiment, before forming the plurality of signal lines arranged at intervals and the test electrodes corresponding to the signal lines one to one, the preparation method further includes:
forming a plurality of superposed films, wherein the films are positioned in the display area and the bending area;
and etching the plurality of film layers to form a concave part in the bending area.
In one embodiment, the end portion of the signal line includes two branch structures, one of the branch structures is electrically connected with the corresponding test electrode, and the other branch structure is used for electrically connecting with a chip; and/or the presence of a gas in the gas,
the area range of the test electrode is 36100 mu m2～44100μm2。
According to a second aspect of the embodiments of the present application, there is provided a display substrate, the display substrate including a display area and a bending area;
the display substrate is also provided with a plurality of signal wires which are arranged at intervals and test electrodes which are in one-to-one correspondence with the signal wires, the signal wires extend from the display area to the bending area, and the signal wires are electrically connected with the corresponding test electrodes;
the display substrate further comprises a light emitting layer located on the signal line, and the light emitting layer is located in the display area.
In one embodiment, the thickness and material of the test electrode and the signal line are the same; and/or the presence of a gas in the gas,
the signal line is a data line.
In one embodiment, the display substrate forms a recess, and the recess is located in the bending region.
In one embodiment, the end portion of the signal line includes two branch structures, one of the branch structures is connected to the corresponding test electrode, and the other branch structure is used for connecting to a chip; and/or the presence of a gas in the gas,
the area range of the test electrode is 36100 mu m2～44100μm2。
According to a third aspect of embodiments of the present application, there is provided a display panel including the above display substrate.
According to a fourth aspect of embodiments of the present application, there is provided a display device including the display panel described above.
The embodiment of the application achieves the main technical effects that:
according to the display substrate, the manufacturing method of the display substrate, the display panel and the display device, the test electrodes which are in one-to-one correspondence with the signal lines are arranged, and the signal lines are electrically connected with the corresponding test electrodes, so that the electrical characteristic detector can be used for applying voltage between the test electrodes corresponding to the two adjacent signal lines, and whether metal residues exist between the two adjacent signal lines is judged according to the electrical parameters detected by the electrical characteristic detector. Therefore, the preparation method and the display substrate provided by the embodiment of the application can detect whether metal residues exist between the adjacent signal lines in the preparation process, are easy to operate, and stop the preparation of the display substrate when the metal residues exist between the adjacent signal lines, so that the cost waste caused by the continuous subsequent preparation process is prevented.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a display substrate according to an exemplary embodiment of the present disclosure;
FIG. 2 is a partial cross-sectional view of a location of a display substrate provided by an exemplary embodiment of the present application;
FIG. 3 is a partial cross-sectional view of another location of a display substrate provided by an exemplary embodiment of the present application;
fig. 4 is a schematic partial structure diagram of a display substrate according to an exemplary embodiment of the present disclosure.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It is to be understood that although the terms first, second, third, etc. may be used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
As described in the background art, in the manufacturing process, metal residue may occur in the bending region of the OLED display device between the display region and the binding region. The reason for this problem is that: a barrier layer and a buffer layer are arranged above a substrate of the display substrate, the barrier layer is generally made of organic materials, the buffer layer is made of inorganic materials, the buffer layer is etched in the bending area before the signal line is formed to form a groove, the buffer layer can be completely etched during etching, and therefore the part, located in the bending area, of the barrier layer is exposed; due to the fact that the organic material is easy to absorb water, the part, in contact with the organic material, of the metal layer deposited and formed on the organic material is easy to oxidize, the oxidized part of the metal layer is not easy to etch and remain when the metal layer is etched to form the signal line, and residual metal may cause short circuit of adjacent signal lines to affect display of the display device.
The embodiment of the application provides a display substrate, a preparation method of the display substrate, a display panel and a display device. The display substrate, the manufacturing method thereof, the display panel, and the display device in the embodiments of the present application are described in detail below with reference to the accompanying drawings. Features in the embodiments described below may complement or be combined with each other without conflict.
The embodiment of the application provides a preparation method of a display substrate. Referring to fig. 1, the preparation method includes the following steps 110 to 140.
Referring to fig. 2 and 3, the display substrate includes a display region 101 and a bending region 102. The bending region 102 may be adjacent to the display region 101. Referring to fig. 4, the display substrate may further include a bonding region 103, and the bending region 102 is located between the display region 101 and the bonding region 103.
In step 110, a plurality of signal lines arranged at intervals and test electrodes corresponding to the signal lines one to one are formed, the signal lines extend from the display area to the bending area, and the signal lines are electrically connected with the corresponding test electrodes.
In one embodiment, the test electrode 70 and the signal line 20 are completed in one patterning process. In this way, the test electrode 70 and the signal line 20 can be formed in the same process step, which helps to simplify the complexity of the manufacturing process. The test electrode 70 may be electrically connected to the signal line 20 through a connection line.
In one embodiment, the test electrode 70 may be located in the bending region 102, or may be located in a frame region of the display substrate. In other embodiments, the display substrate is formed on a glass substrate, and the test electrodes may be located in a blank area of the glass substrate. Thus, the test electrodes do not occupy the space of the display substrate.
In one embodiment, the signal line 20 is a data line. The test electrodes and the data lines can be completed in one patterning process. The display substrate may further include a thin film transistor including source and drain electrodes, and the source and drain electrodes, the data line, and the test electrode of the thin film transistor may be formed in a one-time patterning process. In other embodiments, the signal line 20 may be other types of signal lines, such as a scan line, a power line, and the like.
In one embodiment, before forming the plurality of signal lines arranged at intervals and the test electrodes corresponding to the signal lines one to one, the preparation method further includes: forming a plurality of superposed films, wherein the films are positioned in the display area and the bending area; and etching the plurality of film layers to form a concave part in the bending area.
By forming the concave portion in the bending region 102, the thickness of the portion of the display substrate located in the bending region 102 can be reduced, so that the thickness of the portion of the display substrate located in the bending region 102 is smaller than the thickness of the portion of the display substrate located in the display region 101, and the display substrate is more prone to bend in the bending region 102. After the display substrate is bent, the portion of the display substrate located in the bonding region 103 is bent to the back of the portion of the display substrate located in the display region 101.
In some embodiments, referring to fig. 2 and 3, the display substrate may further include a thin film transistor 30 and a capacitor 40, the thin film transistor 30 includes an active layer 31, a gate electrode 32, a source electrode 33, and a drain electrode 34, and the capacitor 40 includes a first plate 41 and a second plate 42. The plurality of layers may include a substrate 10, a barrier layer 21, a buffer layer 22, an active layer 31, a gate insulating layer 61, a gate electrode 32 and a first plate 41, a capacitor insulating layer 62, a second plate 42, and an interlayer dielectric layer 43.
In one embodiment, the forming a plurality of stacked film layers, and etching the plurality of film layers to form a recess in the bending area may include:
first, a substrate is provided.
In some embodiments, the substrate may be a flexible substrate, and the material of the flexible substrate may be one or more of PET (polyethylene terephthalate), PI (polyimide), and PC (polycarbonate). In other embodiments, the substrate may be a rigid substrate, and the material of the rigid substrate may be metal or glass.
And then, forming barrier layers and buffer layers which are alternately arranged on the substrate.
Referring to fig. 2, a barrier layer 21, a buffer layer 22, a barrier layer 23, and a buffer layer 24 are sequentially formed on a substrate 10. The material of the barrier layer may be PI, for example. The buffer layer 24 is made of, for example, silicon oxide or silicon nitride.
Subsequently, an active layer 31 is formed on the buffer layer 24. The active layer 31 is located in the display region 101.
Subsequently, a gate insulating layer 61 is formed on the active layer 31. The gate insulating layer 61 may be located at the display region 101, the bending region 102, and the binding region 103.
Subsequently, the film layer of the bending region 102 may be etched to form a recessed structure. In this step, the gate insulating layer 61 located in the bending region 102 is etched away, and the buffer layer 24 located in the bending region 102 may also be etched away, and the buffer layer 24 may be partially or completely etched away.
Subsequently, the gate electrode 32 and the first plate 41 are formed. The gate electrode 32 and the first electrode plate 41 are located in the display region 101, and the gate electrode 32 is located above the active layer 31.
Subsequently, a capacitance insulating layer 62 is formed over the gate electrode 32. The capacitor insulating layer 62 may be located in the display region 101, the bending region 102, and the binding region 103.
Subsequently, the second plate 42 is formed over the capacitor insulating layer 62. The second plate 42 is located above the first plate 41 and opposite to the first plate 41.
Subsequently, an interlayer dielectric layer 63 is formed over the second plate 42. The interlayer dielectric layer 63 may be located in the display region 101, the bending region 102, and the bonding region 103.
Subsequently, a contact hole penetrating the interlayer dielectric layer 63, the capacitor insulating layer 62, and the gate insulating layer 61 is formed in the display region 101, and the contact hole exposes a partial region of the active layer 31.
Subsequently, the capacitor insulating layer 62 and the interlayer dielectric layer 63 located in the bending region 102 are etched. If buffer layer 24 is not completely etched away prior to this step, buffer layer 24 may be etched away during this step, and buffer layer 24 may be partially or completely etched away.
In some embodiments, the step of forming a plurality of signal lines arranged at intervals and the signal lines comprises the following processes:
first, a metal layer is formed, and the metal layer covers the display region 101, the bending region 102, and the bonding region 103. A metal layer may be formed on the interlayer dielectric layer 63. The metal layer may include two titanium film layers and an aluminum film layer between the two titanium film layers. A metal layer is formed and a conductive portion is formed in the contact hole, and the source electrode 33 and the drain electrode 34 are electrically connected to the active layer 31 through the conductive portion in the corresponding contact hole.
Subsequently, the metal layer is subjected to patterning processing to form the source electrode 33, the drain electrode 34, the signal line 20, and the test electrode 70.
Referring to fig. 3 and 4, during the patterning process of the metal layer, a residual metal 22 may exist between two adjacent signal lines 20, and the residual metal 22 may electrically connect the two adjacent signal lines 20.
In step 120, for any two adjacent signal lines, an electrical characteristic detector is used to apply a voltage between the test electrodes corresponding to the two adjacent signal lines, and electrical parameters detected by the electrical characteristic detector are obtained.
In one embodiment, an electrical property tester (EPM) includes a plurality of probes, with one probe connected to a positive pole of an internal power source and one probe connected to a negative pole of the internal power source. When the electrical characteristic tester is used, the test electrode corresponding to one of the two adjacent signal lines is electrically connected to the probe connected to the positive electrode of the internal power supply, and the test electrode corresponding to the other signal line is electrically connected to the probe connected to the negative electrode of the internal power supply, so that the electrical characteristic tester applies a voltage between the test electrodes corresponding to the two adjacent signal lines.
In step 130, it is determined whether metal residue exists between the two adjacent signal lines according to the electrical parameters corresponding to the two adjacent signal lines.
The electrical parameters corresponding to the two adjacent signal lines refer to the electrical parameters detected by the electrical characteristic tester when the two adjacent signal lines are respectively connected to the internal power supply of the electrical characteristic tester through the probe.
When two adjacent signal lines are electrically connected through the metal left between the two adjacent signal lines, the electrical parameter detected by the electrical characteristic tester is different from the electrical parameter detected by the electrical characteristic tester when the two adjacent signal lines are not electrically connected, so that whether metal left exists between the two adjacent signal lines can be judged through the electrical parameter detected by the electrical characteristic tester.
In one embodiment, the electrical parameter is a resistance value. The judging whether metal residue exists between the two adjacent signal lines according to the electrical parameters corresponding to the two adjacent signal lines includes:
if the resistance value corresponding to the two adjacent signal lines is smaller than a first preset threshold value, determining that metal residue exists between the two adjacent signal lines;
and if the resistance value corresponding to the two adjacent signal lines is greater than or equal to the first preset threshold value, determining that no metal residue exists between the two adjacent signal lines.
The resistance values corresponding to the two adjacent signal lines refer to resistance values detected by the electrical characteristic tester when the two adjacent signal lines are respectively connected to an internal power supply of the electrical characteristic tester through the probe. When the metal 22 remaining between two adjacent signal lines 20 electrically connects the two adjacent signal lines 20, the metal 22 remaining between the two adjacent signal lines 20, and the power supply inside the electrical characteristic tester form a loop. The resistance value detected by the electrical characteristic tester is small at this time, and is, for example, generally a few tenths of ohms to a few tens of ohms. If there is no metal residue between two adjacent signal lines 20, the two adjacent signal lines 20 and the power supply inside the electrical characteristic tester cannot form a loop, and the resistance value detected by the electrical characteristic tester is large, for example, greater than 2000 ohms. Whether metal residues exist between two adjacent signal lines can be judged through the resistance value detected by the electrical characteristic tester, and the judgment is easy.
In some embodiments, the first preset threshold may be 2000 ohms.
In other embodiments, the electrical parameter is a current value. The judging whether metal residue exists between the two adjacent signal lines according to the electrical parameters corresponding to the two adjacent signal lines includes:
if the current values corresponding to the two adjacent signal lines are larger than a second preset threshold value, determining that metal residues exist between the two adjacent signal lines;
and if the current values corresponding to the two adjacent signal lines are smaller than or equal to the second preset threshold value, determining that no metal residue exists between the two adjacent signal lines.
The current value corresponding to the two adjacent signal lines refers to a current value detected by the electrical property tester when the two adjacent signal lines are respectively connected to an internal power supply of the electrical property tester through the probe. When the metal 22 remaining between two adjacent signal lines 20 electrically connects the two adjacent signal lines 20, the metal 22 remaining between the two adjacent signal lines 20, and the power supply inside the electrical characteristic tester form a loop. The current value detected by the electrical characteristic tester is greater than 0, for example, a few tenths of an ampere to a few amperes. If no metal remains between two adjacent signal lines 20, the two adjacent signal lines 20 and the power supply inside the electrical characteristic tester cannot form a loop, and the current value detected by the electrical characteristic tester is zero. Whether metal residues exist between two adjacent signal wires can be judged through the current value detected by the electrical characteristic tester, and the judgment is easy.
In some embodiments, the second preset threshold may be zero. Or the second preset threshold is slightly larger than zero.
In step 140, if no metal residue exists between any two adjacent signal lines, a light emitting layer is formed in the display region.
If the metal residue does not exist between the two adjacent signal lines, the situation that the adjacent signal lines are short-circuited is not caused, and abnormal display cannot be caused during display. Therefore, the subsequent preparation steps can be continued to form the light emitting layer in the display area so as to obtain the display substrate. If it is determined that there is metal residue between two adjacent signal lines, which indicates that there is a short circuit between the adjacent signal lines, it is necessary to repair the display substrate or stop the manufacturing of the display substrate to avoid the obtained display substrate being a defective product.
In one embodiment, referring to fig. 4, the end portion of the signal line 20 includes two branch structures 21, wherein one of the branch structures 21 is electrically connected to the corresponding test electrode 70, and the other branch structure 21 is used for electrically connecting to a chip. This arrangement facilitates electrical connection of both signal lines 20 and corresponding test electrodes 70 and signal lines 20 to the chip.
In one embodiment, the portion of the signal line 20 located at the bending region 102 may be provided with a plurality of through holes. The through holes can improve the flexibility of the signal wire 20 and reduce the risk of breaking the signal wire 20 when the bending region 102 is bent.
In one embodiment, the test electrode 70 has an area in the range of 36100 μm2～44100μm2. By such an arrangement, it is avoided that the area of the test electrode 70 is large to affect the arrangement of other elements, and the process is not easy to implement due to the small size of the test electrode 70. The area of the test electrode 70 may be 36100 μm, for example2、38000μm2、40000μm2、42000μm2、44100μm2And the like.
In some embodiments, the test electrodes 70 are rectangular, and the dimensions of the test electrodes 70 may be 200 μm by 200 μm, 190 μm by 190 μm, 190 μm by 200 μm, 190 μm by 210 μm, 210 μm by 210 μm, and the like.
In the method for manufacturing a display substrate according to the embodiment of the present application, by providing the testing electrodes corresponding to the signal lines 20 one to one, and electrically connecting the signal lines to the corresponding testing electrodes, a voltage may be applied between the testing electrodes corresponding to two adjacent signal lines by using an electrical characteristic detector, and whether metal residue exists between the two adjacent signal lines is determined according to electrical parameters detected by the electrical characteristic detector. Therefore, the preparation method provided by the embodiment of the application can detect whether metal residues exist between the adjacent signal lines in the preparation process, is easy to operate, stops the preparation of the display substrate when the metal residues exist between the adjacent signal lines, and prevents the cost waste caused by the continuous subsequent preparation process.
When the display substrate prepared by the preparation method of the display substrate provided by the embodiment of the application is tested in a lighting mode, all display pictures are normally displayed. When the display substrate with metal residues between the adjacent signal lines is subjected to a lighting test, the display picture is abnormal, including that the picture is purple red when the red sub-pixel is lighted, the picture is purple red when the blue sub-pixel is lighted, or other abnormalities and the like. It can be known that the quality of the prepared display substrate can be ensured by the preparation method of the display substrate provided by the embodiment of the application.
The embodiment of the application also provides a display substrate. Referring to fig. 2 to 4, the display substrate includes a display region 101 and a bending region 102.
The display substrate is further provided with a plurality of signal lines 20 arranged at intervals and test electrodes 70 corresponding to the signal lines 20 one by one, the signal lines 20 extend from the display area 101 to the bending area 102, and the signal lines 20 are electrically connected with the corresponding test electrodes 70.
The display substrate further includes a light emitting layer on the signal line 20, the light emitting layer being located in the display region 101.
The display substrate provided by the embodiment of the application, through setting up the test electrodes corresponding to the signal lines 20 one-to-one, and the signal lines are electrically connected with the corresponding test electrodes, can adopt the electrical characteristic detector to apply voltage between the test electrodes corresponding to two adjacent signal lines, and judges whether there is metal residue between the two adjacent signal lines according to the electrical parameters detected by the electrical characteristic detector. Therefore, the preparation method provided by the embodiment of the application can detect whether metal residues exist between the adjacent signal lines in the preparation process, is easy to operate, stops the preparation of the display substrate when the metal residues exist between the adjacent signal lines, and prevents the cost waste caused by the continuous subsequent preparation process.
In one embodiment, the thickness and material of the test electrode 70 and the signal line 20 are the same. In this way, the test electrode 70 and the signal line 20 can be formed in the same process step, which helps to simplify the complexity of the manufacturing process. The test electrode 70 may be electrically connected to the signal line 20 through a connection line.
In one embodiment, the signal line 20 is a data line. In other embodiments, the signal line 20 may be other types of signal lines, such as a scan line, a power line, and the like.
In one embodiment, the display substrate forms a recess, which is located in the bending region 102.
In one embodiment, the display substrate includes at least one insulating film layer hollowed out at the bending region 102 to form the recess. The at least one insulating film layer includes an interlayer dielectric layer 63, a capacitor insulating layer 62, and a gate insulating layer 61. The interlayer dielectric layer 63, the capacitor insulating layer 62 and the gate insulating layer 61 in the bending region 102 may be etched to make the insulating film hollowed out in the bending region 102. The buffer layer 24 may be etched when the film layer in the bending region 102 is etched, and the buffer layer 24 may be partially etched or completely etched.
In one embodiment, the end of the signal line 20 includes two branch structures 21, wherein one of the branch structures 21 is connected to the corresponding test electrode 70, and the other branch structure 21 is used for connecting to a chip.
In one embodiment, the test electrode 70 has an area in the range of 36100 μm2～44100μm2。
In one embodiment, the display substrate further includes a planarization layer over the signal lines and under the light emitting layer. The light emitting layer may include an anode, a cathode, and an organic light emitting material layer between the anode and the cathode. The display substrate may further include an encapsulation layer over the light emitting layer, and the encapsulation layer may be a thin film encapsulation layer.
For the product embodiment, since it basically corresponds to the method embodiment, the description of the relevant details and beneficial effects may refer to the partial description of the method embodiment, and will not be repeated.
The embodiment of the application also provides a display panel. The display panel comprises the display substrate of any one of the embodiments.
The display panel may further include a polarizer and a glass cover plate. The polaroid and the glass cover plate are positioned on one side of the display substrate, which is deviated from the substrate.
The embodiment of the application also provides a display device. The display device comprises the display panel.
The display device further comprises a shell, and the display panel can be embedded in the shell.
The display device provided by the embodiment of the application can be any equipment with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer and the like.
It is noted that in the drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. Also, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening layers may also be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may also be present. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intermediate layer or element may also be present. Like reference numerals refer to like elements throughout.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (11)

1. The preparation method of the display substrate is characterized in that the display substrate comprises a display area and a bending area; the preparation method comprises the following steps:
forming a plurality of signal wires which are arranged at intervals and test electrodes which are in one-to-one correspondence with the signal wires, wherein the signal wires extend from the display area to the bending area, and the signal wires are electrically connected with the corresponding test electrodes;
for any two adjacent signal lines, applying voltage between the test electrodes corresponding to the two adjacent signal lines by using an electrical characteristic detector, and acquiring electrical parameters detected by the electrical characteristic detector;
judging whether metal residue exists between the two adjacent signal wires according to the electrical parameters corresponding to the two adjacent signal wires;
and if no metal residue exists between any two adjacent signal lines, a light emitting layer is formed in the display area.
2. The method for manufacturing a display substrate according to claim 1, wherein the electrical parameter is a resistance value, and the determining whether metal residue exists between two adjacent signal lines according to the electrical parameter corresponding to the two adjacent signal lines comprises:
if the resistance value corresponding to the two adjacent signal lines is smaller than a first preset threshold value, determining that metal residue exists between the two adjacent signal lines;
if the resistance value corresponding to the two adjacent signal lines is greater than or equal to the first preset threshold value, determining that no metal residue exists between the two adjacent signal lines;
or,
the electrical parameter is a current value, and the method for judging whether metal residue exists between two adjacent signal lines according to the electrical parameter corresponding to the two adjacent signal lines comprises the following steps:
if the current values corresponding to the two adjacent signal lines are larger than a second preset threshold value, determining that metal residues exist between the two adjacent signal lines;
and if the current values corresponding to the two adjacent signal lines are smaller than or equal to the second preset threshold value, determining that no metal residue exists between the two adjacent signal lines.
3. The method of claim 1, wherein the testing electrode and the signal line are formed in a single patterning process; and/or the presence of a gas in the gas,
the signal line is a data line.
4. The method of claim 1, wherein before forming the plurality of signal lines arranged at intervals and the test electrodes corresponding to the signal lines one to one, the method further comprises:
forming a plurality of superposed films, wherein the films are positioned in the display area and the bending area;
and etching the plurality of film layers to form a concave part in the bending area.
5. The method of manufacturing a display substrate according to claim 1, wherein the end portion of the signal line includes two branch structures, one of the branch structures is electrically connected to the corresponding test electrode, and the other of the branch structures is used for electrically connecting to a chip; and/or the presence of a gas in the gas,
the area range of the test electrode is 36100 mu m2～44100μm2。
6. A display substrate is characterized by comprising a display area and a bending area;
the display substrate is also provided with a plurality of signal wires which are arranged at intervals and test electrodes which are in one-to-one correspondence with the signal wires, the signal wires extend from the display area to the bending area, and the signal wires are electrically connected with the corresponding test electrodes;
the display substrate further comprises a light emitting layer located on the signal line, and the light emitting layer is located in the display area.
7. The display substrate according to claim 6, wherein the thickness and material of the test electrode and the signal line are the same; and/or the presence of a gas in the gas,
the signal line is a data line.
8. The display substrate of claim 6, wherein the display substrate forms a recess, and the recess is located in the bending region.
9. The display substrate according to claim 6, wherein the end portion of the signal line comprises two branch structures, one of the branch structures is connected to the corresponding test electrode, and the other branch structure is used for connecting to a chip; and/or the presence of a gas in the gas,
the area range of the test electrode is 36100 mu m2～44100μm2。
10. A display panel comprising the display substrate according to any one of claims 6 to 9.
11. A display device characterized by comprising the display panel according to claim 10.
CN202011323625.3A 2020-11-23 2020-11-23 Display substrate, preparation method thereof, display panel and display device Active CN112331581B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011323625.3A CN112331581B (en) 2020-11-23 2020-11-23 Display substrate, preparation method thereof, display panel and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011323625.3A CN112331581B (en) 2020-11-23 2020-11-23 Display substrate, preparation method thereof, display panel and display device

Publications (2)

Publication Number Publication Date
CN112331581A true CN112331581A (en) 2021-02-05
CN112331581B CN112331581B (en) 2024-09-27

Family

ID=74322147

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011323625.3A Active CN112331581B (en) 2020-11-23 2020-11-23 Display substrate, preparation method thereof, display panel and display device

Country Status (1)

Country Link
CN (1) CN112331581B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120077408A1 (en) * 2009-06-29 2012-03-29 Yoshimitsu Tajima Device and method for manufacturing active matrix substrate, and device and method for manufacturing display panel
CN108231036A (en) * 2018-01-10 2018-06-29 广东欧珀移动通信有限公司 Display panel, display screen, electronic device, display control method and storage device
US20190025619A1 (en) * 2017-07-19 2019-01-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Test circuit for display panel and display device
CN110708790A (en) * 2019-11-13 2020-01-17 京东方科技集团股份有限公司 Light-emitting substrate and electronic device
CN213124380U (en) * 2020-11-23 2021-05-04 京东方科技集团股份有限公司 Display substrate, display panel and display device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120077408A1 (en) * 2009-06-29 2012-03-29 Yoshimitsu Tajima Device and method for manufacturing active matrix substrate, and device and method for manufacturing display panel
US20190025619A1 (en) * 2017-07-19 2019-01-24 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Test circuit for display panel and display device
CN108231036A (en) * 2018-01-10 2018-06-29 广东欧珀移动通信有限公司 Display panel, display screen, electronic device, display control method and storage device
CN110708790A (en) * 2019-11-13 2020-01-17 京东方科技集团股份有限公司 Light-emitting substrate and electronic device
CN213124380U (en) * 2020-11-23 2021-05-04 京东方科技集团股份有限公司 Display substrate, display panel and display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
林忱;冯玉春;陈曦;汤桂泉;李鑫;周贺;刘文瑞;贠向南;: "铜工艺阵列基板上数据线和公共电极不可见的短路原因分析及改善", 液晶与显示, no. 10, 24 September 2020 (2020-09-24) *

Also Published As

Publication number Publication date
CN112331581B (en) 2024-09-27

Similar Documents

Publication Publication Date Title
US9040974B2 (en) Organic light-emitting display apparatus
US11415621B2 (en) Crack detecting circuit and display panel
KR102137474B1 (en) Pad electrode structure and organic light-emitting display apparatus comprising the pad electrode structure
CN111162199B (en) Display panel and display device
WO2018205626A1 (en) Motherboard and display panel
WO2015027615A1 (en) Array substrate, and detecting method and manufacturing method therefor
CN110797351B (en) Array substrate, detection method thereof, display panel and display device
KR20130105144A (en) Organic light emitting display device and method for manufacturing the same
US8704309B2 (en) Display panel and method of manufacturing the same
CN110890409B (en) Display device, OLED panel thereof and manufacturing method of OLED panel
CN213124380U (en) Display substrate, display panel and display device
US11631619B2 (en) Array substrate and fabricating method thereof, display panel and display device
JP5830810B2 (en) Display panel and manufacturing method thereof
KR102490892B1 (en) Display apparatus and method of manufacturing the same
CN110752187B (en) Preparation method of display substrate and display substrate
CN103187017B (en) For the ageing system of display device and utilize the aging method of this ageing system
CN112331581B (en) Display substrate, preparation method thereof, display panel and display device
US20210091121A1 (en) Array substrate, method of manufacturing same, and display panel
CN112420751B (en) Display substrate, preparation method thereof and display device
CN112151593B (en) Display panel, testing method thereof and display device
CN113424251A (en) Array substrate and display device
JP2007012461A (en) Manufacturing method of organic electroluminescent display device, and organic electroluminescent display device
CN111781770B (en) Array substrate and manufacturing method thereof
WO2023130369A1 (en) Display substrate, display apparatus, and crack detection method for display substrate
CN114975557A (en) Display panel and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant