CN111243472A - Display panel mother board and display panel routing abnormity detection method - Google Patents
Display panel mother board and display panel routing abnormity detection method Download PDFInfo
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- CN111243472A CN111243472A CN202010152834.XA CN202010152834A CN111243472A CN 111243472 A CN111243472 A CN 111243472A CN 202010152834 A CN202010152834 A CN 202010152834A CN 111243472 A CN111243472 A CN 111243472A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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Abstract
The embodiment of the invention discloses a display panel mother board and a method for detecting abnormal routing of a display panel, wherein the display panel mother board comprises the following components: the substrate membrane layer comprises a first slope surface and a second slope surface, the metal routing layer comprises a first metal routing line and a second metal routing line, the first slope surface and the first metal routing line are located in the display panel area, at least part of the first metal routing line is located on the first slope surface, the second slope surface and the second metal routing line are located in a routing test area, at least part of the second metal routing line is located on the second slope surface, the second metal routing line is electrically connected with a test terminal, the second metal routing line and the test terminal are used for testing whether the second metal routing line is in a short circuit or not, and then whether the first metal routing line is in a short circuit or not is deduced. According to the technical scheme, whether the second metal wiring is short-circuited or not is determined through the resistance values between different test terminals, and whether the first metal wiring is short-circuited or not is further determined, so that the detection efficiency of the display panel wiring abnormity is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor testing, in particular to a display panel mother board and a method for detecting abnormal routing of a display panel.
Background
With the development of science and technology, the flexible display panel is more and more widely applied to display devices such as smart phones, tablet computers and notebook computers.
The signal line of the display area of the flexible display panel is electrically connected with the main control panel through the wiring arranged in the non-display area to acquire a driving signal, and then stable pictures are displayed.
In the process of manufacturing the display panel, the situation of short circuit of the wires may occur, and how to quickly determine whether the wires on the display wire surface are short-circuited is not a good method in the prior art.
Disclosure of Invention
In view of this, embodiments of the present invention provide a display panel motherboard and a method for detecting abnormal routing of a display panel, so as to improve the efficiency of detecting abnormal routing of the display panel.
The embodiment of the invention provides a display panel mother board, which comprises a mother board, a first substrate and a second substrate, wherein the mother board comprises a first substrate and a second substrate; the display panel mother board is divided into a display panel area and a routing test area adjacent to the display panel area, the substrate film layer comprises a first slope surface and a second slope surface, the metal routing layer comprises a first metal routing and a second metal routing, the first slope surface and the first metal routing are positioned in the display panel area, at least part of the first metal routing is located on the first slope surface, the second slope surface and the second metal routing are located in the routing test area, at least part of the second metal wire is positioned on the second slope surface, the second metal wire is electrically connected with a test terminal, the second metal wire and the test terminal are used for testing whether the second metal wire is short-circuited or not, and further deducing whether the first metal wire is short-circuited or not;
according to the technical scheme, whether the second metal wiring is short-circuited or not can be determined through the resistance values between different test terminals, whether the wiring of the first metal wiring is short-circuited or not is further determined, and the detection efficiency of the display panel wiring abnormity is improved.
Optionally, the routing test area includes a groove located on the substrate film layer, and a side of the groove is the second slope.
According to the technical scheme, most of the inorganic layers in most of the wiring test areas are removed, so that the wiring test areas have good bending performance and are completely consistent with the structure and the function of the non-display area of the flexible display panel in the display panel area.
Optionally, the second metal routing wire covers the second slope surface and a plane connected to the second slope surface, and extends from the second slope surface on a first side of the plane to a second slope surface on a second side opposite to the first side, where two adjacent metal routing wires are different in electrically connected test terminal;
preferably, the test terminals are located on the same side of the second metal trace.
According to the technical scheme, the second metal wiring in the wiring test area is ensured to be the same as the first metal wiring in the non-display area of the flexible display panel, the second metal wiring can be determined to be in a short circuit through the test terminal, and whether the first metal wiring in the display panel area is in a short circuit is further determined, so that the detection efficiency of the display panel wiring abnormity is improved.
Optionally, a distance that the second metal trace extends out of the second slope is greater than or equal to 8 micrometers.
In this technical scheme, the distance that second metal is walked the line and is extended the domatic second is too short, when being less than 8 microns, is unfavorable for and subsequent first short circuit connecting wire electricity to be connected.
Optionally, the test terminals include a first test terminal and a second test terminal;
the second metal wiring layer further comprises a first short circuit connecting wire which is electrically connected with the odd second metal wirings; at least one of the odd second metal wires is electrically connected with the first test terminal;
the second short circuit connecting wire is electrically connected with the even number of second metal wires; at least one of the second metal routing wires is electrically connected with the second test terminal;
preferably, the first short circuit connection line and the second short circuit connection line are located on different sides of the second metal trace.
In the technical scheme, different test signals are applied to the first test terminal and the second test terminal through the probe of the test equipment, the resistance value between the first test terminal and the second test terminal is obtained, namely the resistance value between the odd second metal wiring and the even second metal wiring is obtained, whether short circuit occurs between the second metal wirings is determined, and therefore whether short circuit exists between the first metal wiring in the flexible display panel area is determined.
Optionally, the trace test area further includes a dummy test terminal, and the dummy test terminal is not electrically connected to the second metal trace.
When testing, there are many probes on the test equipment, and when the quantity of test terminal was less than the quantity of probe, the probe that does not connect test terminal was damaged easily, therefore, this technical scheme sets up the dummy test terminal, can protect the probe not damaged.
Optionally, the test terminals include a first test terminal and at least two second test terminals; the wire test area also comprises a first short circuit connecting wire and at least two second short circuit connecting wires, and the odd number metal wires are electrically connected with the first short circuit connecting wire; at least one of the odd second metal wires is electrically connected with the first test terminal, the even second metal wires are respectively electrically connected with at least two second short circuit connecting lines, and each of the even second metal wires is electrically connected with one second short circuit connecting line; at least one of the second metal wires electrically connected with each second short circuit connecting wire is electrically connected with one second test terminal;
or, the test terminals include at least two of the first test terminals and the second test terminals; the line testing area further comprises at least two first short-circuit connecting lines and at least two second short-circuit connecting lines, the odd-numbered second metal lines are electrically connected with the at least two first short-circuit connecting lines respectively, and each odd-numbered second metal line is electrically connected with one first short-circuit connecting line; at least one of the odd second metal wires electrically connected with each first short circuit connecting wire is electrically connected with one first test terminal; the even number of second metal wires are electrically connected with the second short circuit connecting wire; at least one of the second even number of second metal wires is electrically connected with the second test terminal.
According to the technical scheme, the position of short circuit between the second metal wires can be further locked.
In a second aspect, an embodiment of the present invention provides a method for detecting abnormal routing of a display panel, which is applied to any display panel motherboard in the first aspect, and includes:
sending a first test signal to a test terminal of a wiring test area, detecting the test terminal to obtain a second test signal, and determining whether a second metal wiring of the wiring test area is short-circuited based on the first test signal and the second test signal so as to determine whether the first metal wiring of the display panel area is short-circuited and further deduce whether the wiring of the display panel is abnormal.
According to the technical scheme, whether the second metal wires in the wire test area are short-circuited or not can be detected, so that whether the first metal wires in the display panel area are short-circuited or not is determined, and whether the wires of the display panel are abnormal or not is further judged.
Optionally, sending a first test signal to a test terminal of a routing test area, detecting the test terminal to obtain a second test signal, and determining whether a second metal routing of the routing test area is short-circuited based on the first test signal and the second test signal to determine whether a first metal routing of a display panel area is short-circuited includes:
determining a resistance value between different ones of the test terminals based on the first test signal and the second test signal;
and if the resistance values between different test terminals are not equal to the preset resistance value, determining the second metal wiring short circuit so as to determine the first metal wiring short circuit in the display panel area.
The technical scheme can test whether the wiring on the display panel is abnormal or not by testing the resistance value of the second metal wiring.
Optionally, after determining that the second metal trace has a short circuit, the method further includes: acquiring an image signal of the second metal wiring through an image sensor;
and determining the short circuit position of the second metal wire and the short circuit position of the first metal wire in the display panel area based on the image signal of the second metal wire.
According to the technical scheme, the image signals of the second metal wires can be collected through the image sensor, and the positions of metal residues between the second metal wires are locked, so that the short circuit position of the second metal wires and the abnormal position of the wires on the display panel are determined.
According to the technical scheme, one part of the second metal wiring is located on the slope surface of the second, the second metal wiring is electrically connected with the test terminal, the second metal wiring layer and the test terminal are used for testing whether the second metal wiring is short-circuited, and then whether the first metal wiring is short-circuited is determined.
Drawings
Fig. 1 is a schematic structural diagram of a flexible display panel in a state where a non-display area is bent in the prior art;
fig. 2 is a schematic structural diagram of a specific film layer of the flexible display panel in fig. 1;
FIG. 3 is a top view of the metal trace of FIG. 2;
fig. 4 is a top view of a display panel motherboard according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional structure diagram of the display area, the non-display area and the trace detection area in fig. 4;
fig. 6 is a top view of one of the trace testing areas of fig. 4.
FIG. 7 is a top view of another trace testing area shown in FIG. 4;
FIG. 8 is a top view of another trace testing area shown in FIG. 4;
fig. 9 is a flowchart of a method for detecting abnormal routing of a display panel according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background art, in the process of manufacturing the conventional flexible display panel, the situation of short-circuit of the traces may occur, and the inventors have found through careful research that the reason for this technical problem is that, taking the flexible display panel 100 as an example for illustration, fig. 1 is a schematic structural diagram of the non-display area of the flexible display panel in the prior art in a bent state; fig. 2 is a schematic structural diagram of a specific film layer of the flexible display panel in fig. 1; fig. 3 is a top view of the metal trace in fig. 2. Referring to fig. 1, 2 and 3, the flexible display panel 100 includes a display area AA and a non-display area NA located at one side of the display area AA, and the non-display area NA is bent and electrically connected to the flexible circuit board at the back of the flexible display panel 100 through a connection pad 150 disposed on the non-display area NA, so that the display area AA can obtain a required driving signal. Since a portion of the inorganic layer, which illustratively includes the interlayer insulating layer 14, the capacitor insulating layer 13, the gate insulating layer 12, the buffer layer 11, and a portion of the inorganic layer of the flexible substrate 10, needs to be etched away for the non-display area NA in the process of manufacturing the flexible display panel 100, so as to obtain a better bending performance. After the etching is completed, a slope is formed, which results in that when the metal trace 15 exists as a metal layer before being patterned, the thickness of the gentle region NA2 at the slope region NA1 is thinner, and the thickness of the subsequently formed photoresist layer 16 at the slope region NA1 is thicker than that of the gentle region NA 2. In the patterning process, namely, in the process of forming a plurality of metal wires 15 (electrically connected to the signal lines in the display area AA), in the exposure process of the photoresist layer 16, the thickness of the photoresist layer 16 at the slope area NA1 is thick, and the photoresist layer cannot be fully exposed and developed to form residual photoresist, so that subsequent metal etching residues are caused, metal residues can be formed between the metal wires 15, short circuits between the metal wires 15 are caused, and the abnormal wiring on the display panel is shown. However, how to determine whether the wires are short-circuited is not a good test method in the prior art.
In order to solve the technical problems, the invention provides the following solutions:
fig. 4 is a top view of a mother board of a display panel according to an embodiment of the present invention, and fig. 5 is a schematic cross-sectional structure diagram corresponding to the display area, the non-display area, and the trace detection area in fig. 4; fig. 6 is a top view of the trace testing area in fig. 4. Referring to fig. 4, 5 and 6, the display panel mother substrate includes: the display panel mother board is divided into a display panel area B1 and a routing test area B2 adjacent to the display panel area B1, the substrate film layer 30 comprises a first slope 300A and a second slope 300B, the metal routing layer comprises a first metal routing 50 and a second metal routing 51, the first slope 300A and the first metal routing 50 are located in the display panel area B1, at least part of the first metal routing 50 is located on the first slope 300A, the second slope 300B and the second metal routing 51 are located in the routing test area B2, at least part of the second metal routing 51 is located on the second slope 300B, the second metal routing 51 is electrically connected with a test terminal 60, and the second metal routing 51 and the test terminal 60 are used for testing whether the second metal routing 51 is short-circuited or not, so as to infer whether the first metal routing 50 is short-circuited or not.
Exemplarily, fig. 4 shows at least two display panel regions B1, a display panel region B1 is provided with the display panel 200; the trace test area B2 and the trace test area B2 are located between the adjacent display panel areas B1.
It should be noted that, the display panel motherboard in the prior art includes a display panel area, and a test circuit is usually manufactured in a non-display area of the display panel included in the display panel area to test whether the wires on the display panel are short-circuited, wherein the test circuit side needs to be cut after completing the test, and the wires on the display panel are easily damaged irreversibly in the cutting process, which affects subsequent manufacturing processes, thereby reducing the yield of the display panel.
The display panel mother board provided by the embodiment of the invention is provided with the independent display panel area B1 and the wiring test area B2, the wiring test area B2 and the display area 201 and the non-display area 2021 of the flexible display panel 200 arranged in the display panel area B1 are simultaneously prepared, and the structure and the film layer are the same as the non-display area 2021. Therefore, if the second metal trace 51 in the trace test area B2 is short-circuited, the first metal trace 50 in the non-display area 2021 on the flexible display panel is also short-circuited inevitably; the second metal trace 51 in the trace test area B2 is not shorted, and the first metal trace 50 in the non-display area 2021 on the flexible display panel is also not shorted. Therefore, it can be determined whether the first metal trace 50 is short-circuited by using the second metal trace 51 and the test terminal 60 located in the trace test area B2 to test whether the second metal trace 51 is short-circuited. After the test in the routing test area B2 is completed, the display panel mother board can be cut off, and after the cutting, an independent display panel can be obtained. Therefore, the technical problem that the wiring of the display panel is easily irreversibly damaged in the cutting process to influence the subsequent manufacturing process can be avoided, and the technical effect of improving the yield of the display panel is achieved.
It can be known that, in the process of forming the first metal wiring 50 of the non-display area 2021 of the flexible display panel 200 at the first slope 300A, the thickness of the photoresist layer on the metal wiring layer at the first slope 300A is thick, and the photoresist layer cannot be fully exposed and developed to form residual photoresist, so that subsequent metal etching residue is caused, that is, metal residues are easily generated between the first metal wirings 50, and a short circuit exists between the first metal wirings 50.
As can be appreciated, referring to fig. 4, the display panel area B1 is provided with a display panel 200, the display panel 200 including a display area 201 and a non-display area 202, wherein the non-display area 202 includes a non-display area 2021. The schematic cross-sectional structure of the display area 201 and the non-display area 2021 in fig. 4 corresponds to the schematic cross-sectional structure of the display area 201 and the non-display area 2021 shown in fig. 5. Referring to fig. 5, the flexible display panel 200 includes a display region 201 and a non-display region 2021, the display region 201 includes a thin film transistor for driving the light emitting unit to emit light, wherein the thin film transistor exemplarily includes a low temperature polysilicon thin film transistor 40 having a bottom gate structure, and the non-display region 2021 is electrically connected to the flexible circuit board on the back of the flexible display panel 200 through bending. The first metal trace 50 disposed in the non-display area 2021 is electrically connected to the data signal line, the scanning signal line, and the power signal line in the display area 202, and if the first metal trace 50 is short-circuited, the data signal line, the scanning signal line, and the power signal line in the display area 202 cannot obtain a normal display signal through the first metal trace 50, which may cause abnormal trace of the display panel.
The top view of trace test zone B2 shown in figure 4 corresponds to the top view of trace test zone B2 shown in figure 6. It can be known that the trace testing area B2 is prepared simultaneously with the display area 201 and the non-display area 2021 of the flexible display panel 200 disposed in the display panel area B1, and the structure and the film layer are the same as the non-display area 2021. Specifically, referring to fig. 5, the film layers (the flexible substrate 32, the buffer layer 33, the gate insulating layer 34, the capacitor insulating layer 35, and the interlayer insulating layer 36) on the board-carrying sacrificial layer 31 in the substrate film layer 30 in the trace test area B2 correspond to the flexible substrate 32, the buffer layer 33, the gate insulating layer 34, the capacitor insulating layer 35, and the interlayer insulating layer 36 in the non-display area 2021 of the flexible display panel 200. The second slope 300B of the trace test area B2 corresponds to the first slope 300A of the non-display area 2021 of the flexible display panel 200. The second metal trace 51 in the trace test area B2 corresponds to the first metal trace 50 in the non-display area 2021 of the flexible display panel.
In summary, it can be determined whether the first metal trace 50 in the non-display area 2021 on the flexible display panel is short-circuited by detecting whether the second metal trace 51 in the trace testing area B2 is short-circuited, so as to determine whether the trace of the display panel is abnormal.
The specific test principle is as follows: whether or not the second metal wiring 51 is short-circuited can be determined by the resistance value of the second metal wiring 51. The resistance value between the second metal traces 51 is infinite, so that there is no short circuit of the first metal traces 50 on the flexible display panel 200. If the resistance between the second metal traces 51 is not infinite, it is determined that there is an abnormality in the first metal traces 50 on the flexible display panel included in the display panel area B1.
Therefore, according to the technical scheme provided by this embodiment, at least a portion of the second metal wire 51 is located on the second slope surface 300B, the second metal wire 51 is electrically connected to the test terminal 60, the second metal wire 51 and the test terminal 60 are used for testing whether the wires on the display panel are short-circuited, specifically, whether the second metal wire 51 is short-circuited or not can be determined through the resistance values between different test terminals 60, and then whether the first metal wire 50 is short-circuited or not is determined, so that whether the wires on the display panel included in the display panel area are abnormal or not is determined, and the detection efficiency of the abnormal display panel wires is improved.
It can be known that after the test in the trace test area B2 is completed, the trace test area B2 can be cut off, and after the trace test area B2 is cut off, the display panel motherboard can obtain an independent display panel. According to the technical scheme in this embodiment, the non-display area 2021 on the flexible display panel is not tested, but an independent routing test area B2 is provided, so that the test terminal 60 and a short-circuit connection line subsequently provided can be prevented from occupying the area of the non-display area of the flexible display panel.
Optionally, on the basis of the above technical solution, referring to fig. 5, the trace testing area B2 includes a groove located on the substrate film layer 30, and a side surface of the groove is the second slope 300B.
In particular, referring to fig. 5, the first and second slopes 300A, 300B comprise a front slope 301, a middle slope 302, and a rear slope 303, respectively, wherein the grooves comprise a first etched groove, a second etched groove, and a third etched groove, the first etched groove is formed by an etching process, a portion of the interlayer insulating layer 36 is removed corresponding to a main etch of the interlayer insulating layer 36, the first etched groove is flanked by the front slope 301, the front slope 301 has an inclination angle of α. a second etched groove is formed corresponding to an over etch of the interlayer insulating layer 36, the interlayer insulating layer 36 remaining after the main etch is removed, the second etched groove is flanked by the middle slope 302, the middle slope 302 has an inclination angle of β. the third etched groove is formed for the purpose of removing the buffer layer 33, the gate trace insulating layer 34, the capacitive insulating layer 35 arranged in sequence between the interlayer insulating layer 36 and the flexible substrate 32, wherein the flexible substrate 32 comprises a stack of organic and inorganic layers, and the third etched groove may also be formed by removing a portion of the inorganic layer 33, the inorganic layer 302, the metal layer 303, when the third etched groove is formed, the third etched groove, the metal layer may be formed, the metal layer 120 may be removed, the metal layer 120, the metal layer 303, the metal layer 120 may be found in a smaller inclination angle, the area, the.
As can be seen, referring to fig. 5, in the formation of the low temperature polysilicon thin film transistor 40, when forming the source electrode 42 and the drain electrode 43, a via hole 44 needs to be etched in the interlayer insulating layer 36 above the polysilicon active layer 41 to expose the polysilicon active layer 41, so that the source electrode 42 and the drain electrode 43 are electrically connected to the polysilicon active layer 41. In which the etching of the interlayer insulating layer 36 is performed in two steps, i.e., main etching and over-etching, respectively. The etching gas selected by the main etching comprises: CF (compact flash)4And O2. The etching gas selected by the over-etching comprises: CHF5Ar and H2. The difference between the over-etching and the main etching is that the over-etching selects a gas having a higher etching ratio for silicon oxide (the interlayer insulating layer 36 includes a stack of silicon oxide, silicon nitride, and silicon oxide) and the polysilicon active layer 41. Therefore, when the display area 201 of the flexible display panel 200 is etched, the part of the inorganic layer far away from the polysilicon active layer 41 is selectively etched, and the part close to the polysilicon active layer is selectively over-etched, which is beneficial to protecting the insulating layer above the polysilicon active layer 41 from being etched when the insulating layer is etched.
Specifically, referring to fig. 5, the distance L1 between the rear slope 303 and the center slope 302 is greater than or equal to 10 microns and less than or equal to 15 microns.
It can be known that the trace testing region B2 and the display region 201 and the non-display region 2021 of the flexible display panel 200 disposed in the display panel region B1 are prepared at the same time, and the structure and the film layer are the same as the non-display region 2021, if the distance of the interval L1 between the rear slope 303 and the middle slope 302 is greater than 15 micrometers, the area of the inorganic layer retained in the non-display region 2021 is larger, which may cause poor bending performance. The distance L1 between the rear slope 303 and the middle slope 302 is less than 10 μm, so that the distance between the second etched groove and the third etched groove is too short to easily etch the interlayer insulating layer 36 at the middle slope 302, and during the process of forming the third etched groove, a part of the inorganic layer of the flexible substrate 32 cannot be etched, which affects the bending performance of the non-display region 2021.
Optionally, on the basis of the above technical solution, referring to fig. 5 and fig. 6, the second metal routing line 51 covers the second slope surface 300B and the plane 304 connected to the second slope surface 300B, and extends from the second slope surface 300B on a first side of the plane 304 to the second slope surface 300B on a second side opposite to the first side, where the test terminals 60 electrically connected to two adjacent second metal routing lines 51 are different.
As can be known, the metal traces 51, which are insulated, may be one or more of data signal traces, scan signal traces, and power signal traces. In the routing test area B2, the N insulated second metal routing lines 51 correspond to the first metal routing lines 50 in the non-display area 2021 of the flexible display panel 200, and the front slope 301 and the middle slope 302 correspond to the front slope 301 and the middle slope 302 in the non-display area 2021 of the flexible display panel 200, so as to ensure that the structure and the film layer of the routing test area B2 are the same as those of the non-display area 2021 of the flexible display panel 200.
Preferably, the test terminals 60 are located on the same side of the second metal traces 51, in order to match the structural arrangement of the probes of the test equipment, which are generally aligned in the same direction. The test terminal 60 is electrically connected to a probe of a test device to obtain a test signal, so as to complete a test process of whether the routing of the display panel is abnormal.
Optionally, on the basis of the above technical solution, referring to fig. 6, a distance L2 that the second metal trace 51 extends out of the second slope 300 is greater than or equal to 8 micrometers.
The distance L2 that the second metal trace 51 extends out of the second slope 300B is too short to be electrically connected to the subsequent first short-circuit connection line 52 when it is less than 8 μm.
Alternatively, on the basis of the above technical solution, referring to fig. 6, the test terminal 60 includes a first test terminal 61 and a second test terminal 62; the trace test area B2 further includes a first short-circuit connection line 52, the first short-circuit connection line 52 is electrically connected to the odd-numbered second metal traces 510; at least one of the odd second metal traces 510 is electrically connected to the first test terminal 61; a second short circuit connection line 53, wherein the second short circuit connection line 53 is electrically connected to the even number of second metal traces 511; at least one of the second even number of second metal traces 511 is electrically connected to the second test terminal 62.
It can be known that, in the process of forming the second metal traces 51, the position of the metal residue is between two adjacent second metal traces 51, one of the two adjacent second metal traces 51 is the odd second metal trace 510, and the other one is the even second metal trace 511.
The first short circuit connection line 52 is electrically connected to the odd-numbered second metal traces 510, at least one of the odd-numbered second metal traces 510 is electrically connected to the first test terminal 61, the second short circuit connection line 53 is electrically connected to the even-numbered second metal traces 511, and at least one of the even-numbered second metal traces 511 is electrically connected to the second test terminal 62, so that different test signals can be applied to the first test terminal 61 and the second test terminal 62 through a probe of a test device, for example, the first test terminal 61 is applied with a first power supply signal, the second test terminal 62 is applied with a second power supply signal, and then the test device can obtain a resistance value between the first test terminal 61 and the second test terminal 62, that is, obtain a trace resistance value between the odd-numbered second metal traces 510 and the even-numbered second metal traces 511. If the resistance value is infinite, there is no short circuit between the second metal traces 51, and thus there is no short circuit between the first metal traces 50, and it is determined that there is no abnormality in the traces on the flexible display panel. If the resistance between the second metal traces 51 is not infinite, it can be determined that there is a short circuit between the second metal traces 51, and thus a short circuit occurs between the first metal traces 50, and it is determined that there is an abnormality in the traces on the flexible display panel. Therefore, the above technical solution can test whether the wires on the display panel are abnormal by testing the resistance value of the second metal wire 51.
In addition, in the above technical solution, the first short circuit connection line 52 is electrically connected to the odd-numbered second metal lines 510, at least one of the odd-numbered second metal lines 510 is electrically connected to the first test terminal 61, the second short circuit connection line 53 is electrically connected to the even-numbered second metal lines 511, and at least one of the even-numbered second metal lines 511 is electrically connected to the second test terminal 62.
It should be noted that, in fig. 6, it is exemplarily shown that one of the odd-numbered second metal traces 510 is electrically connected to the first test terminal 61, and one of the even-numbered second metal traces 511 is electrically connected to the second test terminal 62.
Preferably, the first short-circuit connection line 52 and the second short-circuit connection line 53 are located on different sides of the second metal trace 51, so as to avoid the problem that circuit faults are easily caused by too high line density due to the fact that the first short-circuit connection line 52 and the second short-circuit connection line 53 are located on the same side of the second metal trace 51.
Optionally, on the basis of the above technical solution, referring to fig. 6, the trace test area B2 further includes a dummy test terminal 63, and the dummy test terminal 63 is not electrically connected to the second metal trace 51.
It can be known, when the test, there are a lot of probes on the test equipment, when the quantity of test terminal 60 is less than the quantity of probe, if do not set up dummy test terminal 63, the probe that does not connect test terminal 63 is in unsettled state, does not have the support, is damaged very easily, consequently, sets up dummy test terminal 63, can protect the probe not damaged.
In the above technical solution, whether a short circuit occurs between the second metal wires 51 is determined by obtaining a resistance value between the first test terminal 61 and the second test terminal 62, so as to determine whether the first metal wire 50 is short-circuited, and further determine whether the wires on the flexible display panel are abnormal. In order to further lock the position of the short circuit between the second metal traces 51, the embodiment of the present invention further provides the following solutions:
optionally, on the basis of the above technical solution, fig. 7 is a top view of another trace testing area in fig. 4, referring to fig. 7, the testing terminal 60 includes a first testing terminal 61 and at least two second testing terminals 62; the trace test area B2 further includes a first short-circuit connection line 52 and at least two second short-circuit connection lines 53, and the odd-numbered second metal traces 510 are electrically connected to the first short-circuit connection line 52; at least one of the odd second metal traces 510 is electrically connected to the first test terminal 61; the second metal wirings 511 are respectively electrically connected with at least two second short-circuit connecting lines 53, and each second metal wiring 511 is electrically connected with one second short-circuit connecting line 53; at least one of the second metal traces 511 electrically connected to each of the second short-circuit connection lines 53 is electrically connected to a second test terminal 62.
Illustratively, the test terminals 60 include two second test terminals 62, and the trace test area B2 further includes two second short-circuit connection lines 53. The resistance between the second test terminal 62 in the trace test first sub-region B21 and the first test terminal 61 is infinite, and there is no short circuit between the second metal traces 51 in the trace test first sub-region B21. If the resistance between the second test terminal 62 in the line test first sub-area B21 and the first test terminal 61 is not infinite, it can be determined that there is a short circuit between the second metal lines 51 in the line test first sub-area B21. Accordingly, the resistance between the second test terminal 62 in the second sub-area B22 and the first test terminal 61 is infinite, and there is no short circuit between the second metal traces 51 in the second sub-area B22. If the resistance between the second test terminal 62 in the second sub-area B22 and the first test terminal 61 is not infinite, it can be determined that there is a short circuit between the second metal traces 51 in the second sub-area B22.
Specifically, in the process of manufacturing the display panel motherboard, the number of the second test terminals 62 included in the test terminal 60 and the number of the second short-circuit connection lines 53 included in the routing test region B251 can be increased according to actual conditions, so as to further lock a more accurate position where a short circuit occurs between the second metal routing lines 51.
Optionally, on the basis of the above technical solution, fig. 8 is a top view of another trace testing area in fig. 4, referring to fig. 8, the testing terminal 60 includes at least two first testing terminals 61 and second testing terminals 62; the trace test area B2 further includes at least two first short-circuit connection lines 52 and second short-circuit connection lines 53, the odd-numbered second metal traces 510 are electrically connected to the at least two first short-circuit connection lines 52, respectively, and each odd-numbered second metal trace 510 is electrically connected to one first short-circuit connection line 62; at least one of the odd second metal traces 510 electrically connected to each first short-circuit connection line 52 is electrically connected to a first test terminal 61; the second metal routing 511 is electrically connected to the second short-circuit connection line 53; at least one of the second even number of second metal traces 511 is electrically connected to the second test terminal 62.
Illustratively, the test terminals 60 include two first test terminals 61, and the trace test area B2 further includes two first short connection lines 52. The resistance between the first test terminal 61 in the first sub-area B21 and the second test terminal 62 is infinite, and there is no short circuit between the second metal traces 51 in the first sub-area B21. If the resistance between the first test terminal 61 in the first sub-area B21 and the second test terminal 62 is not infinite, it can be determined that there is a short circuit between the second metal traces 51 in the first sub-area B21. Accordingly, the resistance between the first test terminal 61 in the second sub-area B22 and the second test terminal 62 is infinite, and there is no short circuit between the second metal traces 51 in the second sub-area B21. If the resistance between the first test terminal 61 and the second test terminal 62 in the second sub-area B22 is not infinite, it can be determined that there is a short circuit between the metal traces 510 in the second sub-area B22.
Specifically, according to actual conditions, the number of the first test terminals 61 included in the test terminal 60 and the number of the first short-circuit connection lines 52 also included in the line test area B2 may be further increased, so as to further lock a more precise position where a short circuit occurs between the second metal lines 51.
It should be noted that, in fig. 6, fig. 7 and fig. 8 of the embodiment of the present invention, only 8 second metal traces 51 are exemplarily shown, and the specific number of the second metal traces 51 is not limited in the embodiment of the present invention.
Because the display panel mother board in the prior art includes the display panel region, usually, the test circuit is manufactured in the non-display region of the display panel included in the display panel region to test whether the wiring on the display panel is short-circuited, wherein the test circuit side needs to be cut after the test is completed, the wiring of the display panel is easily damaged irreversibly in the cutting process, the subsequent manufacturing process is influenced, and the yield of the display panel is reduced.
The display panel mother board provided by the embodiment of the invention is provided with the independent display panel area B1 and the wiring test area B2, the wiring test area B2 and the display area 201 and the non-display area 2021 of the flexible display panel 200 arranged in the display panel area B1 are simultaneously prepared, and the structure and the film layer are the same as the non-display area 2021. Therefore, if the second metal trace 51 in the trace test area B2 is short-circuited, the first metal trace 50 in the non-display area 2021 on the flexible display panel is also short-circuited inevitably; the second metal trace 51 in the trace test area B2 is not shorted, and the first metal trace 50 in the non-display area 2021 on the flexible display panel is also not shorted. Whether the first metal trace 50 is short-circuited is determined by testing the second metal trace 51 and the test terminal 60 located in the trace test area B2 for whether the second metal trace 51 is short-circuited. After the test in the routing test area B2 is completed, the display panel mother board can be cut off, and after the cutting, an independent display panel can be obtained. Therefore, the technical problem that the wiring of the display panel is easily irreversibly damaged in the cutting process to influence the subsequent manufacturing process can be avoided, and the technical effect of improving the yield of the display panel is achieved.
Based on the same inventive concept, the embodiment of the invention also provides a method for detecting abnormal routing of a display panel, which is applied to any display panel motherboard in the technical scheme and comprises the following steps:
step 110, sending a first test signal to the test terminal of the trace test area, detecting the test terminal to obtain a second test signal, and determining whether the second metal trace of the trace test area is short-circuited based on the first test signal and the second test signal, so as to determine whether the first metal trace of the display panel area is short-circuited, and further deducing whether the trace of the display panel is abnormal.
Taking fig. 6 as an example for explanation, a first test signal is sent to the test terminal 60 in the trace test area B2, the test terminal 60 is detected to obtain a second test signal, and based on the first test signal and the second test signal, whether the second metal trace 51 in the trace test area is short-circuited is determined, so as to determine whether the first metal trace in the display panel area is short-circuited, and further, whether the trace of the display panel is abnormal is inferred.
It can be known that, taking fig. 5 as an example for illustration, the trace testing area B2 is prepared at the same time as the display area 201 and the non-display area 2021 of the flexible display panel 200 disposed in the display panel area B1, and the structure and the film layer are the same as the non-display area 2021. Therefore, if the second metal trace 51 in the trace test area B2 is short-circuited, the first metal trace 50 in the non-display area 2021 on the flexible display panel is also short-circuited inevitably; the second metal trace 51 in the trace test area B2 is not shorted, and the first metal trace 50 in the non-display area 2021 on the flexible display panel is also not shorted. In summary, whether the second metal traces 51 in the trace testing area B2 are short-circuited can be detected to determine whether the traces on the display panel 200 are abnormal, so as to improve the efficiency of detecting the abnormal traces on the display panel 200. Specifically, whether the second metal wire 51 is short-circuited or not can be determined through the resistance value between different test terminals 60, so as to determine whether the first metal wire 50 in the display panel area is short-circuited or not, and further determine whether the wires on the display panel included in the display panel area are abnormal or not, so as to improve the detection efficiency of the abnormal wires of the display panel.
It can be known that after the test in the trace test area B2 is completed, the trace test area B2 can be cut off, and after the trace test area B2 is cut off, the display panel motherboard can obtain an independent display panel. According to the technical scheme in this embodiment, the non-display area 2021 on the flexible display panel is not tested, but an independent routing test area B2 is provided, so that the test terminal 60 and a short-circuit connection line subsequently provided can be prevented from occupying the area of the non-display area of the flexible display panel.
Optionally, on the basis of the foregoing technical solution, referring to fig. 9, in step 110, sending a first test signal to a test terminal of a trace test area, detecting the test terminal to obtain a second test signal, and determining whether a second metal of the trace test area is short-circuited based on the first test signal and the second test signal, so as to determine whether the first metal trace of the display panel area is short-circuited includes:
Taking fig. 6 as an example, if the first test terminal 61 is applied with the first power signal, and the second test terminal 62 is applied with the second power signal, the test equipment can obtain the resistance value between the first test terminal 61 and the second test terminal 62, that is, obtain the resistance value between the odd second metal trace 510 and the even second metal trace 511. If the resistance value is infinite, there is no short circuit between the second metal traces 51, so that there is no abnormality in the traces on the flexible display panel included in the display panel area. If the resistance between the second metal traces 51 is not infinite, it can be determined that there is a short circuit between the second metal traces 51, and thus there is an abnormality in the traces on the flexible display panel included in the display panel area. Therefore, the above technical solution can test whether the routing on the display panel included in the display panel area is abnormal by testing the resistance value of the second metal routing 51. Wherein, the infinite resistance value is a preset resistance value.
Optionally, on the basis of the foregoing technical solution, referring to fig. 9, after step 1102, determining that the second metal trace has a short circuit, the method further includes: acquiring an image signal of the second metal wiring through an image sensor;
In the above technical solution, by obtaining the resistance value between the first test terminal 61 and the second test terminal 62, a short circuit between the second metal wires 51 does occur, so that the wires on the flexible display panel are abnormal. In order to further lock the position of the short circuit between the second metal traces 51, an image sensor may collect image signals of the second metal traces, and lock the position of the metal residue between the second metal traces 51, so as to determine the short circuit position of the second metal traces 51 and the abnormal position of the traces on the display panel.
Specifically, before the image signal of the second metal wire is collected by the image sensor, the central point position of the wire test area B2 can be obtained, and according to the central point position of the wire test area B2, the image signal of the second metal wire is collected by the image sensor quickly.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel motherboard, comprising:
the display panel mother board is divided into a display panel area and a wiring test area adjacent to the display panel area;
the substrate film layer comprises a first slope surface and a second slope surface, the metal routing layer comprises a first metal routing and a second metal routing, the first slope surface and the first metal routing are located in the display panel area, at least part of the first metal routing is located on the first slope surface, the second slope surface and the second metal routing are located in the routing test area, at least part of the second metal routing is located on the second slope surface,
the second metal wire is electrically connected with a test terminal, and the second metal wire and the test terminal are used for testing whether the second metal wire is short-circuited or not so as to deduce whether the first metal wire is short-circuited or not.
2. The display panel motherboard according to claim 1, wherein the trace test area comprises a groove on the substrate film layer, and a side surface of the groove is the second slope.
3. The display panel motherboard according to claim 1, wherein the second metal trace covers the second slope and a plane connected to the second slope, and extends from a second slope on a first side of the plane to a second slope on a second side opposite to the first side, wherein two adjacent second metal traces are different in electrically connected test terminal;
preferably, the test terminals are located on the same side of the second metal trace.
4. The display panel motherboard according to claim 3, wherein the distance that the second metal trace extends out of the second slope is greater than or equal to 8 μm.
5. The display panel motherboard according to claim 3, wherein the test terminal includes a first test terminal and a second test terminal;
the wiring test area also comprises a first short circuit connecting wire which is electrically connected with the odd second metal wirings; at least one of the odd second metal wires is electrically connected with the first test terminal;
the second short circuit connecting wire is electrically connected with the even number of second metal wires; at least one of the second metal routing wires is electrically connected with the second test terminal;
preferably, the first short circuit connection line and the second short circuit connection line are located on different sides of the second metal trace.
6. The display panel motherboard of claim 1, wherein the trace test area further comprises dummy test terminals that are not electrically connected to the second metal traces.
7. The display panel motherboard according to claim 5, wherein the test terminals include a first test terminal and at least two second test terminals; the routing test area further comprises a first short circuit connecting line and at least two second short circuit connecting lines, and the odd second metal routing lines are electrically connected with the first short circuit connecting line; at least one of the odd second metal wires is electrically connected with the first test terminal, the even second metal wires are respectively electrically connected with at least two second short circuit connecting lines, and each of the even second metal wires is electrically connected with one second short circuit connecting line; at least one of the second metal wires electrically connected with each second short circuit connecting wire is electrically connected with one second test terminal;
or, the test terminals include at least two of the first test terminals and the second test terminals; the line testing area further comprises at least two first short-circuit connecting lines and at least two second short-circuit connecting lines, the odd-numbered second metal lines are electrically connected with the at least two first short-circuit connecting lines respectively, and each odd-numbered second metal line is electrically connected with one first short-circuit connecting line; at least one of the odd second metal wires electrically connected with each first short circuit connecting wire is electrically connected with one first test terminal; the even number of second metal wires are electrically connected with the second short circuit connecting wire; at least one of the second even number of second metal wires is electrically connected with the second test terminal.
8. A method for detecting abnormal routing of a display panel is applied to the display panel mother board of any one of claims 1 to 7, and is characterized by comprising the following steps:
sending a first test signal to a test terminal of a wiring test area, detecting the test terminal to obtain a second test signal, and determining whether a second metal wiring of the wiring test area is short-circuited based on the first test signal and the second test signal so as to determine whether the first metal wiring of the display panel area is short-circuited and further deduce whether the wiring of the display panel is abnormal.
9. The method for detecting routing anomaly of a display panel according to claim 8, wherein sending a first test signal to a test terminal of a routing test area, detecting the test terminal to obtain a second test signal, and determining whether the second metal routing layer of the routing test area is short-circuited based on the first test signal and the second test signal to determine whether the first metal routing of the display panel area is short-circuited comprises:
determining a resistance value between different ones of the test terminals based on the first test signal and the second test signal;
and if the resistance values between different test terminals are not equal to the preset resistance value, determining the second metal wiring short circuit so as to determine the first metal wiring short circuit in the display panel area.
10. The method for detecting routing anomaly of a display panel according to claim 9, wherein after determining that the second metal routing has a short circuit, the method further comprises: acquiring an image signal of the second metal wiring through an image sensor;
and determining the short circuit position of the second metal wire based on the image signal of the second metal wire, and further deducing the short circuit position of the first metal wire in the display panel area.
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